PH12018000380A1 - Semiconductor die sorting and test handler system and method therefor - Google Patents
Semiconductor die sorting and test handler system and method therefor Download PDFInfo
- Publication number
- PH12018000380A1 PH12018000380A1 PH12018000380A PH12018000380A PH12018000380A1 PH 12018000380 A1 PH12018000380 A1 PH 12018000380A1 PH 12018000380 A PH12018000380 A PH 12018000380A PH 12018000380 A PH12018000380 A PH 12018000380A PH 12018000380 A1 PH12018000380 A1 PH 12018000380A1
- Authority
- PH
- Philippines
- Prior art keywords
- test
- station
- semiconductor die
- die
- sorting
- Prior art date
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000003032 molecular docking Methods 0.000 claims abstract description 24
- 238000007689 inspection Methods 0.000 claims abstract description 16
- 238000010330 laser marking Methods 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 5
- 241001133184 Colletotrichum agaves Species 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009877 rendering Methods 0.000 description 2
- XBWAZCLHZCFCGK-UHFFFAOYSA-N 7-chloro-1-methyl-5-phenyl-3,4-dihydro-2h-1,4-benzodiazepin-1-ium;chloride Chemical compound [Cl-].C12=CC(Cl)=CC=C2[NH+](C)CCN=C1C1=CC=CC=C1 XBWAZCLHZCFCGK-UHFFFAOYSA-N 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67271—Sorting devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67775—Docking arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
Abstract
The present invention relates to a system and method for semiconductor die sorting and test handler (101), comprising of at least one pick and tape system (103) and at least one hard docking test system (105), whereby said pick and tape system (103) comprises of at least one turret (107) with at least one input station (117), at least one die alignment station (118), at least one die physical inspection station (119) and at least one tape and reel station (121). The hard docking test system (105) comprises of at least one test site (109) and at least one test arm (111), whereby said die is transferred back and forth from the pick and tape system (103) to the hard docking test station (105) through at least one bridging system (113).
Description
: using at least one pick-up head (not shown) or from at least one wafer using at least - one flipper (not shown). There is provided at least one unit alignment module (120) @ with vision inspection station, the module (120) is to align the units/dies before being placed on buffer cavity (not shown). Also, there is provided at least one purge bucket - to dispose any units/dies that fails in inspection. The turret (107) comprises of a - plurality of pick-up heads, at least one direct drive rotary motor, at least one rotary = blade and at least one vertical motion pusher, whereby said pick-up heads are placed © at the circumference of said rotary blade.
The hard docking test system (105) comprises of at least one test site (109) and at least one test arm (111). The test arm (111) typically picks the dies to the test site to be performed electrical test. After the test is done, die will be placed in a stencil plate (not shown), and then unit transfer arm (not shown) will pick and place to buffer cavity. Referring to FIG. 3, there is shown the test site (109) further comprises of at least one vision camera (123) to inspect at least one contactor pin (125) positions on the test plate to calculate the offset between pins of said die and the pins of said contactor to facilitate alignment of position between both set of pins.
It can be appreciated that after the system (101) can further be bridged to at least one SMT or wire bond station in order to perform packaging to the die after the hard docking station (105) or pick and tape system (103).
:
Referring to FIG. 4 there is shown an exemplary method process flow of a ~ method for semiconductor die sorting and test handler (2), comprising the steps of: ° performing an assembly operation from a semiconductor wafer (21), the assembly . operation is done without prior performing wafer probing; then performing die - sorting to the assembly operation (22); the die sorting further comprising step of - performing electrical test and vision inspection to the semiconductor die (23), the © electrical test and vision inspection comprising hard docking test and soft docking test. =
While, the die sorting comprising automated optical inspection.
As mentioned in supra, the assembly operation comprising but not limited to, back grinding, coating, laser marking, laser grooving, and dicing.
While the preferred embodiment of the present invention and its advantages have been disclosed in the above Detailed Description, the invention is not limited thereto but only by the scope of the appended claim.
Sr Co
Len Ti fo | p us > 1 ~
SEMICONDUCTOR DIE SORTING AND TEST HANDLER SYSTEM AND =
METHOD THEREFOR = 1. TECHNICAL FIELD OF THE INVENTION .
The present invention relates to a system and method for semiconductor die fat fd sorting and test handler, comprising of at least one pick and tape system and at least one hard docking test system, whereby said pick and tape system comprises of at least one turret with at least one input station, at least one die alignment station, at least one die physical sorting station and at least one tape and reel station. The hard docking test system comprises of at least one test site and at least one test arm, whereby said die is transferred back and forth between the pick and tape system and the hard docking test station through at least one bridging system. 2. BACKGROUND OF THE INVENTION
Semiconductor dies are usually being handled before being shipped out to another location for device packaging. The dies are usually transferred in the form of reels or wafer. Dies in reels are usually packed in tapes, sealed and reeled before being transported to the handling site. Dies in wafer usually come in the form of already diced dies before being used in the handling site. The handling task, usually done by one machine may involve picking and placing said dies, operating in many different
’ - stations such as die sorting station, die tape and reel and many others. Examples of dies are WLCSP and WLBGA. After the handling process, dies are using being @ shipped out. Problems from the above implementation are many. Dies which are being ) shipped out are having many types of defects such as performance defect or physical “ defect, caused during the handling process. =
Some past solutions were created solve the above problems. In certain handling o machines, wafer probe is done to the dies before they are being grinded, diced, and sorted. No further test is done to the dies those processes, rendering possibility of dies that are being damaged in those processes, still rendering high amount of damaged dies being shipped out.
The test station is transferred to be done with the sorting station to reduce handling risk before packaging. Usually the cost to purchase and fabricate the machines is high because it involves fabricating two or more machines to perform the whole process. The time needed for the operators to unload and load the dies from and to each machine is much more and can also lead to human errors.
It would hence be extremely advantageous if the above shortcoming is alleviated by having a system for semiconductor die sorting and test handler, comprising of at least one pick and tape system and at least one hard docking test system, further comprising a bridging system.
3. SUMMARY OF THE INVENTION ft
Accordingly, it is the primary aim of the present invention to provide a system ~ for semiconductor die sorting and test handler which is a more cost effective solution w due to the invention’s capability to perform tasks which was required by more than ~*~ two equipment in the past. =
It is yet a further object of the present invention to provide a system for semiconductor die sorting and test handler which is time-saving because dies are only required to be loaded to the system once instead of multiple loadings in the prior arts.
It is yet a further object of the present invention to provide a system for semiconductor die sorting and test handler which reduces the steps in process of handling and testing dies in the production line.
It is yet a further object of the present invention to provide a system for semiconductor die sorting and] test handler which provides higher product yield rate as the dies are tested prior to being shipped out.
It is yet a further object of the present invention to provide a system for semiconductor die sorting and test handler which provides higher output quality as the dies are tested before taping and packaging.
: -
It is yet a further object of the present invention to provide a system for = fd semiconductor die sorting and test handler which reduces the cost per die. =
Additional objects of the invention will become apparent with an © understanding of the followling detailed description of the invention or upon n employment of the invention in actual practice. =
According to the preferred embodiment of the present invention the following - is provided:
A system for semiconductor die sorting and test handler (101), comprising of: at least one pick and tape system (103) comprising of at least one turret (107) with at least one station, and at least one flipper; characterized in that said system (101) further comprises of at least one hard docking test system (105); said hard docking test system (105) comprises of at least one test site (109) and atleast one test arm (111); and
= said system (101) er comprises of at least one bridging system (113) to ~. transfer said die back and forth between said pick and tape system (103) and the hard ~ docking test station (105). on
An aspect of the present invention there is provided, de 5 A method for semiconductor die sorting and test handler (2), comprising the o steps of: performing an assembly operation from a semiconductor wafer (21); and performing die sorting to the assembly operation (22); characterized in that the die sorting further domprising step of performing electrical test and vision inspection to the semiconductor die (23); and the assembly operation is done without prior performing wafer probing. 4. BRIEF DESCRIPTION OF THE DRAWINGS
Other aspect of the present invention and their advantages will be discerned after studying the Detailed Description in conjunction with the accompanying drawings in which:
6 ~
FIG. 1 shows an exemplary block diagram of the present invention disposed at a test operation which is capable of performing a plurality of semiconductor die tests = (such as electrical test, hard docking test), AOI (automated optical inspection), and - tape and reel. - fo
FIG. 2 shows a block diagram of the current invention comprising the pick and = tape system, hard docking test system, and bridging system. -
FIG. 3 shows the components of the test site, to perform alignment between contactor pin and die pin.
FIG. 4 shows an exemplary method process flow of the present invention. 5. DETAILED DESCRIPTION OF THE DRAWINGS
In the following detailed description, numerous specific details are set forth in order to provide a thorough lunderstanding of the invention. However, it will be understood by the person having ordinary skill in the art that the invention may be practised without these specific details. In other instances, well known methods, procedures and/or components have not been described in detail so as not to obscure the invention.
The invention will be more clearly understood from the following description of = the embodiments thereof, given by way of example only with reference to the ® accompanying drawings, which are not drawn to scale. ;
Referring to FIG. 1 there is shown an exemplary block diagram of the present - invention, a semiconductor die sorting and test handler (101) disposed at a test = operation after an assembly operation of a semiconductor wafer. The assembly os operation comprising steps, but not limited to, back grinding, coating, laser marking, laser grooving, and dicing/sawing. The semiconductor die sorting and test handler (10) is capable of performing a plurality of semiconductor die tests (such as electrical test, hard docking test), AOI (automated optical inspection), and tape and reel.
Referring to FIG. 2, there is shown the present invention relates to a system for semiconductor die sorting and test handler (101), comprising of at least one pick and tape system (103), at least one hard docking test system (105) and at least one bridging system (113) to transfer said die back and forth between said pick and tape system (103) and the hard docking test station (105).
The pick and tape system (103) comprises of at least one turret (107) with at least one station. The turret (107) of the pick and tape system (103) comprises of at least one input station (117), at least one die alignment station (118), at least one die physical inspection station (119), at least one tape and reel station (121) and at least one laser marking station (not shown). The input station (117) receives die from at least one reel
Claims (10)
1. A system for semiconductor die sorting and test handler (101), comprising of: oe at least one pick and tape system (103) comprising of at least one turret (107) with at least one station, and at least one flipper; = characterized in that = said system (101) further comprises of at least one hard docking test system (105); said hard docking test system (105) comprises of at least one test site (109) and at least one test arm (111); and said system (101) further comprises of at least one bridging system (113) to transfer said die back and forth between said pick and tape system (103) and the hard docking test station (105).
2. The system for semiconductor die sorting and test handler (101) as claimed in Claim 1, wherein said turret (107) comprises of at least one input station (117), at least one die alignment station (118), at least one die physical inspection station (119) and at least one tape and reel station (121).
3. The system for semiconductor die sorting and test handler (101) as claimed in = Claim 1, wherein said turret (107) comprises of at least one input station (117), at least © one die alignment station (118), at least one die physical inspection station (119), at ’ least one tape and reel station (121) and at least one laser marking station. -
4. The system for semiconductor die sorting and test handler (101) as claimed in = Claim 2 or 3, wherein said input station (117) receives die from at least one reel using ) i at least one pick-up head (not shown) or from at least one wafer using at least one flipper (not shown).
5. The system for semiconductor die sorting and test handler (101) as claimed in Claim 1, wherein said turret (107) comprises of a plurality of pick-up heads, at least one direct drive rotary motor, at least one rotary blade and at least one vertical motion pusher, whereby said pick-up heads are placed at the circumference of said rotary blade.
6. The system for semiconductor die sorting and test handler (101) as claimed in Claim 1, wherein said test site (109) further comprises of at least one vision camera (123) to inspect at least one contactor pin (125) positions on the test plate to calculate the offset between pins of said die and the pins of said contactor to facilitate alignment of position between both set of pins.
12 =
7. A method for semiconductor die sorting and test handler (2), comprising the - [a steps of: = performing an assembly operation from a semiconductor wafer (21); and @ performing die sorting to the assembly operation (22); oy characterized in that ed the die sorting further comprising step of performing electrical test and vision inspection to the semiconductor die (23); and the assembly operation is done without prior performing wafer probing.
8. The method for semiconductor die sorting and test handler (2) as claimed in Claim 7 wherein the electrical test and vision inspection comprising hard docking test and soft docking test.
9. The method for semiconductor die sorting and test handler (2) as claimed in Claim 7 wherein the assembly operation comprising back grinding, coating, laser marking, laser grooving, dicing, and AOI (Automated Optical Inspection).
10. The method for semiconductor die sorting and test handler (2) as claimed in Claim 7 wherein the die sorting comprising automated optical inspection.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| MYPI2017704526A MY186082A (en) | 2017-11-27 | 2017-11-27 | Semiconductor die sorting and test handler system and method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| PH12018000380A1 true PH12018000380A1 (en) | 2019-06-24 |
Family
ID=66845598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PH12018000380A PH12018000380A1 (en) | 2017-11-27 | 2018-11-16 | Semiconductor die sorting and test handler system and method therefor |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR20190062240A (en) |
| MY (1) | MY186082A (en) |
| PH (1) | PH12018000380A1 (en) |
| TW (2) | TWM589361U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111725104B (en) * | 2020-06-22 | 2023-02-17 | 宁波芯健半导体有限公司 | Method, device and equipment for braiding wafer |
-
2017
- 2017-11-27 MY MYPI2017704526A patent/MY186082A/en unknown
-
2018
- 2018-11-16 PH PH12018000380A patent/PH12018000380A1/en unknown
- 2018-11-19 TW TW108213549U patent/TWM589361U/en unknown
- 2018-11-19 TW TW107140970A patent/TW201926500A/en unknown
- 2018-11-23 KR KR1020180146229A patent/KR20190062240A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| TWM589361U (en) | 2020-01-11 |
| KR20190062240A (en) | 2019-06-05 |
| TW201926500A (en) | 2019-07-01 |
| MY186082A (en) | 2021-06-19 |
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