NZ203792A

NZ203792A - Tdm communications system synchronisation apparatus:highway connections to equalise delays

Info

Publication number: NZ203792A
Application number: NZ203792A
Authority: NZ
Inventors: C-G E Perntz; S G Roos
Original assignee: Ericsson Telefon Ab L M
Priority date: 1982-04-26
Filing date: 1983-04-06
Publication date: 1986-07-11
Also published as: IT8320760A0; DK159232C; US4646291A; ES8406820A1; IE54315B1; GR77397B; IE830924L; MX153972A; KR860001259B1; YU93283A; FI834615A; IN159045B; FI75704B; ES521815A0; AU1477283A; EP0105902B1; AU552579B2; EP0105902A1; DZ533A1; DK159232B

Description

<div class="application article clearfix" id="description"> 2 03792 Priority Date(s): Q&. A Complete Specification Filed: 6..^3. Class: • ■ • * • [fV'iuL'W Publication Oate: P.O. Jot/mat, No: .. S.PJ&. ~6 APR 1983 , NEW ZEALAND \ I tp . / PATENTS ACT, ]953 - No.: Date: COMPLETE SPECIFICATION "SYNCHRONISATION APPARATUS IN TRANSMITTING INFORMATION ON A SIMPLEX BUS11 XXWe, TELEFONAKTIBBOLAGET L M ERICSSON, a company organized under the lavs of Sweden, of S-126 25 Stockholm, Sweden hereby declare the invention for which we pray that a patent may be granted to anc* method by which it is to be performed, to be particularly described in and by the following statement: - - 1 - ("followed by page -la-) J..^f.^»^rtW9*r^^ -\a- 203792 TECHNICAL FIELD The invention relates to a synchronization apparatus in a telecommunication system of the time division multiplex (TDM) type in which information^ transmitted in assigned time slots in one-way data transmission between a plurality of equal transmitter/receiver modules con-1 5 nected to a common bus. ^ BACKGROUND ART In order to achieve data transmission correctly in time, signals for synchronizing between transmitter and receiver must also be sent out \ on the bus. In known apparatus 10 ——— relating to the regional processor bus in the AXE 110 telephone exchange, separate clock equipment is utilized for the bus, which means that the information is intentionally delayed and clocked out on the bus with the aid of the separate clock signal unit. DISCLOSURE OF INVENTION 15 For a combination of transmitter and receiver in the same module, in the known apparatus there are required separate clock signals and possibly clock oscillators in both transmitters and receivers for synchronizing towards the bus. This results in delay in the information transmission, poor capacity utilization on the bus and a com-20 plicated hardware structure. Furthermore, it is difficult to achieve great reliability with central feeding of clock signals. The apparatus solving the mentioned problem is characterized by the claims,and consists of a bus intended for simplex information transmission connected to a plurality of modules, each of which includes 25 a transmitter and a receiver. An arbitrarily selected module cowg^t /yf»? /tutes the master module, and sends synchronizing pulses as w^t'l as data to the other modules (slave modules). The synchronizing pulses 13 FEB 1986 m 2 0379 7 2 are used to establish time slots in the TDM system. With respect to the transmission direction/, all the transmitters are successively connected to the starting section of the bus, while all receivers are connected to the final section thereof in the same order 5 as the transmitters. This enables disposing the starting and final sections in parallel conductors in the same cable. The intermediate section of the bus, extending from the last connected transmitter to the first connected receiver is dimensioned such that the delay of information through the bus for transmission from transmitter to re-10 ceiver in one and the same module, in accordance with the example below, will'be at Least one time slot or more. The time delay can also be less than one time slot in certain cases. Since the synchronizing pulse and the data information travel the same way, each of the slave modules is synchronized to assume a relative phase position corre-15 sponriing to its position on the bus. Data is-thus clocked-out in the same local clock phase irrespective of the transmitter module, and is clocked-in in the next local clock phase irrespective of receiver module. The one time slot delay through the bus allows the same clock oscillator to be utilized for both transmitter and receiver in a module. 20 The arrangement and dimensioning of the bus enables interferencefree transmission of first information between an arbitrarily selected module pair, and second information between a second arbitrarily selected module pair while using two mutually adjacent time slots, and so on until all time slots are occupied. 25 The advantages of the apparatus in accordance with the invention over known apparatus are: Better bus capacity utilization is obtained by the implementation of the bus and the synchronizing method. No re-clocking unit on the bus intermediate section is necessary. 30 Transmitter and receiver clocks are the same for the respective module, irrespective of whether the module is a master or a slave, i.e. master and slave are alike, unified hardware thus being obtained. 2 037 92 DESCRIPTION OF FIGURES The apparatus in accordance with the invention is described in detail below with the aid of an embodiment and with reference to the appended drawing, on which Figure 1 is a simplified block diagram of the apparatus in accordance with the invention, 5 Figure 2 is a block diagram of the transmitter/receiver equipment included in the respective module and, Figure 3 is a timing chart illustrating how the data information and synchronizing pulses occur in time during transmission through the bus between transmitter and receiver. PREFERRED EMBODIMENT 10 .As mentioned, the bus is divided into three sections, a first section B1 connected to the transmitter outputs of the modules, a second intermediate section B2 and a third final section B3, which is connected to the receiver inputs of the modules. The bus is adapted for a high transmission rate, e.g. 8 MHz bus clocking 15 frequency. If the time delay is selected as one time slot, it will be 125 ns, which is comparatively short in relation to a whole frame. As mentioned previously, a given time delay is decided, e.g. corresponding to one time slot between the transmitter and receiver in the same module. The same time delay applies to arbitrary transmission, 20 i.e. irrespective of what module is the transmitter and what module is the receiver, by a synchronizing pulse sent from the master module being transmitted parallel to the data signals from the respective transmitter module. Said time delay is determined by the different sections B1, B2, B3 of the bus. The sections B1 and B3 consist of 25 parallel conductors in the same cable, and give a fixed time delay depending on the number of modules comprising both transmitter and receiver that are connected to the bus. Since the number of modules can vary, and thereby the fixed part of the time delay, the intermediate section B2 of the bus is variable and is adjustable in length so that 30 the desired combined time delay of at least one time slot is always achieved indepent of the fixed time delay in the bus section B1 and B3. * 2 4 •J The cable length from transmitter to bus and from bus to receiver is also predetermined. The bus nay be a cable bus with cable contacts as connection means. As will be seen from Figure % a number of modules A-N are connected 5 to a common bus, each module containing a transmitter S and a receiver R. The bus is divided into three sections, a first section B1 at the start of the bus to which all transmitters S are connected, a second section B2 consisting of the intermediate section of the bus, and a third section B2 which is the final section to which all receivers R 10 are connected. The transmitters are connected to the bus in a definite order and the receivers are connected to the bus in this same order. In order to achieve the object of the invention, namely the provision of a synchronization method allowing exchange of information between arbitrary transmitters and receivers in adjacent time slots-without 15 play in time, the apparatus in accordance with the invention also includes equipment in said modules A-N, apart from said bus arrangement. As will be seen from Figure 2, each module A-N includes a time slot memory TM of the INTEL 2148 type, in which data from and to the bus is respectively read in and read out under control by signals from a 20 continuously stepping,time slot counter TSC of the type 74LD161 and a control memory CM of the type INTEL 2148. The time slot counter is controlled by a local clock oscillator CL of the type MOTOROLA MC 4024, associated with the module and common to transmitter and receiver, this oscillator also generating synchronization pulses FS to the bus, 25 and also generating remaining internal control signals. The control memory CM is conventionally controlled by a microprocessor CP of the type MOTOROLA 6801, not shown in the Figure. For transmission to the bus, the control memory CM sends addresses to the time slot memory TM on clocking from the time slot counter, so 30 that data can change time slot in the TDM system. The address pointing out the cell in the memory TM from which data is to be read out during the appropriate time slot. The data outputs from the memory TM are connected to the inputs on a latch circuit L1 in the form of a D flipflop of the type 74LS373, in which data is stored for feeding 203792 5 out in the right moment to the inputs on a bus transmitter BS of the type AMD 26LS31. Feeding out data from the Latch circuit L1 is done under the controL of an internal cLock signaL CS continuousLy fed out via the time sLot counter TSC. A signal TE (time slot enable) is fed 5 from the control memory CM via the Latch circuit to an input of the bus transmitter, thus controlling the feed-out of synchronization pulse and data from the bus transmitter BS to the bus. The oscillator t ^ CL delivers a synchronization pulse to the bus once per frame via the i - time slot counter TSC to synchronize the time slots. The frame syn-10 chrcnization puLse FS is transferred in time slot 0 (zero) to one input on an AND circuit 01, the other input of which obtains the continuousLy sent internal clock signaL from an output of the time slot I counter TSC, which is the same signaL controlling the feed-out of data from the latch circuit L1.The AND circuit is activated once per 15 frame for sending the synchronization puLse to be bus transmitter. It is only the module selected as master which delivers synchronization pulses to the bus. Reception of data and synchronization pulses from the bus to the module takes places continuously in a bus receiver BR of the type AMD 26LS32, which sends from its outputs data to the in-20 puts of a further Latch circuit L2, a D-flipflop of the type 74LS373. The information is clocked into the Latch circuit under control of the internal clock signaL CS, which is the same signaL cLocking out data to the bus, but since the information through the bus is delayed by one time slot the internal clock signaL in this case is inverted by an 25 inverting circuit I, the same basic clock signaL thus controlLing both clocking-out and clocking-in of data respectively to and from the bus. The phase relationship between the clock signals is dependent on the size of the deLay through the bus. The Latch circuit L2 has outputs connected to inputs on the time slot memory TM. When the information 30 in the Latch circuit is to be fed into the time slot memory TM/ the latter is controlled by a signaL DS (Data Select) from the control me-^ mory CM to the latch circuit L2, the clock signals from the time slot counter TSC then serving as pointer for writning in the correct address in the memory. 35 The frame synchronization puLse sent through the bus is taken from an output on the bus receiver BR and applied to a first input on a 203752 6 phase comparator PC of the type MC 4044. The frame synchronization pulse FS generated by the Local oscillator CL and fed out via the time slot counter is applied to a second input on the phase comparator. The latter thus conventionally makes a comparison between the phase posi-5 tion of the locally generated synchronizing pulse and the synchronizing pulse transmitted through the bus. The comparison result is a voltage U, which is utilized to control the frequency of the clock oscillator CL so that it is always stable. The clock frequency increases and de- f ■ ^ I' creases in response to how the relative phase position between the 10 both signals varies, and thereby the resulting voltage U. Figure 3 is a timing chart illustrating how a module A transmits in a v < time slot and receives its own information in the receiver one time V,' slot later. As previously mentioned, the inverted transmitter clock signal shouLd be used for enabling clocking the received information 15 in the middle of the data puLse. The chart also illustrates how the frame.synchronization pulse FS is displaced in time from the transmitter in a master module B through the bus to the receivers A, B and C. As will be seen in Figure 2, the slave receiver A receives this frame synchronization pulse and makes a phase comparison with its own local clock. If the phase position is not correct, the phase is controlled so that the synchronization pulse will appear in the middle of its own time slot 0 (zero). As will further be seen from Figure 3, the relative phase positions are the same all the time- The delay is one time slot, as will be seen. The instant when the information will start to be transmitted and received in the different modules is dependent on the positions of the transmitters and receivers on the bus. Since all the receivers come after the transmitters in respect of delay, it is thus possible to begin transmission in one time slot before transmitted information from the preceding time slot has been received. This is an advantage which is not possible to achieve in a ring bus, for example. C i A 25 </div>

Claims

<div class="application article clearfix printTableText" id="claims"> 7 203792 WHAT WE CLAIM IS:

1. A time division multiplex telecommunication system synchronisation apparatus, in which information is transmitted in assigned time slots in one-way data transmission between a plurality of equal transmitter/receiver modules connected to a common bus, for enabling transmission through the bus from arbitrary transmitters to arbitrary receivers in adjacent time slots without time difference between transmission sequences in respective time slots, characterized in that: there is a first bus section to which said transmitters are connected in a given order; the distance between each transmitter output and the associated first bus section input is predetermined so that a fixed time delay is obtained which is the same for each module; the total fixed time delay through said first bus section is dependent on the number of module transmitters connected to the first bus section; there is a final bus section to which said receivers are connected in the same order as the transmitters; the distance between the associated final bus section output and each receiver input is predetermined so that a fixed time delay is obtained which is the same for each module; the total fixed time delay through said final bus section is dependent on the number of module receivers connected to the final bus section; there is an intermediate bus section having variable length and extending from the last connected transmitter to the first connected receiver, the length of said intermediate section, in relation to the 8 203752 size of said fixed time delays, being adjusted to give a selectable, predetermined total time delay between transmitter and receiver in the same module; each of said modules contains: (a) a clock signal unit common to its own transmitter and receiver, said clock signal unit sending, apart from internal clock signals each time the module is selected as master, a frame synchronization pulse once per frame to the input of said bus via a bus transmitter; said frame synchronizing pulse for synchronizing remaining slave modules is sent in parallel with the data information from the respective transmitter; (b) a time slot memory for storing data which is written in from and read out to the bus under control of control signals; (c) a control memory connected to the address inputs of the memory which provides at least some control signals to control said time slot memory; (d) a time slot counter into which clock signals are fed to produce further control signals to control said time slot memory; (e) a first latch circuit through which the data information is read out to the bus transmitter and the bus; (f) a bus receiver and a second latch circuit through which data is written in to the memory from the bus; said read-out and write-in respectively being controlled by signals from the common clock signal unit.

2. Apparatus as claimed in claim 1, characterised in that said control signals from the clock signal unit for reading-out and writing-in of information to and from the bus consists of clock signals from the same basic clock signal in a given phase relatioeffnT&^ftp^&a.ch \ 9 203792 other

3. Apparatus as claimed in claim 1, characterized in that said first bus section and said final bus section are arranged on parallel conductors in the same cable.

4. Apparatus as claimed in claim 1, characterized in that a phase comparator in each module receives the frame synchronization signal from the bus and compares it with the locally generated frame synchronization pulse, the difference being given as a voltage which corrects the phase position of the common clock signal unit.

5. A time division multiplex telecommunication system synchronisation apparatus substantially as hereinbefore described with reference to the accompanying drawings. by ma/ i neir Muinorised Agents, A.J. PARK & SON </div>