KR0149644B1 - Communication line match device of full electronic telephone exchanger - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an electronic switch, and in particular, the jitter of time slots generated at ports having different timings is eliminated due to the distance difference between blocks during data static pressure between the block of the telephone line so that the matching between blocks is independent of the cable length. An apparatus for removing inter-block timeslot jitter of an exchanger to be kept constant.

According to the present invention, a timing signal of latching a data signal using a clock signal and a synchronization signal used for data matching in a central data link and a selection signal generated according to a local clock of a space switch after temporary storage of the latched data signal. By matching the phase with respect to the phase of the data signal delayed according to the length of the to provide reliability in the matching between the telephone line block of the electronic switchboard.

Description

Monetary line matching device of electronic exchange

1 is a block diagram of a currency matching system in a conventional electronic switch.

FIG. 2 is a timing diagram of data for currency path matching in the electronic switchboard shown in FIG. 1. FIG.

Figure 3 is a block diagram of the configuration of the currency line matching device of the electronic switching system according to the present invention.

4 is a timing diagram of data transmission for synchronizing synchronization by removing inter-block timeslots at different timings in the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

10A-10D: Access Switching System 11A-11D: Time Switch and Link

20: interconnection network system 21A-21D: central data link

30: space switch 40: register

50A-50D: MUX 60: Block Matching Timing Supply Unit

70 Local Timing Supply

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an all-electronic exchange, and in particular, the jitter of timeslots generated at ports having different timings is eliminated due to the distance difference between blocks in data line matching, so that the matching between blocks is independent of the cable length. An apparatus for removing inter-block timeslot jitter in an electronic exchanger is kept constant.

As can be seen from the accompanying drawings, Figure 1, an access switching system (10A-10D) consisting of a time switch and a link (11A-11D), and a central data link (21A-). 21D) and the interconnection network system 20 consisting of the space switch 30. The access switching system (Access Switching Subsystem: 10A-10D) is a subsystem that is responsible for external matching of an electronic switch such as a subscriber or a trunk. Interconnection Network Subsystem 20 is a subsystem in which resources are provided for interconnecting the access switching systems 10A-10D.

At this time, the NES (Network Synchronization) signal applied to the interconnection network system 20 is a signal supplied to match the timing synchronization between the entire telephone line system and the network.

Where the inter-block matching occurs in the currency line matching device of the conventional all-electronic switching system having the functions as described above, the time switch and the link 11A-11D in the access switching system 10A-10D, and the interconnection network In the embodiment, since the data is generated at the central data link 21A-21D and the space switch 30 in the system 20, the central data link 21A-21D and the space switch 30 in the interconnect network system 20 may be generated. A timing synchronization for matching data transmitted / received will now be described with reference to FIG. 2.

Predetermined data signals for matching the time switches in the access switching system 10A-10D and the communication path system output from the links 21A-21D, which are formed in a predetermined number, according to the capacity of the all-electronic exchange, are mutually connected through the data bus. When applied to the central data link 21A-21D of the connection network system 20, the central data link 21A-21D can know the data applied from the time switch and the link 21A-21D in FIG. As shown, the space switch 30 is synchronized with the data CDL0, CDL2, CDL3, and CDL4 having the same phases TS0, TS1, TS2 according to the clock of the NES signal applied from the outside in a cycle of a specific frame FP2. Is applied to the Rx side to match data transmission / reception between the central data link 21A-21D and the space switch 30.

In the conventional electronic switch as described above, when the cable gap between the central data link and the space switch is inconsistent, the delay time of the transmitted data is 5 ns / m according to the length of the cable. Timeslot jitter applied to the switch can be up to 50ns. Therefore, if the central data link has different timings due to cable differences, the data output from the central data link is transmitted in different phases in the frame of the synchronization signal applied from the NES. There was a problem that can not be matched for.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and its object is to eliminate the jitter in the time slots generated by the transmission cable due to the distance difference between the blocks in the matching of the telephone line of the electronic switchboard, thereby making it reliable for data transmission and reception of the telephone line. To provide.

A feature of the present invention for achieving the above object is a central data link for receiving a data signal applied from an access switching system in accordance with the clock of the NES signal applied from the outside, and from the central data link in an all-electronic switch. A block switch having a space switch for matching applied channel data, and outputting a predetermined latch signal for latching a signal output from the central data link according to a clock signal and a synchronization signal applied from the central data link; A timing generator, a register for storing a data signal applied from the central data link according to a latch signal applied from the block matching timing generator, and a signal output from the register according to a local clock applied from the space switch. God to choose And a mux for synchronizing the phase of the data signal applied from the register according to the selection signal applied from the local generating means and applying the mux to the space switch side through the highway. Provides a coin-path matching device for an electronic switchgear.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of the coincidence matching system of the electronic switching system according to the present invention. FIG. 4 is a block diagram showing the timing of inter-block timing at different timings according to the present invention shown in FIG. A timing diagram of data transfer.

As can be seen in FIG. 3, the interconnection network 20 is a central data link 21A-21D, a register 40, and a mux 50A-50D in the telephone system of the electronic switching system according to the present invention. And a block matching timing supply unit 60 and a local timing supply unit 70. The central data link 21A-21D synchronizes a data signal applied from an access switching system to a frame period of an NES signal applied from the outside. It is matched and applied to the space switch side. The register 40 latches a predetermined data signal CDLn applied at the central data link 21A-21D at a predetermined time slot TSm of the latch signal applied from the block matching timing supply unit 60. The mux 50A-50D multiplexes the data signal latched in the register 40 and sequentially selects the data signal applied from the register 40 once in accordance with the selection signal applied from the local timing supply unit 70. It is applied to the space switch side via the highway (HWY0-HWY3). The block matching timing supply unit 60 matches data signals output from the central data link 21A-21D according to the clock signal CK of the NES signal applied from the central data link 21A-21D and the synchronization signal SY. Outputs a latch signal for The local timing supply unit 70 is output from the register 40 in accordance with a clock that the space switch outputs a data signal input from the central data link 21A-21D to synchronize its local clock input from the NES. Generates a data selection signal.

Referring to the operation for inter-block data matching of the present invention having the function as described above is as follows.

When a predetermined data signal from the access switching system is applied to the central data link 21A-21D side, the central data link 21A-21D is applied with the applied data signal CDL0 Data0 as shown in FIG. And CDL1 Data1, CDL2 Data2, and CDL3 Data3 are applied to the register 40 side in synchronization with a specific frame FP of the NES signal applied from the outside. The register 40 includes the clock signals CK0, 1, 2, 3 of the NES signal and the synchronization signals SY0, SY1, which are applied from the central data link 21A-21D, as shown in FIG. Data signals CDL0 Data0, CDL1 Data1, CDL2 Data2, and CDL3 Data3 applied from the central data link 21A-21D according to the latch signals Latch00-Latch33 applied from the block matching timing supply unit 60 by SY2 and SY3. ) Is temporarily stored and then applied to the mux (50A-50D) side. At this time, the clock signals CK0, 1, 2, and 3 of the central data link 21A-21D generating the latch signals Latch00-Latch33 have a timing margin sufficient for the data signal applied to the register 40 to be latched. The synchronization signal SY0-SY3 is a signal for notifying the position of the timeslot in the frame of the NES signal.

For example, the latch signal Latch03 is assigned to the timeslots 0, 4, 8, 12... Of the data signal Data0 outputted from the central data link 21A. , Timeslot 1, 5, 9, 13... , Timeslots 2, 6, 10, 14... , Timeslots 3, 7, 11, 15... Latch. That is, when the data signal Data0 output from the central data link 21A is latched by the latch signal Lathc00-Latch03 applied from the block matching timing supply unit 60 in the CDL0TS0-CDL0TS3 in the register 40, the accompanying drawings are attached. As can be seen from the fourth degree, CDL0TS0 of register 40 has timeslots 0, 4, 8, 12... , CDL0TS1 contains timeslots 1, 5, 9, 13... , CDL0TS2 contains timeslots 2, 6, 10, 14... In CDL0TS3, timeslots 3, 7, 11, and 15 are stored, and the stored data signals are sequentially applied to the mux 50A-50D. The mux 50A-50D synchronizes the phase of the data signal applied from the register 40 according to the selection signal from the local timing supply unit 70 by the local clock applied from the space switch so as to synchronize the highways (HWY0-HWY3). Transfer to the space switch side via.

As described above, the present invention is reliable in the transmission and reception of data by eliminating the time slot jitter that is out of phase due to the delay of data generated according to the length of the cable that connects the blocks when matching between the call-path block of the electronic switching system. This is provided.

Claims (1)

In an all-electronic switch, a central data link for receiving a data signal applied from an access switching system according to a clock of an NES signal applied from an external device, and a space switch for matching data of a telephone line system applied from the central data link is provided. Block matching timing generating means for outputting a predetermined latch signal for latching a signal output from the central data link according to a clock signal and a synchronization signal applied from the central data link, and from the block matching timing generating means. A local timing generating means for outputting a register for storing a data signal applied from the central data link according to an applied latch signal, and a signal for sequentially selecting a signal output from the register according to a local clock applied from the space switch; , Local The synchronization of the phase of the data signals applied from the register system to the mux to be applied to the space switch side via the highway to the former e-exchanger according to claim 1, further provided with a call registration device in accordance with the selection signal applied from the production tool.