NO933495D0 - FILTER TO SET THE BANDWIDTH FOR A CONTROL POWER - Google Patents
FILTER TO SET THE BANDWIDTH FOR A CONTROL POWERInfo
- Publication number
- NO933495D0 NO933495D0 NO933495A NO933495A NO933495D0 NO 933495 D0 NO933495 D0 NO 933495D0 NO 933495 A NO933495 A NO 933495A NO 933495 A NO933495 A NO 933495A NO 933495 D0 NO933495 D0 NO 933495D0
- Authority
- NO
- Norway
- Prior art keywords
- bandwidth
- filter
- control loop
- amplifying units
- loop
- Prior art date
Links
- 230000003247 decreasing effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/04—Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
- Electrophonic Musical Instruments (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Networks Using Active Elements (AREA)
- Filters And Equalizers (AREA)
Abstract
The bandwidth of the control loop can be increased or decreased by selectively changing gain factors of amplifying units (BSI, BSP) of a filter present in the control loop. When the bandwidth is set, other quantities such as, for example, a peaking of the closed loop characterising the dynamic characteristics remain unchanged in the first approximation. The filter consists of at least one input (UD) and one output (UF), is implemented by means of digital chips and enables the bandwidth to be changed by setting at least one value of one chip of the filter. Further embodiments consist of at least two amplifying units (BSI, BSP), at least one control unit (BST), at least one integrator (IG) consisting of an adder (ADDI) and a register (REG), at least one adder (ADD) and possibly also of two or more further amplifying units (FSI, FSP). In particular, the control loop can also be a phase-locked loop in which the bandwidth is to be switched without the peaking in the frequency response of the closed control loop being significantly changed. <IMAGE>
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH308792 | 1992-10-02 |
Publications (3)
Publication Number | Publication Date |
---|---|
NO933495D0 true NO933495D0 (en) | 1993-09-30 |
NO933495L NO933495L (en) | 1994-04-05 |
NO304914B1 NO304914B1 (en) | 1999-03-01 |
Family
ID=4248337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO933495A NO304914B1 (en) | 1992-10-02 | 1993-09-30 | Phaseless loop with controllable filter |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0590323B1 (en) |
AT (1) | ATE180931T1 (en) |
DE (1) | DE59309625D1 (en) |
NO (1) | NO304914B1 (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU724131B2 (en) * | 1995-10-20 | 2000-09-14 | Telefonaktiebolaget Lm Ericsson (Publ) | Phase locked loop |
SE517602C2 (en) * | 1995-10-20 | 2002-06-25 | Ericsson Telefon Ab L M | Locked loop |
JP2891149B2 (en) * | 1995-11-20 | 1999-05-17 | 日本電気株式会社 | Phase control loop method |
US5966416A (en) * | 1996-11-21 | 1999-10-12 | Dsp Group, Inc. | Verification of PN synchronization in a spread-spectrum communications receiver |
US6072842A (en) * | 1996-11-21 | 2000-06-06 | Dsp Group, Inc. | Carrier-recovery loop with stored initialization in a radio receiver |
JP2000278124A (en) | 1999-03-26 | 2000-10-06 | Sanyo Electric Co Ltd | Pll circuit |
WO2002005428A2 (en) * | 2000-07-10 | 2002-01-17 | Silicon Laboratories, Inc. | Digitally-synthesized loop filter circuit particularly useful for a phase locked loop |
US7409028B2 (en) * | 2000-12-22 | 2008-08-05 | Ericsson Inc. | Clock synchronization in a communications environment |
US7145399B2 (en) | 2002-06-19 | 2006-12-05 | Texas Instruments Incorporated | Type-II all-digital phase-locked loop (PLL) |
DE102004035257B3 (en) * | 2004-07-21 | 2006-02-09 | Siemens Ag | Electronic controller for phase equalization uses phase locked loop arrangement with integrator equalization module to eliminate phase errors |
TWI478500B (en) * | 2009-09-23 | 2015-03-21 | Richwave Technology Corp | Digital phase-locked loop, frequency adjusting method and integrated receiver |
CN105978558B (en) * | 2009-11-10 | 2021-06-18 | 立积电子股份有限公司 | Digital phase-locked loop, frequency adjusting method and integrated receiver |
CN113131888B (en) * | 2020-01-10 | 2024-05-24 | 微龛(广州)半导体有限公司 | Bandwidth-adjustable amplifier circuit, bandwidth-adjustable method, bandwidth-adjustable medium, bandwidth-adjustable terminal and bandwidth-adjustable optical receiver |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4598257A (en) * | 1983-05-31 | 1986-07-01 | Siemens Corporate Research & Support, Inc. | Clock pulse signal generator system |
JPS6273818A (en) * | 1985-09-27 | 1987-04-04 | Toshiba Audio Video Eng Corp | Digital pll device |
US4912434A (en) * | 1989-02-27 | 1990-03-27 | Honeywell Inc. | Digital control for analog phase locked loop |
US5121085A (en) * | 1991-06-28 | 1992-06-09 | Digital Equipment Corporation | Dual-charge-pump bandwidth-switched phase-locked loop |
US5268655A (en) * | 1992-05-27 | 1993-12-07 | Codex Corporation | Device and method for automatically adjusting a phase-locked loop |
-
1993
- 1993-08-28 DE DE59309625T patent/DE59309625D1/en not_active Expired - Fee Related
- 1993-08-28 EP EP93113795A patent/EP0590323B1/en not_active Expired - Lifetime
- 1993-08-28 AT AT93113795T patent/ATE180931T1/en not_active IP Right Cessation
- 1993-09-30 NO NO933495A patent/NO304914B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
NO933495L (en) | 1994-04-05 |
EP0590323B1 (en) | 1999-06-02 |
NO304914B1 (en) | 1999-03-01 |
DE59309625D1 (en) | 1999-07-08 |
EP0590323A1 (en) | 1994-04-06 |
ATE180931T1 (en) | 1999-06-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM1K | Lapsed by not paying the annual fees |
Free format text: LAPSED IN MARCH 2002 |