NO300710B1 - Lamp brightness control circuit - Google Patents

Abstract

A dimmer circuit for a load circuit having a low-voltage halogen light or lights (NV) and a power transformer (Tr) or power transmitter connected upstream thereof, for variation of the real power taken from an AC voltage supply and emitted to a load circuit (Tr, NV) has: a high-frequency AC voltage generator (20) which emits an output AC voltage (uW) from an essentially smoothed or unsmoothed, rectified low-frequency intermediate circuit voltage (uN) to the load circuit (Tr, NV) and a variable delay switching element or a digital/analog propagation time element, in particular a lowpass filter (PT1) consisting of a variable resistor (R4, R5, P) and a synchronous capacitor (C1) in a series circuit. The circuit arrangement is intended to be designed such that an improved (in particular reduced in size) dimmer circuit permits continuous dimming control between zero and maximum of, in particular, low-voltage halogen lamps. This is achieved according to the invention by providing a synchronous circuit (V5, V7, TH; R16, V13) which is connected on the output side to the delay switching element, to the propagation time element or to the synchronous capacitor (C1) of the lowpass filter (PT1) and, on the input side, is supplied from the rectified intermediate circuit voltage (uN) or the AC voltage supply. <IMAGE>

Description

The present invention relates to a circuit device for brightness regulation, as stated in the introductory part of claim 1. Furthermore, the invention relates to a method for changing the brightness of a low-voltage halogen lamp as stated in the introductory part of claim 14.

Circuits for controlling the degree of brightness or brightness (dimming) in incandescent lamps are commonly known. Thereby, a distinction is made between incandescent lamps that receive power directly from the mains voltage supply, and incandescent lamps (low-voltage halogen lamps NV) that are powered indirectly through an isolating transformer. The former are connected directly to a supply network (typically 200V, 50Hz) and the brightness is regulated by known phase section control (ignition delay) using triac and diac.

The brightness of the latter is more difficult to set, as the load circuit uses an inductively acting, voltage-reducing transformer with secondary-side low-voltage incandescent lamp NV. If the low-voltage lamps driven through the transformer (typically 220V/12V) are connected to a normal phase difference dimmer, symmetry problems will arise, because a normal phase difference driven dimmer cannot easily output a pure alternating voltage required for a transformer. Problems of a protection technical nature also arise, as an isolation transformer which in and of itself constitutes a passive construction element, is nevertheless clearly more sensitive to current and temperature increases than directly driven lamps. Finally, the necessary construction height of a magnetically coupling amplifier (isolating transformer) constitutes an important problem in the operation and brightness regulation/control of low-voltage halogen lamps.

Halogen lamps are particularly advantageous in use, due to their longer lifetime, higher efficiency and greater light output. Due to their very small size, the low-voltage halogen lamps will also enable greater creativity when designing lamps and lighting fittings. As a result of high brightness and small size, however, the light density is particularly high, and direct consideration of an almost point-shaped light source, i.e. without a reflector and/or covering or shielding, can sometimes be a nuisance. Brightness control will be very beneficial in this regard.

Dimming devices for Lawolts halogen lamps are known, for example, from GB-A-2,204,191 or EP-A3-0331157. Such a dimming device comprises a rectifier circuit to convert a supply alternating voltage into a rectified and low-frequency intermediate circuit voltage, as well as a high-frequency alternating voltage generator which converts the intermediate circuit voltage into a high-frequency alternating voltage and delivers this further to a power converter. The power converter is connected in front of a lamp for variation of the real power taken from the alternating voltage generator. The dimming is achieved in the usual way by phase section control.

According to GB-A-2,204,191, the dimming device also comprises a variable delay circuit, for example a low-pass circuit, which contains a synchronization capacitance. A synchronizing circuit is controlled via a Diac which activates the alternating voltage generator when the charge of the synchronizing capacitor exceeds the Diac's threshold value. Thereby the synchronization capacitance is discharged. However, the synchronization capacitance charges up parasitically or per half-wave with the mains voltage frequency, when during one or more mains voltage half-waves no ignition of the alternating voltage generator is carried out. As the synchronizing capacitance is only discharged upon activation of the alternating voltage generator, the synchronizing capacitance is charged step by step in a parasitic manner. At an arbitrary half-wave, the synchronizing capacitance's voltage finally exceeds the Diac's ignition voltage, and thus a parasitic and unwanted high-frequency oscillation is started for the alternating voltage generator.

The purpose of the invention is therefore to produce an improved and in particular a reduced brightness control device for stepless brightness adjustment between zero and maximum, especially for low-voltage halogen lamps.

According to the invention, this has been achieved by producing a circuit device as stated in the introductory part of claim 1, with special features as described in the characterizing part. The task is further solved by a method with special features as stated in the characterizing part of claim 15. In accordance with the invention, brightness control will be achieved by using the synchronous control circuit according to claim 1 in a remote controlled inverter according to claim 17.

A significant effect of the invention lies in the now accurate mains synchronization of an NV halogen dimmer according to the invention. In this way, in particular, the brightness regulation down to the value zero will be achieved with an accurate mains synchronization. Parasitic fluctuations and occasional flaring or flickering of the low-voltage halogen lamp will also be avoided, and likewise a power jump/brightness jump when slowly increasing the brightness from zero.

An important purpose of the invention is the increased safety precautions and the improved protection, which applies both to the idling and the short circuit case. The temperature and current maximum value monitoring is also improved. The latter is particularly advantageous, because low-voltage halogen lamps in a cold state have an extremely low internal resistance, and that the transformer must consequently deliver a very high, short-term switching current.

Another and significant effect according to the invention is the reduced construction size, as well as the reduction of the mechanical weight of the used power transformer. Due to the invention and the high heat resistance of the NV glow coil, equalization of the supply voltage can be dispensed with at the same time, which reduces costs. Despite strong instantaneous value power pulsations, the emitted light is largely regular.

Advantageous versions of the invention are indicated in the method and device sub-claims.

Particularly advantageous is the high-frequency periodic and low-frequency periodic combination synchronization according to claim 14. High-frequency periodic this applies to the inverter output voltage uw which can amount to approximately 40 kHz. At low periods, this applies to the mains voltage frequency, which is, for example, 50 or 60 Hz. Global synchronizing conditions thereby advantageously present only the low-frequency periodic synchronization, which synchronization periodically resets/initiates a delay stage (PT1). With output from the control voltage ust which is created through PT1 and whose pitch can be varied, an inverter which oscillates at a predetermined high frequency is released after a variable ignition delay a (ignition angle). At the same time as the fluctuation in the inverter output voltage uw(t), a continuous, high-frequency controlled synchronization of PT1 takes place. The two synchronizations jointly make it possible to predetermine the same output conditions for PT1 at the onset of each supply voltage half-wave uN(t) both at arbitrary brightness and at zero brightness.

Favorable protective measures for the power transformer and for operational safety can be seen from requirements 8 (overload protection), 9 (temperature limitation), 19 (oscillation stabilization) and 11 (idle protection).

Claim 4 deals with a self-controlled (self-controlled or self-oscillating) inverter which is particularly advantageous for the control device according to claim 1. Next to a self-controlled inverter, due to the use of an externally controlled (externally controlled) inverter, i.e. with output frequency that can be pre-set using a control alternating voltage signal, an independent solution variant emerges.

As an alternating voltage generator, a half-bridge connection as stated in claim 2, or a full-bridge connection as stated in claim 3 can be advantageously used, whereby the capacity branching can be omitted, and both of the externally controlled and of the self-controlled type. The predetermination of a synchronizing threshold as stated in claim 5 offers advantages when determining the sensitivity of the zero synchronization according to claim 1. Advantageous modifications with regard to dimming and the inverter's self-locking effect appear in claims 12 and 13.

The particularly favorable combination of low-frequency and high-frequency synchronization which is highlighted in claim 14 can also be advantageously used separately, which is the independent subject of claim 7 and claim 10 respectively. A disconnection as stated in claim 6 will be particularly advantageous for the low-frequency synchronization, if the load part of the brightness control circuitry includes equalizing capacities, in particular the capacitive branching for the self-controlled inverter in half-bridge connection.

Embodiments of the invention are described in more detail below in connection with a self-controlled inverter that serves as an alternating voltage generator 20.

It is pointed out in this connection that this does not limit the invention to self-controlled inverters. Instead, externally controlled inverters will be used with particular advantage, if the frequency of the output alternating voltage uw(t) varies or is to be stabilized.

Reference is made to the drawings, where:

Fig. 1 shows a connection diagram for an embodiment of

the invention.

Fig. 2 shows a section of the connection diagram according to Figure 1, which particularly illustrates the connection system for a control amplifier Y for a self-controlled inverter. Fig. 3 shows a time diagram illustrating the operation of the embodiment according to Figs. 1 and 2, with the oscillation-insertion time-displacement al=36°. Fig. 4 shows a diagram corresponding to Fig. 3 with the oscillation insertion time offset a2=126°. Fig. 5 shows two time-matched time diagrams illustrating the dependence of control voltage ust(t) and high-frequency load current iL(t) in the power amplifier Tr. Figure 1 shows an embodiment of a dimmer for low-voltage halogen lamps, for consideration in close connection with the time diagram according to Figure 3. The dimmer works in principle with an ignition offset a, which in Figure 3 is for example shown as otl=36°, or with an oscillation insertion time - offset ten, ten corresponding to this ignition offset. As can be seen from the operation according to Figure 3, a high-frequency oscillation packet (burst) is activated with a time shift. It has an enveloping function that corresponds to (is approximately proportional to) it

rectified mains voltage uN(t). For the sake of clarity, the frequency conditions are not correctly reproduced in Figure 3, as the high frequency (HF) from an inverter 20 iL(t) or uw(t) will in practice amount to approx. 40 kHz, while the enveloping uN(t) has a half-wave period duration of 10 ms corresponding to a rectified 50 Hz low frequency oscillation (NF). Rendered to the correct scale, approximately 800 complete high-frequency sine oscillations would therefore have to lie within an NF half-wave time space.

In Figure 1, the control connection part is shown in the left half of the image (separated by a coupling diode Vil), and the power part of an NV halogen lamp dimmer in the right half of the image. The mains AC voltage is rectified through a mains filter 100 and a rectifier, preferably a full-path rectifier 99. The rectified and unbalanced voltage is supplied through the switching diode Vil to an inverter 20. This includes power connections a, b and c as well as control connections d and e. Between the power connections a and b is the series connection for two power semiconductor switches V3 and V4 which can be operated through two control connections, and which are preferably in the form of power transistors or MOS-FETs. Between the two switches (with the center point Ml), i.e. the upper switch V3 and the lower switch V4, the output alternating voltage uw(t) is transferred through the connection c to a load circuit.

Parallel to the aforementioned inverter-semiconductor branch is a series connection consisting of two largely equal capacities C9 and CIO, whose intermediate, common connection is denoted by M2. The load circuit includes a power transformer with at least one primary winding and one secondary winding. A low-voltage halogen lamp with a nominal voltage of preferably 12V is connected, permanently or detachably, to the secondary winding. The primary winding voltage is usually 220 V, but depending on the type of inverter 20 used and the connection device used, for example in the form of a full bridge, half bridge or half bridge with capacitive midpoint, a different primary voltage is chosen for the transformer. An idle protection capacitor C7 is connected in parallel with that of the transformer

input contacts.

The primary winding in the power amplifier Tr has its one connection connected to the output contact C or Ml on the inverter.20, from which the alternating voltage uw(t) is emitted. The primary winding's other connection is connected to the midpoint M2 between capacitors C9 and C19. This midpoint section forms an artificial alternating voltage midpoint, so that the output alternating voltage uw(t) from the inverter 20 has a bipolar effect in relation to this artificial midpoint with roughly half the supply voltage uN(t).

The inverter 20 third connection, denoted b in Figure 1, is connected through a low-ohm current meter resistor R13 (shunt) at the negative connection at the rectifier 99. The inverter 20 control input D is a synchronous input which, according to Figure 1, is directly connected to the output contact C, i.e. with the midpoint Ml in the semiconductor branch V3, V4.

The control input E shown only in principle for releasing the high-frequency inverter 20 controls the alternating operation of the two power semiconductor switches V3 and V4, so that the inverter, after a single pulse at the connection E, is automatically switched on (for self-controlled inverters) and swings on.

Between the 99 positive and negative connections of the rectifier, there is, in front of the disconnection diode at 11, i.e. in the control connection part, connected a series connection consisting of a dimming potentiometer P, a fixed resistance R5, a further, fixed resistance R4 and a capacitor Cl (synchronous capacitor). When the potentiometer position is changed, either the time period for charging the capacitor Cl or the phase position for the voltage fluctuation in the capacitor Cl changes in relation to the output voltage uN(t) from the rectifier 99. In the same way as when using the output voltage from the rectifier 99, a control circuit section route through the series connection consists of of P, R5, R4 and Cl, based on the direct AC voltage, feasible. Likewise, P can be used without R4 and R5, which serve to set the reaction limit.

Parallel to the synchronous capacitor Cl is, firstly, a series connection consisting of a low-ohm resistor R16 and a synchronous transistor V13, and secondly, an independent element, either a thyristor TH or base commutator-comparator circuit in a PNP and NPN transistor V5, V7 for separate creation of a thyristor element. At the connection point between the fixed resistance R4 and the synchronous capacitor Cl, a connection is established, through a release element in the form of a release diode V6 as shown in Figure 1, with the start input or release input E in the inverter 20. This means that, as the synchronous capacitor Cl achieves a predetermined voltage, namely the trigger voltage or switching threshold uz, the control input E will receive a start pulse. At the same time, the capacitor Cl is discharged through V6 and synchronizes the diode V2 which is described below.

Furthermore, the anode of a high-frequency synchronizing diode V2 is connected in connection point R4/C1. The cathode of the diode is connected to the synchronous input d in the inverter 20, which corresponds to the output contact c. When the inverter is in operation, i.e. by periodic operation of the power semiconductor switches V3 and V4, the cathode will allow the discharge of the synchronous capacitor Cl, each time the lower power semiconductor switch V4 is engaged. This causes a continuous discharge of the capacitor Cl, when the inverter emits high-frequency oscillations uw(t), i.e. when the output AC voltage is active. The discharge takes place regularly during an HF half-wave.

The thyristor TH or the transistor combination V5, V7 which is connected in parallel with the synchronous capacitor Cl short-circuits or discharges the latter when the voltage in the current meter resistor 13 exceeds a predetermined or predetermined limit value imax. This is effected by means of a zener diode which connects the output contact b of the inverter 20, which is connected to the meter resistor R13, in blocking direction with the gate connection in the thyristor TH. The blocking voltage of the diode determines the current limit value imax. If greater accuracy is desired, other comparator circuits can also be used. For equalizing short-term disturbances, a noise suppressor capacity C2 can be connected between the gate connection in the thyristor TH and the cathode in the same thyristor.

The voltage in R13 is proportional to the current strength, and always corresponds to the load current iL(t) in the primary winding in the power amplifier Tr, when the lower power semiconductor switch V4 is switched on. Thereby, a current half-wave measurement is formed which, due to its connection potential, can be used with particular advantage for overcurrent monitoring without further translation or transmission links.

An NTC resistor R6 is connected in parallel with the zener diode VI which determines the absolute limit value for the permissible inverter output current iL(t). This resistor is thermally connected to the transformer Tr and advantageously to its secondary winding. The capacitor C2 is connected in parallel with a resistor RI which, in cooperation with the temperature sensor-NTC R6, forms a potentiometer in such a way that the voltage, proportional to the current, from the resistor R13 is led to the thyristor TH, when the resistor R6 decreases in resistance value. This is the case with increasing temperature 8. At the same time as the temperature dependence, a current dependence arises. A very low temperature 9 in the secondary winding allows for a higher amperage before disconnection, while an increased secondary winding temperature in the amplifier Tr causes the temperature monitoring to react earlier. In any case, the current limit value is determined by the breakdown voltage for the zener diode VI, and when the voltage value in the resistor R13 exceeds the zener diode's blocking voltage +0.6V (the flux voltage of the gate-cathode section), the thyristor TH is switched on. A function of iL is used as the maximum value 9max for the isolation transformer temperature. Instead of NTC, other temperature sensors can be used. In addition to discharging the synchronous capacity Cl, the thyristor TH can advantageously short-circuit the later described control amplifier Y according to Figure 2 in such a way that a self-induced, continued oscillation of the self-controlled inverter 20 is prevented or interrupted.

Between the resistors R5 and R4, a voltage proportional to the rectified supply voltage uN(t) is supplied to a zero voltage detector, consisting of R15, R17, R18 as well as V12, V13 and R16, through a resistor R14. The zero voltage detector works in such a way that at low voltage between resistors R5 and R4, i.e. at the beginning and end of the half-waves in the rectified supply voltage uN(t), the synchronous transistor V13 is switched on. This will, in the same or similar way as the thyristor TH, discharge the synchronous capacity Cl through its collector resistance R16. Such a discharge takes place every time the voltage between R5 and R4 drops below a predeterminable minimum value (synchronous threshold).

The synchronous transistor V13 becomes blocking again when the synchronous threshold is exceeded, as occurs periodically. A time-continuous charging of the synchronous capacitor Cl is then allowed through the dimming potentiometer P and possibly through the series-connected resistors R5 and R4. The greater the resistance in dim potentiometer P, the slower the voltage in Cl increases. Correspondingly (in terms of time) later, the voltage threshold for diac V6 is reached and correspondingly later, the automatic high-frequency oscillation is initiated in the (self-controlled) inverter 20 through the release input E. The later the initiation time t2 or tx or t2 occurs (see figures 3, 4), the lower the effect which is supplied to the low-voltage halogen lamp NV. In this way, a brightness control is achieved by shifting the ignition angle (oscillation insertion time).

Equivalent to the discharge of the synchronous capacity Cl through the series connection consisting of the resistor R16 and the synchronous transistor V13, a switching device can be used which creates a connection with the thyristor TH, when the voltage at the output of the rectifier 99 is "close to zero". Because the thyristor TH self-switches off when its quiescent current falls below it, the capacitance Cl can also be discharged in/near the "zero crossing" of the rectified, unbalanced supply voltage uN(t) without disturbing influence from the self-controlled thyristor TH (own reset).

Such control could be achieved, for example, by means of an OR connection of control signals for the thyristor TH, as the thyristor gate would firstly be controlled through the temperature and overcurrent monitoring (Qmax/<i>max) 0<3' for the second, through a snipping trigger with a similar coupling system, which will transmit a control signal to the gate when the half-wave supply voltage u(t) is below a predetermined voltage threshold uH which is close to zero (approx. 5..3 0V).

The resistor R14 (supply resistor) which controls the synchronous connection with the transistors V12 and V13, also supplies the series-connected resistors R17 and R15, the latter of which is connected to the negative connection in the rectifier 99. This connection forms the reference point in the connection device according to Figure 1, but this is only to be considered as an example. In the same way, the entire switching arrangement with inverters can be inverted so that the positive supply voltage, i.e. the positive connection in the rectifier 99 will serve as a reference point.

The base of the transistor V12, whose emitter is connected to the reference point and the connector with the first-mentioned supply resistor R14 through a resistor R18, is connected between the resistors R15 and R17. The connector of the transistor V12 is connected to the base of the synchronous transistor V13 which functions as an emitter follower. The switching system works in such a way that as soon as the applied voltage from R14 falls below a predetermined threshold value, the transistor V12 will, due to the potentiometer R17/R15, be brought into blocking state. Its connector resistor R18 is briefly connected to the base of the synchronous transistor V13 which thereby, through R16, can discharge the synchronous capacitor Cl. As soon as the supplied voltage from R14 increases again, the transistor V12 between collector and emitter becomes conductive, after which the synchronous transistor V13 blocks and releases the charging phase at the synchronous capacitor Cl. A corresponding change of the supply resistor R13 (upper) connection point can be carried out corresponding to the effective one

voltage magnitude uN(t).

When dimensioning the resistors R15 and R17, the synchronous threshold must be set appropriately low, as it is predetermined by the necessary discharge time for the capacitor Cl. If the resistor R16 is chosen larger, switching on the synchronous transistor V13 will only result in the discharge of the synchronous capacitor Cl, without interrupting the high-frequency oscillation which is triggered by the ignition of the thyristor TH. A coupling connection between the zero voltage sensor and the gate connection of the thyristor will, on the other hand, lead to the discharge of the synchronous capacitor Cl, while at the same time the only negligible high-frequency oscillation of the inverter 20 is interrupted.

A comparator (function amplifier) can also be used for the "zero registration".

The operation of a control amplifier Y is briefly described below in connection with figure 2. It causes a sustained oscillation (oscillation bundle, -burst) of the inverter 20 (self-controlled inverter), when its primary winding T1A is connected to the load circuit, i.e. in series with the primary winding in the power amplifier Tr.

In the example shown, the amplifier Y comprises three secondary windings T1B, TIC and TID. The windings T1B and TID are connected to each of the controllable power semiconductor switches V3 and V4. With positive load current, the lower power semi-switch V4 is affected. This also corresponds to the original switching state, when Diac V6 transmits a start pulse to the release input e in the inverter 20, and Cl is discharged through V4 and V6/V2. This discharge is advantageous for the release of further "start" pulses which during an oscillation (HF) could bring this to an end parasitically.

This starting input e which connects the third secondary winding TIC rectified with the second secondary winding T1B which is in connection with the lower power semiconductor switch V4, is shown in more detail in Figure 2. When switching on Diacs V6, i.e. when the control voltage ust(t) for the synchronous capacitor Cl exceeds the trigger threshold uz for Diacs VG, the series connection consisting of the secondary winding TIC and T1B in the control amplifier Y will consequently be supplied with positive current. The lower power semiconductor switch V4 will conduct (brought into conductive connection) and the high frequency oscillation (packet, bundle)

is initiated.

On the other hand, the series connection consisting of the secondary windings TIC and T1B will (or can) be short-circuited through a disconnection diode V9 whose anode is connected to the "on" control contact e in the inverter 20 and the cathode to the synchronous capacitor Cl, upon ignition of the thyristor TH. In this way, a self-controlled oscillation through the control amplifier Y is prevented. Any remaining inductance current in the load circuit is discharged/diverted through the idle diode, which, with its cathode connected to the positive voltage, is connected in parallel with each of the power semiconductor switches V3 and V4.

Figure 3 shows a diagram of the output and input sizes in the switching device according to Figure 1. The (enveloping) rectified mains voltage uN(t) is shown with a broken line.

Due to a specific setting of the dimmer potentiometer P, an ignition delay (ignition angle) al=36° is predetermined. This means that the high-frequency oscillation, which is modulated by means of the mains voltage half-wave uN(t) (up to 100%), is only initiated 36° after the half-wave introduction (natural occurrence or ignition time).

In the case of the self-controlled inverter, the high-frequency oscillation is determined by the dimensioning of the control amplifier Y and the capacities C9 and CIO, as well as the output voltages for the power semiconductor switches V3 and V4. In the case of an externally controlled inverter, the frequency is predetermined by a VCO or an (external) counter.

A delay of the high-frequency oscillation insertion time (denoted by ten in Figure 3) results in a reduction of the power transmitted to the NV lamp. Due to the high-frequency oscillation, a reduced magnetic construction height of the power amplifier Tr will be achieved at the same time. The high-frequency oscillation which is modulated with the enveloping mains voltage half-wave uN(t) finds its natural end at the zero crossing of the mains voltage or at the end a=18 0° of the half-wave. If the time delay a is further increased, as shown in Figure 4, the high frequency load current iL(t) caused by the output AC voltage uw(t) in the inverter 20 will be created even later. However, some periods of the high-frequency voltage (current) may remain, which self-cancel in the zero crossing of the controlling, feeding mains voltage half-wave uN(t).

It appears from figure 5 that if, for a longer period of time, comprising one or more mains voltage half-waves, ignition or initiation of the high frequency does not take place, which means that a=180°, the capacity Cl will be discharged parasitically and pulse-wise/half-wave-wise. This is shown in the lower diagram in figure 5. Corresponding to the voltage half-waves uN(t) and assuming a higher, set value for the dimming potentiometer P, the ignition voltage threshold uz predetermined by the release diode V6 will not be reached within a mains voltage half-wave. Consequently, high-frequency oscillations are not

gen during one or more mains voltage periods. The high-frequency synchronization through the discharge diode V2 which, when the inverter is switched on, ensures regular, high-frequency periodic discharge of the synchronous capacity Cl, remains inactive. The output condition for low-pass PT1 (comprehensive serial

the coupling P, R5 and R4 as well as the synchronous capacity Cl) are different, without HF oscillation for the respective initiation of a mains voltage half-wave uN(t) . In an arbitrary half-wave, the control voltage ust for the synchronous capacity Cl will eventually correspond to the ignition voltage uz for the release diode V6 and, as shown on the right in Figure 5, a parasitic and unwanted high-frequency oscillation in the inverter 20 is initiated. This takes place at time tz. This corresponds to the parasitic ignition delay ax which takes place due to parasitic charging (charging) of the synchronous capacity Cl.

This causes, even if the dimming potentiometer indicates the disconnected state, a sudden flare-up of the NV lamp, and can also cause a parasitic brightness fluctuation or a constantly reduced (but not set) brightness of the same lamp. This is unwanted.

For the above reason, i.e. in the event of a lack of high-frequency synchronization through the output alternating voltage uw with an impact on the synchronous capacity Cl through the discharge diode V2 which is inactive in the disconnected state, an additional low-frequency synchronization is initiated through V13 and R16. This takes place periodically with the "zero crossing" for the rectified supply voltage uN(t).

The effect of the low-frequency (approx. 50 Hz or 60 Hz) synchronization causes in the lower diagram in Figure 5 a respective reset or discharge of the synchronous capacity Cl on. such a way that the synchronous voltage ust in the synchronous capacity Cl at each initiation (a=0) of a supply voltage half-wave uN(t) will always be in a defined, especially discharged, output state. The ignition angle a can thereby, without parasitic influence, be shifted between the values 0<a<18 0° and there will also be no parasitic initiation of the high-frequency oscillations at a larger ignition angle a=180°.

However, the operation and functioning of the Lawolt halogen dimmer described in connection with Figure 1 and the associated timing diagram 3-5 is not limited to this embodiment. In addition to a self-controlled inverter, an external controlled inverter can also be used. Especially in such a case, the used trigger diode V6 and the delay element PT1, (consisting of the dimming potentiometer P, the resistors R5 and R4 and the synchronous capacitor) which determines the ignition delay a can be advantageously replaced by a counter or an analogue or digital timing element. The ignition condition will thereby be defined when a predetermined or predeterminable counter value is reached or when counting down to the value zero. The ignition angle a. can be set by varying the counter output value or the counter frequency.

In the same way, the low-frequency synchronization through R16 and the synchronous transistor V13 can be carried out by resetting or setting the counter. Commissioning, i.e. release, of the self-controlled or externally controlled inverter 20, then takes place through a

enable input that allows an oscillation by receiving an active logic signal. A passive, logical signal would

result in disconnection of the power semiconductor switch with consequent cessation/interruption of the high-frequency oscillation. With a self-controlled inverter, the high-frequency oscillation can be freely predetermined and changed.

When using a counter of the digital version, the reset of this counter takes place in terms of low frequency in the same way as with the low-frequency synchronization of the synchronous capacitor Cl. Likewise, i.e. when resetting or setting the counter, the high-frequency synchronization that was previously carried out using the discharge diode V2 is carried out, when the inverter oscillation is switched on. However, since the release signal at the release input e is static, this signal can also be used for continuous blocking or setting/resetting of the used counter.

Claims (17)

1. Brightness control circuit, especially for a load circuit with a low-voltage halogen lamp (NV) with a front-connected power transformer (Tr) or power converter for variation of the real power supplied from an alternating voltage supply and emitted to the load circuit (Tr, NV), with a high-frequency alternating voltage generator (20) which supplies an output alternating voltage (uw) from a negligible smoothed or unsmoothed, rectified low-frequency intermediate circuit voltage (uN), to the load circuit (Tr, NV), with a low-pass section consisting of a variable resistance (R4, R5, P) and a synchronizing capacitance (Cl) in series connection, and with a first synchronizing circuit (V2, V6) which is connected on the input side to the synchronizing capacitance (Cl) in the low-pass section, and on the output side to the high-frequency alternating voltage generator (20) , and which activates the alternating voltage generator (20) in response to a signal on the input side, characterized by a second synchronizing circuit (V5, V7, TH; R16, V13) which on the output side is connected to the synchronization capacitance (Cl) of the low-pass link (PT1), and on the input side is controlled by the rectified intermediate circuit voltage (uN) or the AC voltage supply , whereby the synchronizing capacitance (Cl) is mainly discharged before each start of a low-frequency half-wave for the rectified intermediate circuit voltage (uN) or before each start of a charging phase for the synchronizing capacitance (Cl), to provide uniform starting conditions, or whereby the synchronizing capacitance (Cl) is discharged via a self-resetting flip-flop circuit when the unbalanced intermediate circuit voltage (ujj) falls below a synchronizing threshold value (uH). 2. Control circuit in accordance with claim 1, characterized in that the alternating voltage generator (20) is designed as an inverter in a half-bridge connection, and that the unipolar output alternating voltage (uw) is supplied from the middle zone (Ml) between two series-connected (semiconductor branching) power semiconductor switches (V3, V4 ) to the first input connection at the power transformer (Tr), that the second input connection at the power transformer (Tr) can be connected to a further center zone (M2) of a series connection (capacitance branch) comprising two capacitances (C9, CIO), and that both the capacitance branch (C9, CIO) and the semiconductor branch are supplied by the unbalanced intermediate circuit DC voltage (uN), and that the two capacitances that form the additional center zone (M2) are approximately the same size. 3. Control circuit in accordance with claim 1, characterized in that the alternating voltage generator (20) is of the full-bridge connection type with two parallel branches, each of which comprises a series connection consisting of upper (V3) and lower (V4) power semiconductor switches, and that the power transformer (Tr) is connected between the respective middle zones of the two branches (Ml, M2) where both branches are themselves parallel-connected with the rectified and unbalanced intermediate circuit voltage (uN) . 4. Control circuit in accordance with one of the preceding requirements, characterized in that the alternating voltage generator (20) is arranged as a self-controlled inverter with magnetic (ti, T1A, T1B, TIC, TID) or optical coupling between the load current (iL) in the primary winding in the power transformer ( Tr) and the alternating voltage generator (20, V3, V4). 5. Control circuit according to claim 1, characterized in that the second synchronization circuit (V5, V7, TH; R16, V13) discharges the synchronization capacitance (Cl) of the low-pass link (PT1) in each case where its control signal (uN) on the input side drops below the predeterminable synchronization limit value (uH), and in that it other synchronization circuit (V5, V7, TH; R16, V13) releases the synchronization capacitance (Cl) of the low-pass link (PT1) when the control signal (uN) on the input side is greater than the synchronization limit value (ujj). 6. Control circuit in accordance with claim 2 or 4, characterized in that an element, preferably a diode (Vil) is connected in series with the parallel connection consisting of the semiconductor switch branch (V3, V4) and the capacitance branch (C9, CIO) in wire direction, for disconnection of the load part from the control part of the brightness control circuit. 7. Control circuit in accordance with claim 1 and/or claim 5, characterized in that the second synchronization circuit (V5, V7, TH; R16, V13) exhibits a series circuit of a discharge resistor (R16) and a controllable semiconductor or switch circuit (V13) . 8. Board of directors in accordance with requirement 1 and/or requirement 5, characterized by that the second synchronization circuit (V5, V7, TH; R16, V13) has a thyristor as a self-resetting flip-flop circuit. 9. Control circuit in accordance with claim 1 or claim 4, characterized in that a self-resetting flip-flop circuit, in particular a thyristor (TH), blocks the alternating voltage generator (20) abruptly and/or discharges or short-circuits the synchronization capacitance (Cl) at least for the remaining mains voltage half-wave (uN) when the high-frequency load current (iL) exceeds a predetermined limit value (imax)• 10. Control circuit in accordance with claim 1, 4 or 9, characterized in that a temperature sensing element is arranged in the power transformer (Tr), particularly in the immediate, thermal vicinity of its secondary winding(s) which supplies current to the low-voltage lamp(s) ( R6, NTC), and that a self-resettable flip-flop circuit, in particular a thyristor (TH), blocks the alternating voltage generator (20) abruptly and/or discharges or short-circuits the synchronizing capacitance (Cl) at least for the remaining low-frequency mains voltage half-wave (uN) when the measured temperature (9) exceeds a predetermined limit value (9max), where in particular the aforementioned temperature limitation (9max) acts in dependence on the load current in such a way that at a reduced temperature (9) of the load transformer (Tr) a greater, and at an increased temperature, is permitted a correspondingly reduced current maximum value for the high-frequency load current (iL) and that the maximum value is always below a limit value 11. Control circuit in accordance with claim 1 or 4, characterized in that the alternating voltage generator (20) has two inversely controlled semiconductor switches (V3, V4) which form an inverter, and that a periodic discharge of the synchronization capacitance (Cl) via a diode (V2 ) which has its cathode directed towards the output alternating voltage (uw, Ml), occurs in each case where the respective (V4) of the two semiconductor switches (V3, V4) is controlled to be conductive. 12. Control circuit in accordance with claim 1 or 4, characterized in that a load capacitance (C7) is connected in parallel with the primary or secondary winding of the power transformer (Tr). 13. Control circuit in accordance with one of the preceding claims, characterized in that the high-frequency oscillation start time (tz, cxl+Qf2) can be shifted within an intermediate circuit voltage (uN) half-wave, by comparison (V6) of a predetermined or predeterminable threshold value ( u2) with a temporally continuously variable (R4, R5, P) increasing control signal (ust), whereby a time delay of the HF oscillation start time (tz, al, a2) between the beginning (a=0°) and the end (a=180 °) of the half-wave corresponds to a reduction of the lamp brightness (NV) between the maximum brightness and zero. 14. Control circuit in accordance with one of the preceding claims, characterized in that the alternating voltage generator's (20) high-frequency oscillations which are triggered by means of a trigger element, for example a trigger diode (V6), are inherently stable until the end of a respective intermediate circuit voltage half-wave (uN), unless a protective circuit device, such as an over-temperature control or a maximum current control, is activated during the high-frequency oscillations. 15. Method for varying the brightness of at least one low-voltage halogen lamp using high-frequency oscillation packets (uw), which can be supplied periodically by means of a power transformer (Tr) for the low-voltage halogen lamp (NV), whereby the oscillation start time (Tz, ari, a2 ) can be shifted (a) within a half-wave duration of a pulsating supply voltage (uN) in dependence on a brightness control signal (Ugt, <U>z) or a corresponding resistance variation (P), whereby a high-frequency periodic (V2, V6 ) synchronization of the oscillation process occurs during operation, characterized by the fact that there is also a low-frequency periodic synchronization (R16, V13) or resetting/initialization of the system process that determines the oscillation start time (Tz, al, a2), especially the time-dependent charging of a capacitive element (Cl), so that at the start of each half-wave of the pulsating supply voltage (uN) the same starting conditions are provided. 16. Method according to claim 15, characterized in that a high-frequency oscillation packet (uw) which is initiated at the shiftable oscillation start time (tz, al, a2) increases and/or decreases with the driving, unbalanced supply voltage (uN) depending on the sign of the rise of the supply voltage half-wave (uN), and that the oscillations of the oscillation package (uw, iL) are interrupted abruptly when the temperature of the power transformer (Tr) and/or the amplitude of the high-frequency oscillation current (iL) exceeds a predetermined limit value (Imax/ 6max) • 17. Application of a brightness control circuit according to claim 1 in an externally controlled inverter as an alternating voltage generator (20) with free external selection of the oscillator frequency by brightness variation of a low-voltage halogen lamp (NV).