NO134676B - - Google Patents

Description

The invention relates to a semiconductor device with a semiconductor body comprising at least one field-effect transistor with an insulated gate, a first region of a first conductivity type and a second region of a second conductivity type which joins the surface and which forms a pn junction with the first

the council, source and drain zone of the first conductivity type that joins the surface and is arranged in the second re-

advised, at least one gate electrode layer which is arranged between the source and drain zone and is separated from the semiconductor body by an insulating layer.

The invention further relates to a method for producing such a semiconductor device.

Semiconductor devices of this type are known and

turned in various designs, especially in integrated monolith circuits. Such a design where the source and drain zone of the field effect transistor is located in an area separated from the rest of the semiconductor body by means of a pn junction is particularly important because it enables combinations

of semiconductor elements in integrated circuits which are very interesting from a technological point of view.

E.g. one or more bipolar transistors can be very simply arranged in the same semiconductor body in addition to the field effect transistor, with no or very few additional work operations. Of even greater importance is the possibility that, in addition to the aforementioned field effect transistor, one or more additional field effect transistors with a complementary structure can be placed in the same semiconductor body. Such combinations of p-channel and n-channel field effect transistors are used in many important integrated circuits, particularly in storage circuits.

The above-mentioned semiconductor devices are used for

m

. step by step in very fast working circuits and it is consequently of great importance that the dimensions and. thus also the different capacities in the resulting structure are as small as possible so that the number of circuit elements per unit area can also be increased. With known semiconductor devices, this is often not the case, which is mainly due to the necessary work operations below

the manufacturing and the tolerances that are necessary.

Austrian patent document No. 280.3^9 describes the use of a recessed insulation pattern for the formation of semiconductor elements. The manufacture of field-effect transistors with an insulated gate electrode is not apparent from this patent document, however.

DOS No. 1,614,233 and U.S. Patent No. 3,472,712, on the other hand, describe the production of field-effect transistors with an isolated gate circuit> where the gate electrode is used as masking. Manufacture of a transistor structure where the transistor is arranged in a second area which is separated from the adjacent semiconductor area by means of a pn junction does not appear in these patent documents.

The purpose of the invention is therefore to provide a semiconductor device with a new structure comprising a field-y-uv-yyo effect transistor with very small dimensions which enables the placement of many circuit elements per surface unit and which can be used in very fast working integrated circuits, at the same time that the device can be produced with a relatively small number of work operations with, for the most part, very wide tolerances.

The invention is, among other things, based on the fact that the area required for contacting the source and drain zones in the field effect transistors can be significantly reduced by using a pattern of an insulating material that is at least partially recessed in the semiconductor body, preferably oxide deposited by local oxidation, which surrounds an island-like region of the second conductivity type which is arranged in the first region of the first conductivity type, which pattern also limits at least the source and drain regions of the isolated gate field effect transistor which is placed in this island region.

According to the invention, this is achieved by a pattern of electrically insulating material which is at least partially

sunk in the semiconductor body and which practically surrounds the other area

•completely speaking, which pn junction between the first and second regions joins the recessed pattern which also joins the source and drain zones, and with at least one further portion substantially completely surrounds a further likewise surface-adjacent portion of the semiconductor body in which there is a further semiconductor connection element.

In the device according to the invention, there are other

the tip of the second conductivity type already separated from the first region by a pn junction, so that further insulation by means of a recessed insulation pattern seems redundant in this case. However, it has been shown that the use of such a recessed pattern is surprisingly advantageous in this case and makes it possible to obtain a structure with significant advantages in a simple way, where in particular the mutual location of practically all the zones is determined by the recessed pattern as it will be described in more detail below.

One of the important advantages of the semiconductor device

according to the invention is that it can be produced in a very simple way and enables the use of source and diversion zones with mini-

small dimensions, while the distance between this field effect transistor and the nearest circuit element in an integrated monolithic circuit can also be reduced. As a result, it can be

many circuit elements are brought.pr. surface unit, as a reduction of 30-50/S of the surface area can be achieved. The capacity between metallization and the underlying semiconductor body can also be reduced to a significant extent because the metal paths extend at least partially over the recessed insulation pattern. All these advantages are of great importance for achieving very fast working circuits.

Preferably, the recessed pattern further surrounds a further part of the first area joining the surface, in which part are arranged to the surface terminating zones and the drain zone of the second conductivity type of a field effect transistor which is complementary to said field effect transistor and whose source and drain zone joins the recessed pattern, and at least one gate electrode layer is separated from the semiconductor body by an insulating layer disposed between the source and drain regions. Such a combination of one or more e.g. npn field-effect transistors with one or more field-effect transistors of complementary pnp structure are of particular interest, which has already been mentioned above. To increase the number of circuit elements per unit area, the recessed insulation material that surrounds the second area can preferably partly consist of the recessed insulation material that surrounds the further part of the first zone.

A further important embodiment for obtaining a combined field-effect transistor and bipolar circuit elements consists in the recessed insulating sample surrounding a third region of the second conductivity type which joins the surface, joins the recessed insulating material and forms a pn junction with the first region, in which third area is arranged at least one further zone of the first conductivity type which joins the surface and together with the third area forms part of a bipolar circuit element. To obtain a vertical bipolar transistor, the said additional zone of the first conductivity type can join the recessed monster, and the third area can form the base zone of a vertical bipolar transistor whose emitter-collector zone is formed by the additional zone resp. the first area.

A combination of an isolated lateral bipolar transistor is obtained when two zones of the first conductivity type joining the surface are arranged in a third region, which zones form the emitter and collector zones of a bipolar lateral transistor whose base zone is the third region.

An important improvement of the above-mentioned embodiments is achieved if additional gate electrodes are arranged over the third area and are separated from the surface of the semiconductor body by an insulating layer and are preferably DC-connected to the base zone of the bipolar transistor to prevent the formation of leakage current channels.

Such embodiments are advantageous with respect to the production in that the second and third regions of the second conductivity type are placed at the same time, in that the source and drain zone of the first field effect transistor and the further zone of the first conductivity type are placed at the same time, and that any gate electrodes like" the the associated insulation layer is placed at the same time.

The invention further relates to a particularly simple and effective method for producing such a semiconductor device where a second region of the second conductivity type which forms a pn junction with the first region and joins the surface of the semiconductor body is arranged in a first region of the first conductivity type which likewise joins the mentioned surface, and where the source and drain zone of a field effect transistor is arranged in the second area, is characterized in that a layer that protects against oxidation is placed on part of the surface of the first area, that a layer-shaped oxide monster which is at least partially recessed in the semiconductor body and which surrounds a surface part of the first region, practically completely, then is placed by oxidizing on the surface parts that are not covered by the protective layer, that a doping material which determines the second type of conductivity is placed from the outside in the said surface part to form the second region, in that they t recessed oxide pattern protects against the doping,

that a doping material which determines the first conductivity type is placed in the second area from the outside via surface parts of the second area to at least form the source and drain zone, the recessed oxide sample protecting against the doping, and that at least one gate electrode layer is placed as is separated from the second area by means of an electrical insulating layer and which extends over part of the surface of the second area between the source and drain zones.

A very simple method is achieved by placing at least one gate electrode layer for the placement of the source and drain zone, after which the doping material that determines the first conductivity type is introduced into the second area, the gate electrode layer or layers also being used as a protective layer against the doping material.

The method according to the invention is very advantageous compared to known methods for manufacturing a semiconductor device with a field effect transistor with an insulated gate which is placed in an isolated island area.

First, the introduction of dopant (and preferably partial diffusion of dopant through the surface) necessary to form the second region, as well as the use of activators that serve to form the source and drain regions, can all be accomplished by exploiting the masking effect of the recessed oxide samples and preferably also the gate electrode or electrodes, which usually must be present due to other functions (isolation, control). As a result, some of the work operations by the known methods and also the tolerances that must be observed can be simplified and this not only results in certain dimensions of the various zones being achieved in a very simple way, but also in very small dimensions for source and the diversion zone.

Contacting such small zones does not require severe difficulties because the source and drain electrodes are only present with a small part of their surface in the respective zones, other parts of the source and drain electrodes being located on relatively thick sunken oxide. As a result, the capacitances of the vav pn transitions between the source and drain zones and the other area can be kept very small, while adaptation of the contact masking can also take place in relation to the gate electrode sample instead of in relation to the source and drain zone as before. Kt of the results are significantly smaller distances between contact and gate electrode.

As a result, the total length of the field effect transistor can be reduced by more than yjfc which results in smaller dissipation capacities.

It is clear that each of these field effect transistors can have more than one gate electrode layer and that e.g. in the case of a tetrode field-effect transistor, the surface zone of the first conductivity type between two gate electrodes, where island areas serve to connect two current channel parts, can be formed at the same time as the source and drain zone, with only the recessed monster and the gate electrode layer serving for masking.

In most cases, it will be preferable for the resulting field-effect transistor to have a relatively low threshold voltage, e.g. with an absolute value of less than 2 volts. In order to achieve the small surface doping of the channel region between the source and drain electrode regions necessary for this purpose, it is often necessary to diffuse the doping material to form the second region, e.g. by diffusion partially out of the semiconductor body via the surface. This is achieved in a simple way by, after the introduction of the doping material which determines the second conductivity type and preferably for the placement of the gate electrode joint, the doping material is added. a partial out of the semiconductor body through the surface part occupied by the second area and which is limited by the recessed oxide monster, in a room with an atmosphere of reduced pressure, whereby the doping concentration in a zone in the second area that joins the surface, gets a profile that increases to maximum value from the surface and inwards. In this out-diffusion, the recessed oxide sample that is already present is used as a diffusion window. In this case, the source and drain zone can extend seen in a direction across the surface on either side of the level at which the aforementioned maximum value of the doping concentration has. Preferably, however, the source and drain zone are placed completely within the said zone of the second area with a doping concentration that increases from the surface, i.a. to maintain a relatively high breakdown voltage between the source and drain zone and the second region, which is desirable in most cases.

If, in addition to the mentioned field-effect transistor in the second region, a field-effect transistor with a complementary structure is to be placed in the first region, a recessed oxide sample is placed which surrounds at least the further part of the first region and, after the formation of the second region, a doping material is introduced which determines the second conductivity type, from the outside in the further part of the first area to at least form the source and drain zone in the second field effect transistor which is complementary to the first transistor, the delayed oxide monster being used as masking, and that in the at least one gate electrode layer is placed on the further part between the source and drain zone, which layer is separated from the semiconductor body by an electrical insulating layer.

The source and drain zone for the second, complementary field-effect transistor can be placed both before or after the source and drain zone in the first field-effect transistor in the second area. The masking layer against oxidation can form part of the insulation layer on which the gate electrode is placed in one or more field effect transistors.

This method is preferably carried out so that for the placement of the source and drain zone for the complementary, second field-effect transistor, at least one gate electrode layer is placed on the further part, after which the doping material which determines the second conductivity type is introduced into the further part, which gate electrode layer is used as masking for the doping material .

Besides by doping the channel area and the thickness and material of the insulating layer on which the gate electrode is placed, the threshold voltage for a field-effect transistor with an insulated gate can also be determined to a significant extent by the work function of the material for the gate electrode layer. As the gate electrode layer is preferably used as masking during the placement of the source and drain zone, the method according to the invention can be particularly suitable for influencing the threshold voltage, and if desired simultaneously with the placement of the source and drain zone, using polycrystalline. silicon as gate electrode layer and doping of this. This doping of the polycrystalline material can often be carried out with advantage using the polycrystalline gate circuit layer as masking, and in this way the threshold voltage can be varied. To form the gate electrode layer or layers and any interconnections, a layer of polycrystalline silicon is placed in which the layer, the layers and the connection pattern are formed by etching, and to reduce the resistance of the polycrystalline silicon and give the threshold voltage of at least one of the field effect transistors a desired value, the polycrystalline silicon is doped in at least one of the gate electrode layers with a donor or acceptor material.

The polycrystalline silicon is preferably doped with phosphorus.

At least one gate electrode layer can be doped with doping material which is simultaneously used for the doping of the source and drain zone in one of the field effect transistors. It can be advantageous that at least one gate electrode is connected to each of the field effect transistors

at the same time doped with the same doping material that is used when doping by

.the source and drain zone of the field effect transistor.

Some embodiments of the invention will be explained

in more detail with reference to the drawings.

Fig. 1 schematically shows a ground plan of a part of a semiconductor device according to the invention.

Fig, 2 shows a section along line II-II in fig. 1.

Fig. 3 shows a section along the line III-III in fig. 1.

Fig. 2-14 shows a schematic section along the line II-II in fig. 1 for successive work operations during the manufacture of the device. Fig. 15 shows a corresponding section for another embodiment of a device according to the invention.

Fig. 16 similarly shows a third embodiment of

a device according to the invention.

Fig. 17 similarly shows a fourth embodiment of

" a device according to the invention.

The figures are not shown to the correct scale and corresponding components have the same reference numbers on the different figures. In fig. 1, the metal layer is shaded. In the cross-sections, the semiconductor zones are shaded in the same direction for the same conductivity type.

"The semiconductor device in Fig. 1-3 consists of a semiconductor body 1 of silicon in which a field-effect transistor A with an insulated gate is arranged. The body comprises a first area 2 of n-type silicon which joins the surface 3 of the body, and a second area 4 of p-type silicon which forms a pn-junction 5 with the first region 2. Source and drain zone 6 or 7 of the n-type join the surface 3 in a second area 4 and between the source and drain zone is arranged a gate electrode 8 of polycrystalline silicon which is separated from the underlying second area 4 by means of an insulating layer 9 of silicon oxide.

The device further has a monster 10 of electrically insulating material, in the present case silicon oxide, which is recessed at least partially in the semiconductor body, and surrounds the second area 4 practically completely. To the recessed oxide layer 15, the pn junction 5 between the first area 2 and the second area 4 and the source and drain zone 6 resp. 7•

On the surface 3 and the gate electrode 8, an insulating layer 11 of silicon oxide is placed, in which contact windows are etched through which the source and drain zone 6 resp. 7 is contact-connected by means of aluminum layers 12 and 13 which partly extend over the recessed oxide layer 10. At part 4B of the area 4, the source zone 6 is short-circuited with this area by means of the layer 12

as shown in fig. 3-

As a result of this structure, the source and diversion zone can

6 or 7, minimal dimensions are given (in this case, e.g. 10 microns) at the same time that the capacity between the aluminum layers 12 and 13 and the underlying semiconductor material is very small in that the aluminum layers extend to a significant extent over the thick recessed oxide layer 10. This depends, among other things . together with the very simple method which can be used for the production of the device according to the invention and which will be described in more detail below. When using the recessed insulating monster, the distance between the field-effect transistor A and a nearby semiconductor element can be made very small, which means that a larger number of elements can be placed per unit area, with a reduction of 30-50$ of the total area compared to the previously known structures.

In the embodiment described here, the recessed oxide sample 10 surrounds a further part 14 of the first area which borders the surface 3 and which in fig. 2 is shown between the dashed line

15 and the surface 3" In this further part 14, the source and diversion zone 16 or 17 for a field-effect transistor B with p-channel and which is complementary to the field-effect transistor A with n-channel which joins the surface 3« The source and drain zone 16 resp. 17 also joins the recessed oxide sample 10 in the same manner as zones 6 and 7, and a gate electrode layer 18 of polycrystalline

silicon separated from the further part 14 of the silicon region 2 by means of an oxide layer 19 is located between the zones 16 and 17. The complementary field effect transistors AB are separated from each other by a part of the oxide monster 10 which belongs to both the monster part surrounding the other region 4 °g the monster part that surrounds the further part 14 of the first area 2. This common part of the recessed monster 10 can be made very narrow, e.g. 10 microns, and for that reason the distance between gate electrodes 8 and 28 in transistors A and B can be made very small, e.g. 30 microns. This is in contrast to the known methods for e.g. the distance between gate electrodes 8 and l8

is always at least 50 microns, as a result of distances and tolerances in the masking.

The source and diversion zone 16 resp. 17 for the field-effect transistor B with p-channel joins the aluminum layer 13 which also forms contact with the zone 7 and the aluminum layer 20 via windows in the oxide layer 11.

In this embodiment, the transistors A and B are parts of an integrated monolith circuit. In addition to the gate electrode layers 8 and 18, a polycrystalline silicon layer 21 is arranged which serves as a connection between other parts of the integrated circuit seam is not shown in the drawing. This connection 21 crosses the aluminum layer 12 and is covered by an oxide layer 11 at least in the area of the crossing. In the places not shown in the drawing, the layers 8, 18 and 21 are connected through windows in the oxide layer 11.

A device of the above-mentioned kind is produced according to the invention as follows. The various work operations are only described in so far as they apply to the surface where the field effect transistors are arranged, e.g. to the extent that diffusions penetrate into other surfaces and possibly be removed by grinding or etching, this is not shown in the figures because this is not covered by the invention.

One starts from a substrate 2 of n-type (see Fig. 4) of silicon, preferably with the orientation (111) or (100) with e.g. a specific resistance of 6 ohm.cm. A 0.1 micron thick layer of silicon oxide is deposited on the substrate by thermal oxidation. After that, a layer of silicon nitride 31 is applied in the usual way which is 0.1 micron thick and which is again covered by a 0.1 micron thick layer of pyrolytic silicon oxide. For the placement of the silicon nitrite layers and methods used for etching these layers, reference should be made to an article in Philips Research Reports for April 1970 page II8-I32, where all necessary information is provided for the person skilled in the art.

A masking against oxidation is then placed by masking and etching from the layers 31 and 30 in the area of the field effect transistor A

and B. For that reason, the oxide layer 32 is first given the form of an anti-oxidation masking by ordinary photolithographic methods. The remaining parts of the oxide layer 32 are then used as masking to give the underlying nitride layer the desired shape by etching in phosphoric acid, after which the remaining parts of the layer 32 as well as parts of the layer 30 that do not lie below the nitride layer are removed by etching in buffered solution with hydrofluoric acid. In this way (see Fig. 5) an anti-oxidation masking 30, 31 remains after which the parts of the silicon surface not covered by the layers 30 and 31 are etched away to a depth of 1 micron. The obtained structure is shown in fig. 5'. If desired, the etching can be sloyfed and in that case the recessed oxide sample that will be formed afterwards will only partially extend over the silicon surface. The etched surface parts of the silicon that are not covered by the masking 30, 31 are then oxidized by a thermal oxidation for 16 hours at 1000°C in moist oxygen, so that an oxide monster 10 is formed which is recessed in the body and whose surface practically corresponds to the original surface of the semiconductor body, see fig. 6, and which in the area of field effect transistors A and B surrounds surface parts of area 2. A layer of silicon oxide with a thickness of 0.1 micron is then pyrolytically deposited over the whole, after which layers 30 and 31 are photolithographically removed completely over that area where the field-effect transistor A with n-channel is to be placed, see fig. 7«; A boron diffusion with boron nitride as a source is then carried out to give the structure shown in fig. 8 using known methods at a deposition at approx. 920°C and recovery. During this boron diffusion, in which the recessed oxide sample 10 serves as masking, an oxide layer 34 is formed on the silicon, under which area 4 of p-type is located. In some cases, this area 4 can also be formed in another way by external doping, e.g. by ion implantation, whereby the oxide sample 10 also serves as masking. In the case where a directed ion beam is used which does not cover the area of the field effect transistor B, and the ions have sufficient energy to penetrate the layers 30 and 31> the layers must be removed only for the diffusion from the area 4 as will be described below. ;Without the use of masking, the oxide layer 34 and, if desired, but not necessary, the nitride layer 31 are successively removed by etching, after which boron further partially penetrates the silicon and also diffuses out via the surface at 1200°C for 4 hours in a capsule in vacuum. ;This out-diffusion is preferably carried out in the presence of silicon powder which is either not doped or has a precisely known, relatively small surface doping in order to achieve a threshold value for the surface concentration on the surface of the area 4"; In this out-diffusion, the oxide sample 10 also serves as a masking as well as the oxide layer 30. On the surface, an area 4^ is formed in which the boron concentration increases from a value of 10 atoms/cm^ on the surface to a maximum value of 3 * 10^ atoms/cm^ at a depth of 1.5 microns, in that area which is shown by dashed line 35 (M). The okyd layer 30 is then etched away without the use of masking as shown in fig. 9"

"By thermal oxidation, an oxide layer 36 with a thickness of 0.1 micron is placed after which a layer 37 of high-ohmic polycrystalline silicon with a thickness of 0.6 micron is placed over the entire surface, e.g. by thermal deposition of SiH^, as shown in Fig. 10. The layer 37 is then covered with a layer 38 of pyrolytic or thermally placed silicon oxide with a thickness of 0.1 micron.

By means of photolithographic etching, parts of the layers 37 and 38 which comprise the gate electrode layers 8 and 18 in the field-effect transistors A and B to be placed are then removed, as well as the connecting

layer 31 as shown in fig. 11.

The oxide layer 36 of the surface part of the area 2 in which the p-channel field effect transistor B is to be placed is then removed

by etching with a buffered solution with HF, the part of the oxide layer 38 on the gate electrode layer 18 is also etched away as shown in

fig. 12. The part 19 of the layer 36 which is located below the gate electrode layer 18 is retained. The masking used in this etching is not critical and can have rough tolerances provided that the part of the area 2 which is surrounded by the oxide sample 10 and on which the gate electrode 18 is located is not affected.

The source and diversion zone 16 Iresp. 17 of p-type has a surface concentration of 10 atoms/cm-<3> is formed by diffusion of boron,

with the gate electrode layer 18 and the oxide sample 10 serving as a mask. This dpping from the outside can, if desired, also be carried out on another

way using the same masking, e.g. by ion implantation. In this case and using an ion beam with sufficient energy and which does not cover the area of the field effect transistor A can provide ion implantation through the layers 36 and 38 which then do not need to be removed.

During the formation of the zones 16 and 17, the gate electrode layer 18 is also doped with boron. This reduces the threshold voltage for the field effect transistor 16,17,18,19.

A 0.2 micron thick layer 39 of silicon oxide is then placed over the whole as shown in fig. 13, either thermally or by pyrolytic deposition. When using an equally non-critical masking of the surface of the area 4, the layer 39 is etched away as shown in fig. 4 with the exception of the area 4B as shown in fig. 1. The part 9 of the layer 36 below the gate electrode layer 8 remains, while surface parts of the area 4 with the exception of the area 4^ below the layer 8, as well as the layer 8, are completely free of oxide. Phosphorus is then diffused

in from the outside to form the source and diversion zone 6 resp. 7 with a surface concentration of 10 atoms/cm<J>, in which the gate electrode layer 8 and the connection layer 21 are also doped with phosphorus, which reduces the threshold voltage of the field effect transistor 6,7,8,9 fied n^-channel and the specific resistance of the polycrystalline silicon. The gate electrode layer 8 and the oxide sample 10 serve as masking during this doping. If desired, instead of diffusion, other methods for doping can also be used, e.g.

by ion implantation, in which case the implantation can also be carried out via the layer 36, in which case the placement of the layer 39 can be avoided if a directed ion beam is used which does not cover the area for the transistor B.

Zones 6 and 7 (see fig. 14) are entirely located within zone l\. k in area 4 in which the boron concentration increases from the -surface inwards. A relatively large concentration in the area of line 35 prevents channel formation between area 2 and zones 6 and 7 along the oxide pattern 10.

A 0.6 micron thick layer 11 of silicon oxide is placed over the whole (see fig. 2) in which layer contact windows are etched which can partly be located above the oxide sample 10. Finally, an aluminum layer is placed by vapor deposition and which is given the desired shape in the usual way method by.photolithographic etching, where the masking

only needs are oriented in relation to the gate electrodes so that the structure shown in fig. 1 and 2 are achieved. The aluminum layer 12 forms contact both with the source zone 6 and the area 4B, and as a result

hence the area 4 is short-circuited with the zone 6. Contact with the channel area 14 in the transistor B can take place in a lower part of the area. An enamel ring is finally carried out for 30 minutes at 500°C in a mixture of Ng and Hg.

In this way, a very compact structure is achieved (see fig. 2) where e.g. the following dimensions can be achieved:

a = 10 microns

b = 6 microns

c = 10 microns.

Many variations of the described method are possible.

E.g. in certain cases, the gate electrode layers 8 and 18 can both be advantageously doped with boron or phosphorus. E.g. after the placement of the layer 31j, the polycrystalline silicon layer is first doped with boron, after which the oxide layer 38 of greater thickness is placed so that it protects the gate electrode layers 8 and 18 afterwards against phosphorus diffusion, or vice versa. The person skilled in the art will be able to carry out various other variations of the described method which may have the same advantages with regard to the compactness of the structure and less critical accuracy with regard to the masking. Doping of the polycrystalline silicon can already be carried out at the work step shown in fig.

10 during or immediately after the placement of layer 37.

If this is desirable, heavily doped zones 40 as

shown with a dashed line of the same conductivity type as the first area 2 is arranged in the described structure (see fig. 2) to prevent an inversion channel from being formed between adjacent circuit elements, e.g. between area 4 and zone 16. This can e.g. is carried out by local doping of the etched silicon surface in fig. 5 with phosphorus for the formation of the oxide sample 10. In the example described above, however, it will be abundant for the uncer formation of the oxide sample 19, the donors in the n-type silicon area 2 will be forced into the area 2 after the oxidation of the silicon, and consequently an accumulation of donor atoms is formed at the transition surface with the oxide layer 10 in region 2, which is generally sufficiently large to prevent the formation of a p-type inversion channel.

The device according to the invention can further comprise field effect transistors with more than one gate electrode, as well as others

circuit elements, e.g. bipolar transistors. As an example of this, fig. 15 an n-channel tetrode field-effect transistor C (source—

and drain zones 6 and 7 of n-type, gate electrode layers 58 and 59, oy 60 of n-type), a p-channel field-effect transistor D (source and drain zones l6 and 17 of p-type, gate electrode layers 6l and 62, oy 62 of p-type) and a bipolar lateral pnp transistor E (emitter and collector zones 64 and 65 of p-type with an intermediate base of n-type forming part of region 2 of n-type). Zones with the same reference number as in the previous example have the same function and are of the same conductivity type as indicated there. The eyes 60 and 62 can be placed at the same time as and. in the same way as the source and drain zones 6, 7, 16 and 17, the gate electrode layers 58, 59, 6l and 62 being used as masking.

In such a structure, a bipolar transistor can advantageously be arranged in a different way. E.g. as shown in fig. 16, a pair of complementary field effect transistors FG can be combined with a lateral bipolar transistor H. Components with the same reference number have the same function as in fig. 1-14" The bipolar transistor H is in this case electrically isolated from the remaining part of the substrate 2 by means of a pn junction 71" According to the invention, this structure can be produced in a simple way as follows. One starts from an n-type silicon plate 2, in which a recessed oxide layer 10 is arranged, on which gate oxide layer parts 9,19,80,77 and 8l and polycrystalline gate electrode layers 8,18,78,76 and 79 are placed. application of the same masking and diffusion operations as described above, regions 4 and 70 of p-type, zones 16,18,72 and 73 of p-type and zones 6,7,74 and 75 of n-type are preferably formed using of the oxide sample 10 and the polycrystalline gate circuit layers 8,18,78,76 and 79 as masking. Zones 4 and 70 can advantageously be placed in the same diffusion operation, zones 16, 17, 72 and 79 can also be placed in the same diffusion operation and zones 6,7,74 and 75

can also be placed in the same diffusion operation. The gate electrode layers 8.18.78.76 and 79 can be formed and doped simultaneously and the gate oxide layer parts 9.19.80.77 and 8l can also be formed simultaneously. The zone 70 of p-type forms

the base zone and the n-type zones 74 °S 75 form the emitter and collector zones of the lateral bipolar transistor. The extra gate electrodes 76, 78 and 79 which are separated from the area 70 by the gate oxide layer parts 77,

80 and 8l are connected to the base zone 70 by the metal layers 84 and 85

via diffusion contacts 72 and 73 so that any diffusion current channels formed under electrodes 76, 78 and 79 are suppressed. Such diffusion current channels can e.g. causing short-circuits between emitter and collector and the auxiliary gate electrodes connected to the base dannBr itself an important improvement of a vertical or lateral bipolar transistor. See also gate electrodes 95 and 106 in fig. 17 and l8. The direct current connection 86 between the polycrystalline silicon layer 76 and the metal layer 85 is only shown schematically with a line. The extra port electrodes 76, 78 and 79 can be removed in certain cases. It is clear that the bipolar transistor H described with reference to fig. l6 provides particularly advantageous possibilities for combining and off

the field effect transistor structure F with bipolar elements, in particular bipolar transistors.

Another particularly advantageous combination of the field effect transistor structure F with a bipolar transistor K as shown in fig. 17

can be achieved in a very simple way. In this case, K is a vertical transistor whose collector region is formed by n-type substrate region 2, whose base region is formed by p-type region 90 and whose emitter region is formed by n-type region 93 joining it recessed oxide monster 10. The collector contact is formed by the metal layer 97 and the lightly doped zone 94 of n-type is limited by the recessed monster 10. The base contact is formed by the metal layer 98 and the heavily doped zone 92 of p-type. In order to prevent the formation of the leakage current channel from the emitter to the collector, an additional gate valve is arranged

trode 95 of polycrystalline silicon which is separated from area 90

by an oxide layer 96 and is connected by direct current to the base zone through the metal layer 98. This additional gate electrode can be sloyed when there is no danger of channel formation.

The starting material here is also an n-type silicon substrate 2 in which a recessed sample 10 is arranged, on which the gate oxide layer parts 9, 19j96 and the polycrystalline gate electrode layers 8, 18 and 95 are arranged. Areas 4 and 90 of p-type, zones 16,17 and 92 of p-type and zones 6,7,93 and 94 of n-type are preferably arranged using the oxide sample 10 and the polycrystalline gate electrode layers 8,18 and 95 which masking. Also in this case, the zones 1-4 and 90 can advantageously be placed simultaneously in the same diffusion operation, as can the zones 6,7,93 and 94 and the zones 16,17 and 92. The gate electrode layers 8,18 and 95 can also be placed and doped in the same operation and the gate oxide layer parts 9, 19 and 96 can also be placed by the same oxidation and the mask, ng. T'

It is clear that the invention is not limited to the described examples, but that many variations are possible for the person skilled in the art without going beyond the scope of the invention. E.g. a semiconductor material other than silicon, other insulating and masking layers and other metal layers can be used, and the gate electrode layers need not consist of polycrystalline silicon, but can be formed e.g.

of metal layer. The indicated conductivity types can be exchanged for the opposite conductivity type. The sequence in which the different zones, insulating layer and gate electrodes are placed can vary if one<1>only achieves the desired results. The first area 2 can also consist entirely or partially of an epitaxial layer which is arranged on a substrate and the the second area and the insulation sample 10 can extend through the entire thickness of the layer or only a part of the thickness.

This can be seen, for example, of fig. l8 where the area 2 of n-type

has the form of an epitaxial layer which is arranged in a substrate 100

of n-type. A buried layer 101 is arranged between layer 1 and substrate 100. Adjoining layer 101 is a p-type region 102 that completely surrounds a region 103 of layer 2, in which region 103 forms the base zone of a pnp transistor whose surface zone 104 of The p-type and areas 101 and 102 of the p-type form the emitter or collector zone. The heavily doped zone 105 of n-type serves to provide contact. The extraport electrode 106, which is not always necessary, is

preferably of polycrystalline silicon and is connected to the base 103 of the transistor and serves to separate the diffusion zones 10^ and 105 and prevent the formation of a diffusion inversion channel. The zones 4 and 102 are preferably placed simultaneously in the same operation and so are the zones 6,7 and 105, and the oxide layers 9 and 107 and the gate electrodes 8 and 106.

In addition to diffusion from a phase phase or by ion implantation, the doping of the various zones can finally also be carried out by diffusion, e.g. from a doped oxide layer.

Claims (20)

Semiconductor device with a semiconductor body comprising at least one field effect transistor with an insulated gate electrode, a first region of a first conductivity type and a second region of a second conductivity type which joins the surface and forms a pn junction with the first region, source and drain region thereof first conductivity type joining the surface and arranged in the second region, at least one gate electrode layer arranged between the source and drain zones and separated, from the semiconductor body by an insulating layer, characterized by a pattern of electrically insulating material which is at least partially recessed in the semiconductor body and with a first portion substantially completely surrounding the second region, which pn junction between the first and second regions joins the recessed pattern also joining the source and drain regions, and with at least one additional portion substantially spoken completely surrounds a further likewise to the surface bordering part of the semiconductor body in which a further semiconductor connection element is located. 2. Device according to claim 1, characterized in that the recessed pattern further surrounds a further part of the first area which joins the surface, in which part there are arranged to the surface end zones and the derivation zone of the second conductivity type of a field effect transistor which is complementary to said field-effect transistor and whose source and drain zones join the recessed pattern, and at least one gate electrode layer is separated from the semiconductor body by an insulating layer arranged between the source and drain zones. 3. Device according to claim 2, characterized in that the material in the recessed pattern that surrounds the second area also partly belongs to the recessed insulation material that surrounds the further part of the first area. 4. Device according to one or more of claims 1-3, characterized in that the recessed insulation pattern surrounds a third area of the second conductivity type which joins the surface, joins the recessed insulation material and forms a pn junction with the first area, in which third area is arranged at least one further zone of the first conductivity type which joins the surface and together with the third area forms part of a bipolar circuit element. 5. Device according to claim 4, characterized in that the mentioned additional zone of the first conductivity type joins the recessed pattern, and the third area forms the base zone in a vertical bipolar transistor whose emitter and collector zone are formed by the additional zone resp. the first area. 6. Device according to claim 4, characterized in that two zones of the first conductivity type which join the surface are arranged in the third area, which zones form emitter and collector zones in a bipolar lateral transistor whose base zone is the third area. 7. Device according to claim 5 or 6, characterized in that extra gate electrodes are arranged over the third area and are separated from the surface of the semiconductor body by an insulation layer and are preferably connected by direct current to the base zone of the bipolar transistor to prevent the formation of diffusion current channels. 8- Semiconductor device according to claim 1, characterized in that the second region of the second conductivity type has such a doping profile that in a zone bordering the surface the doping concentration has a maximum value from the surface inward, which maximum value is so large that it prevents Itanal formation along the set isolation pattern between the first area and the source and drain areas of the second area. 9. Device according to claim 19, characterized in that the source and diversion areas in the second area are located entirely within the zone bordering the surface. ' 10. Method for manufacturing a semiconductor device according to one or more of the preceding claims, wherein a second region of the second conductivity type which forms a pn junction with the first region and joins the surface of the semiconductor body is arranged in a first region of the first conductivity type which likewise joins the mentioned surface, and where the source and drain zone of a field effect transistor is arranged in the second area, characterized in that a layer that protects against oxidation is placed on part of the surface of the first area, that a layer-shaped oxide pattern which is at least partially recessed in the semiconductor body and which practically completely surrounds a surface part of the first area, is then placed by oxidation on the surface parts that are not covered by the protective layer, that a doping material which determines the second conductivity type is placed from the outside in the said surface part to form the second area, the recessed oxide pattern protecting against the doping, that a doping material which determines the first conductivity type is placed in the second area from the outside via surface parts of the second area for i the smallest to form the source and diversion zone, ie the recessed oxide pattern protects against the doping, and that at least one gate electrode layer is placed which is separated from the second area by means of an electrical insulating layer and which ..extends over part of the surface of the second area between the source and drain zones. 11. Method according to claim 8, characterized in that before the placement of the source and diversion zone, at least one gate electrode layer is placed, after which the doping material which determines the first conductivity type is introduced into the second area, the gate electrode layer or layers also being used as a protective layer against the doping material. 12. Method according to claim 8 or 9, characterized in that after the introduction of the doping material which determines the second conductivity type and preferably before the placement of the gate electrode layer, the doping material diffuses out of the semiconductor body through the surface part which is occupied by the second area and which is limited of the recessed oxide pattern, in a room with an atmosphere of reduced pressure, whereby the doping concentration in a zone in the second region joining the surface acquires a profile that increases to a maximum value from the surface inwards. 13. Method according to claim 10, characterized in that the source and diversion zone are arranged completely within the said zone in the second area. 14. Method according to one or more of claims 8-11, characterized in that a recessed oxide pattern is placed which surrounds at least a further part of the first area, and after the formation of the second area, a doping material is introduced which determines the second conductivity type , from the outside in the further part of the first area to at least form the source and drain zone in a second field effect transistor which is complementary to the first transistor, the recessed oxide pattern being used as masking, and that at least one gate electrode layer is placed on it further part between the source and drain zone, which layer is separated from the semiconductor body by an electrical insulating layer. 15. Method according to claim 12, characterized in that before the placement of the source and drain zone for the complementary, second field-effect transistor, at least one gate electrode layer is placed on the further part, after which the doping material which determines the second conductivity type is introduced into the further part, which gate electrode layer is used as masking against the doping material. 16. Method according to one or more of claims 8-13, characterized in that to form the gate electrode layer or layers and any interconnections, a layer of polycrystalline silicon is placed in which the layer, the layers and the connection pattern are formed by etching, and that in order to reduce the resistance of the polycrystalline silicon and give the threshold voltage for at least one of the field effect transistors a desired value, the polycrystalline silicon is doped in at least one of the gate electrode layers with a donor or acceptor material. 17. Method according to claim 14, characterized in that the polycrystalline silicon is doped with phosphorus. 18. Method according to claim 14 or 15, characterized by at least one gate electrode layer is doped with a doping material that is also used during the doping of the source and drain zone in one of the field effect transistors. 19'. Method according to claim 16, characterized in that at least one of the gate electrodes in one of the field effect transistors is simultaneously doped with the same doping material that is used when doping the source and drain zone in the field effect transistor. _. 20. Method according to one or more of claims 8-17, for manufacturing a device according to one or more of claims <4>-7, characterized in that the second and third areas of the second conductivity type are placed at the same time, that the source and drain zone in the first field-effect transistor and the further zone of the first conductivity type are placed at the same time, and that any gate electrodes and the associated insulation layer are placed at the same time.