NL8403628A - Processing of machine code instructions - using instructions with two part operation code, first being of normal structure and second acting as virtual operation code - Google Patents

Abstract

A data processing system is structured to enable machine code instructions to be readily generated when operating with either of two types of languages, i.e. high level languages or reduced instruction set languages. The central processor operates together with a specific register format consisting of general registers (RO-R7), a zero's register (8), a one's register (9), a program counter (PCR), a stack pointer register (SPR), a condition code register (CCR), and a sign extend register (SER). In addition to the standard registers there are an interpreter programme counter register (IPLR) and an operation extend register (OPER) that provide the necessary facilities for machine code conversion. The instruction words used in the system consist of an operation code and an operand. The operation code is in two part format, with the first part being of a normal structure and the second part acting as a virtual operation code to facilitate the conversion.

Description

* -. s PHN 11.228 1 N.V. Philips' Incandescent lamp factories in Eindhoven

Method for handling machine-coded instruction words, and data processor for performing the method.

The invention relates to a method for treating machine-coded instruction words by means of a data processor provided with a memory for storing said instruction words, each of which contains a code part and at least one operand descriptor part, which code parts belong to a finite set which are a first and a second class is divided, the method comprising the following steps: (a) retrieving under the control of the data processor a first instruction word indicated by a program counter; (B) decoding the code part of the first instruction word and examining to which of the classes the code part of the first instruction word belongs; (c1) performing the instruction word operations given by the first instruction word with a code part belonging to the first class; (c2) for instruction words with a code part belonging to the second class, perform the following steps: (c2-1) storing the current program counter in a dedicated program counter register reserved therefor; 20 (c2-2), based on the coding portion from the first instruction word, generating a memory address to which a second instruction word is located, the second instruction word being the initial instruction of a series of instruction words determining the meaning of the first instruction word 25; (c2-3) setting the current program counter to said memory address; (c2-4) treating said set of instructions; (c2-5) setting the current program counter to a value 30 determined by the program counter contained in the additional program counter register.

Such a method is known from the article "Instruction set extension" by R.L. Bains, R.L. Hoffman, .. G.R. Mitchell and o V V »y £. c? *, * PHN 11.228 2 F.G. Soltis, published in I.B.M. Technical Disclosure Bulletin, Vol. 18, no. 7, December 1975, pages 2250-2252. In the known method, machine-coded instruction words are the result of translation procedures applied to a program text presented by a programmer. The program text is written in a well-known computer language such as PASCAL or FORTRAN. The compiler and the assembler of the data processor (also called computer system) translate the program text into a system of machine-coded instruction words which are then stored in memory 10 during the processing of the program text. For example, an instruction word is 32 bits wide. Of these, for example, 8 bits are intended for the code part and 20 bits for the operand descriptor part. With an 8 bit wide code section

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contains a collection of opcodes maximum (2 =) 256 different opcodes. In the known method, this set is divided into two classes, namely the valid (first class) and the invalid (second class) opcodes. The content of the code section determines the nature of the operation (s) to be performed for handling the instruction. For example, an opcode may indicate a register loading operation or a jump to a subroutine. The purpose of decoding is to convert the code part into control information for the computer system. The order in which the instruction words are retrieved from memory and processed by the data processor is indicated by the program counter.

In the known method, the valid code parts from said set have a fixed meaning which is recognized during decoding. A code part with a fixed meaning is executed in the known manner after decoding. Depending on the capacity of the computer system, the opcode set contains many or few different elements. The. system programmer must work with the given set of opcodes and the fixed meaning given by the computer system during decoding. The known method provides a solution for treating instruction words with an invalid opcode (second class). When an invalid opcode is decoded, the current program counter is stored in a supplementary program counter register and a memory address is formed on the basis of the code part from the first instruction word. That memory address is formed down by making the most significant bits zero in a shift register and for the least significant bits S A A 1 Η 9 A 'Q * ΐ b ν ν d Λ

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.2 11.228 3 of the memory address to use the opcode. In order that memory address, a second instruction word is located which is the initial instruction of a series of instruction words determining the meaning of the first instruction word. Thus, an instruction word with an invalid code portion is translated into an executable instruction.

A drawback of the known method is that with instruction words containing a code part that belongs to the second class (invalid opcode), the operand-10 descriptor part of the relevant instruction word is not taken into account when translating it into an executable instruction and executing it. . As a result, the operand descriptor part of such an instruction word is used inefficiently and thus also the computer system.

The object of the invention is to realize a method for treating machine-coded instruction words, wherein the operand descriptor part of the instruction word with a coding part belonging to the second class for coding operand descriptors is available, and in this way the system programmer is given the freedom for the choice of the meaning of the code parts of the second class. Another object of the invention is to realize a method in which a higher efficiency is also obtained for higher programming languages.

To this end, a method according to the invention is characterized in that in the case of a compelling series of instruction words the operand descriptor part is loaded from the first instruction word into a first index register by at least one third instruction word.

Loading the operand descriptor part into a first index register allows the processing of the operand descriptor and thus also makes the operand descriptors available for encoding. In addition, by using an index register, the existing hardware is used to decode the operand descriptor. The system programmer now has 3Q the ability to store information to be processed in the descriptor part pp, which information is then processed by compliant sequence of instruction words.

In an alternative embodiment, a method according to the invention is characterized in that for instruction words with an opcode-35 part belonging to the second class, at least the operand descriptor part of the first instruction word is loaded into an index register reserved for that purpose before the setting of the memory address. By loading the operand descriptor into a second index register before

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PHN 11.228 4 to generate the memory address, program instructions from said series of instruction words can be saved.

A first preferred embodiment of a method according to the invention is characterized in that in the execution of the third instruction word the content of the supplementary pr ogr ammatellerreg is used for locating in the memory of the operand descriptor part from the first instruction word .

Because the current program counter is stored in the supplementary program counter register, it is thus possible to locate quickly and simply where the operand descriptor of the first instruction word is located in the memory. After all, the operand descriptor is located in the operand descriptor part of that first instruction word indicated by the program counter when retrieving under step (a) of the method according to the invention.

A second preferred embodiment of a method according to the invention is characterized in that in said series of instruction words, the operand descriptor part from the first instruction word is processed by at least one fourth instruction word. The operand descriptor of the first instruction word stored in an index register 20 is treated by the fourth instruction word. The descriptor part of an instruction word with a coding part belonging to the second class is thus used for the coding of operand descriptors.

A further preferred embodiment of a method according to the invention is characterized in that the generation of the memory address 25 for the second instruction word comprises the following sub-steps: (1) forming a table address from a memory table by adding to the coding part of the first instruction word a value previously stored in a dedicated operation extension register; (2) addressing the memory word located at the generated table address; (3) retrieving the memory word at said table address, which memory word constitutes the memory address.

The use of a memory table offers the possibility to make an inventory of specialized instruction collections with which instruction words, which contain a code part belonging to the second class, are treated.

The invention also relates to a data processor for

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See a memory for storing machine-coded instruction words, each containing a coding part and a descriptor part, which coding parts belong to a finite set divided into a first and a second class, which data processor further comprising a program counter, an address generator and a coding decoder, which coding decoder is provided with first means on coding parts of the first and second class separately recognizable and with second means for controlling a recognized coding word of the second class with a control signal. which data processor further comprises a supplementary program counter register and transfer means, which transfer means have a first control input for receiving the control signal and are further provided for transferring the contents of the program counter register to the supplementary program under control of a received control signal. yesterday, and wherein the address generator is provided for generating, under control of the control signal, a memory address at which an initial instruction word of a series of instruction words for treating a descriptor portion is located.

Such a data processor is also known from the aforementioned article "Instruction set extension".

A data processor according to the invention is characterized in that the data processor is provided with an operation extension register which contains a second control input for receiving the control signal and has an output connected to the address generator.

As a result, the address generator can be realized in a simple manner if the operation extension register contains a collection of addresses or address parts.

It is advantageous that the data processor further comprises a second index register which contains a third control input for receiving the control signal and a data input connected to the memory for receiving the operand descriptor part of an instruction word under the control of the control signal .

This also saves program instructions.

The invention will be further described with reference to the drawing, in which: figure 1 shows a first exemplary embodiment of a register architecture of a computer system according to the invention.

Figure 1a schematically shows the method according to the invention '4C.' e 2e * ï PHN 11.228 6 illustrates on the basis of a flow chart.

Figure 2 shows a first computer program by means of which a first embodiment of the method according to the invention is illustrated.

g Figure 3 (I to VI) shows the result of a handling of the coirputer program from figure 2.

Figure 4 (a through f) shows some different opcodes and their associated instruction word format, and Figure 5 (a through f) shows some different descriptor parts 10 within an instruction word.

Figure 6 shows a second embodiment of a register architecture of a computer system according to the invention.

Figure 7 shows a second co-computer program by means of which a second embodiment of the method according to the invention is illustrated.

Figure 8 (I to net V) shows the result of a processing of the computer program from figure 7.

A data processing system or a computer that has to process an order will do this by handling a program suitable for processing that order. That program is written in a well-known programming language such as, for example, PASCAL, FORTRAN or BASIC. However, these programming languages are user languages that are first translated by machine-encoded instructions in order to handle the program. This translation from user language to 25 machine-coded instructions usually takes place in two steps. A first step involves translating user language into "Assembly language" and a second step of translating "Assembly language" into "machine instructions". The first step is handled by a "compiler" and the second by an "assembler". The compiler and assembler 3Q are both translation programs that are part of the computer system. The system programmer took the architecture of the computer into account when creating the compiler and assembler (CA = Computer Architecture, ie the appearance of the machine from the point of view of the system programmer).

35 In Computer Architecture, a distinction is made below between two types of architecture, namely HLL (High Level Language) and RISC (Reduced Instruction Set Computers) architecture. HLL architecture mainly means that the computer hardware is provided with

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€ PHN 11.228 7 an instruction set suitable for processing higher languages. This narrows the gap between user language and machine instructions. RISC architecture essentially means that the machine instructions are so simple that the hardware can achieve maximum performance. However, with RISC architecture, the translation of a user program is considerably more difficult.

The advantages of these two mentioned types of computer architecture are now combined in a data processing system according to the invention. In fact, such a data processing system includes a simple machine whose instruction set is made extensible to efficiently handle HEL-type operations.

The computer system according to the invention comprises a central processing unit (CPU), with, for example, a register architecture.

Figure 1 shows a first exemplary embodiment of a register architecture of a computer system according to the invention. The register Rq through as well as the register ZERDR (8), CNER (9), PCR (Program Counter Register) (B), SPR (Stack Pointer Register) (D), CCR (Condition Code Register) (E) and SEXR (Sign Extend Register) (F) are the usual known registers of a computer with a conventional register-20 architecture. The registers IPCR (Interpreter Program Counter Register) (C) and OPER (Operation Extend Registers) (A) are an addition to the CPU which expands a register architecture for application of the invention, however it should be noted that the register OPER is optional. In the simplest embodiment, the register IPCR suffices. The use of the register IPCR by the computer system during the processing of a program is controlled by the OPCODE PART of an instruction word to be treated, or simply referred to as the OPCODE (Operation Code).

Figure 6 shows a second exemplary embodiment of a register architecture of a computer system according to the invention. The registers Rq through Rc as well as the register OPER and IPCR are identical to the registers of the same name from the first exemplary embodiment given in figure 1. The registers (8) and (9) now call Rg and Rg. The registers PCR (D), SPR (E) and CCR (E) perform the same task as the 35 eponymous registers of the first embodiment, but now have a different order in the system. New for the second embodiment is the register VIR (B), the meaning of which will be explained later in the description.

54 - ..: 3 28 PHN 11.228 8

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In this computer system, the OPCODES are divided into two classes, namely a first class containing "normal" opcodes and a second class containing "virtual" opcodes. The code decoder of the computer system is implemented in such a way that it recognizes from the 5 bit pattern of the opcodes which class it belongs to. For example, all opcodes that have the most significant bits (MSB) of the value "0" can be recognized as "normal" opcodes and all the opcodes that have the value of "1" as MSB can be recognized as "virtual" opcodes. This creates a distribution in which each class contains the same number of 10 opcodes. However, it should be noted that any other distribution is also possible. With a certain distribution, there is always a specific implementation of the code decoder. It will be clear that each class must contain at least one opcode.

The manner in which instructions with normal or virtual op-code are handled by a computer system according to the invention is schematically illustrated with reference to the flow chart of figure 1a. After reading (50) an instruction word, it is examined (51) whether the opcode belongs to the class of the virtual or the normal opcodes.

2o In case the code decoder has decoded an opcode belonging to the class of normal opcodes (N), then the associated instinct is treated in the known manner (52). However, in the event that the code decoder has decoded an opcode belonging to the class of virtual opcodes (V), regardless of the 2g content of the associated instruction, the following operations are performed: reg [IPCR]; = reg (PCR] (53) reg [PCR): = mem (reg [OPER] + opcode] (54)

The operation reg (IPCR) means: = reg (PCRj that the content 3Q of the PCR register is transferred into the IPCR register (: = in programming language stands for "becomes"), in other words the address of the instruction designated by the program counter (current program counter), is loaded into the register IPCR The action reg [PCR]: = mem (reg [oper) + opcode] means that in the register PCR is loaded the memory word (in this case an address word) which is stored in the memory location with address reg (OPER} + opcode. The address reg [OPER ~] + opcode is composed by adding the contents of register OPER to the value as given in g 4 0 co 18 é. 'ί PHN 11.228 9 code part of the instruction word This operation reg [pcr]: = mem [reg [OPER] + opcode] means that a new address for the program counter is loaded into the PCR register.

It is also possible to generate this new address by actions other than by 5 the operation reg [PCR]: = mem [reg [OPER] + opcode]. Possible other actions are for example: a) Reg [PCRj: = reg [OPERJ + opcode

The new address is immediately determined without a read operation from the memory.

10 b) Reg [pcr] I = opcode + fixed address

This is an action that is applied when, as already mentioned, the OPER register is not used. The new address composed here by adding a fixed address to the code part of the instruction word.

15 c) Reg [pcr]: = mem [opcode + fixed address]

Also in this operation no use is made of the OPER register.

However, this operation does contain a memory read operation. This new program counter address now contains a first instruction of a series of instructions which interpret the meaning of the instruction word with virtual opcode (55). This sequence of instructions is always closed by a final instruction from the program immediately following the instruction with virtual opcode which has accomplished the processing of said sequence. For example, one last instruction is of the form 25 reg [pcr]: = reg QlKsQ (56)

The program counter is then reset to the value it had at the beginning of the execution of the instruction with the virtual code part.

The useful effect of a virtual opcode is that a piece of code is executed for every 30 virtual opcode. In this piece of code ("the interpreter" of the virtual opcode) it is possible to efficiently refer to the argument descriptor (s) of the virtual opcode if IPCR is used as index register.

If the computer system now has a register architecture as shown in Figure 6, then when decoding an opcode belonging to the class of virtual opcodes, in addition to the operations (53) and (54), a further operation (150) is performed, namely : reg jyn0: = \ I-rD · - · Λ «S ^ Ji 3 ;; 'Ij * \' PHN 11.228 10

The content of at least the location descriptor part of the instruction register [j.R ^ of the computer system is hereby transferred into the register VIR.

An instruction with a virtual opcode differs mainly from an instruction JUMP SUBROUTINE which has a normal opcode in that during the processing of the subroutine the program counter is temporarily stored in the memory. On the one hand the memory write operation required for this takes extra processing time, on the other hand it is therefore not possible (without extra processing time) to use the old program counter as an index register for retrieving argument descriptor (s).

Figure 2 shows a first computer program by means of which a first embodiment of the operation of a computer system according to the invention will be further elucidated. The program 15 is intended as an example only. It will be clear that a computer system according to the invention is not limited to executing only programs of this nature.

Five columns can be distinguished in figure 2. The first column contains the memory addresses of the instructions. The second column 20 contains the instructions written in machine code (hexadecimal notation).

The third and fourth columns contain the instructions written in "Assembly language" and the fifth column contains comments on the instruction.

Before going deeper into Figure 2, some general aspects of the instructions 25 will be described with reference to Figures 4 and 5 in order to make the reading of the program and its processing more clear. Figures 4 (a) through (f) show opcodes and their associated instruction word format. An instruction as noted in machine code (Figure 4 or second column Figure 2) contains 32 (4x8) bits. Bits 31 to 24 always contain the opcode.

g 30 Since the code section contains 8 bits, 2 = 256 different opcodes are possible. In the example of Figure 2, the opcodes 00 to F8 belong to the class of virtual opcodes and the opcodes F9 to FF belong to the class of normal opcodes. The format of the other bits (0 to 23) depends on the nature and class to which the opcode belongs.

Figure 4 (a) shows a pattern of an instruction which is opcode one of the normal opcodes LOADADRESS (F9), LOADVALUE (FA) or STORE (FB). In this instruction, bits 20 through 23 contain it

Af λ ^ -'ï η λ a .a ··; _ ·. ·. -r t <* «· '«. · «V tl» PHN 11.228 11 number of the register (RGN) to which the operation given by the opcode relates, and bits 0 to 19 contain the location descriptor (LCDSC). The contents of this location descriptor will be discussed further below.

5 Figure 4 (b) shows the pattern of an instruction that has the opcode as the normal opcode MONADIC (PC). In this Instruction, bits 20 through 23 contain the number of the register (RGN) to which the operation given by the opcode relates, and bits 16 through 19 indicate the nature of the Monadic operation (MNPC)) (Increment, decrement, etc.). The other bits do not contain information relevant to this invention.

Figure 4 (c) shows the pattern of an instruction which is opcode as the normal opcode DYADIC (FC). In this instruction, bits 20 through 23 contain the number of the first register (RGN) 15 and bits 12 through 15 contain the number of the second register (EGT) to which the operation given by the opcode relates. Bits 16 through 19 indicate the nature of the Dyadic operation (DPC) (addition, subtraction, logic AND, etc.). The other bits do not contain information relevant to this invention.

Figure 4 (d) and 4 (e) respectively show the pattern of an instruction that is opcode as the normal opcode JUMP SUBROUTINE (EE) and JUMP CONDITIONAL (FF), respectively, where for the instruction just opcode FF the condition (CND) is given by bits 20 to 23. Bits 0 through 19 each contain the location descriptor 25 (LCDSC). Now if the computer system decodes the opcode "FE", the following operations are performed: mem (reg (SPrQ: = reg (PClO reg jSPRl: = reg {jSPR? + 1 reg [PCR]: = effa (LCDSC) 30 Where " effa "stands for" effective address ".

When decoding the opcode "FF", if the condition (CND) is met, the following operation is performed: reg ^ PCR]: -effa (LCDSC) (The program counter (Reg [PCR)) is not remembered since with a Jump Conditional no return takes place.

Figure 4 (f) shows the pattern of an instruction with a virtual opcode (00; ...; F8). Bits 0 to 23 are used here depending on the interpretation routine. This will be discussed later in the description.

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The location descriptor describes the address associated with the instruction operand. The computer system is provided with hardware means to interpret this location descriptor. Figure 5 shows a number of examples of location descriptor parts within an instruction word. For each location descriptor, bits 16 through 19 each indicate the nature of the descriptor, which will be described below for each of parts (a) through (f) of Figure 5.

(a) In Figure 5 (a), the word "0000" represents a register operation related to the register given by bits 12 through 10 through 15. The contents of bits 0 through 11 are for the description of the invention not relevant.

(b) In Figure 5 (b), the word "0001" represents normal index operation. Of these, the resulting address a + Reg [rQ where a represents the number given by bits 0 through 11 and n represents the register number given 15 through bits 12 through 15.

(c) In Figure 5 (c), the word "0010" stands for an index operation preceded by a pre-adjust indexed operation.

Such an operation takes place in two steps: the address given by 20 a + Reg [η] and also

Reg [η]: = a + Reg (nl (a and n have the same meaning as quoted above).

(d) In Figure 5 (d), the word "0011" represents an index operation followed by a post-adjust index operation. Such an operation also takes place in two steps: the address was given by Reg jn]; and also 30 Reg Cn3: = a + Reg \ n} (with analogous meaning for a and n).

Thus, in an index operation accompanied by an adjustment operation, both a value and an address are determined. The use of the address is determined by the code part.

(E) In Figure 5 (e), the word "0100" represents a number whose value is given by bits 0 through 15. ("immediate") (f) In Figure 5 (f), the word "1111" for an interpretation operation. The contents of the register numbered t) A ri 9 8 PHN 11.228 13 by bits 12 to 15 are considered location descriptors. The contents of bits 0 through 11 are intended for data to be used in the sequence of instructions initiated by an instruction with virtual coding sections. Using the data from Figures 4 and 5, the computer program illustrated in Figure 1 2 are treated. The result of the elaboration of this program is illustrated in Figure 3 (I through VI). In each further description, in addition to the instruction, it will be stated in brackets in which part of Figure 3 the relevant instruction has been worked out.

The first instruction of the computer program is located in memory location with address 0 and reads: FAD47FFF; LOADVAL SPR, $$ 7FFF (Figure 3 (1) instr. 1).

The opcode "FA" indicates that this is an instruction with normal opcode 15 (Figure 4 (a)), namely the instruction "LOAD VALUE". The register number "D" indicates that the register to be used is the register SPR (Figure 1). The location descriptor contains the number "47FEF", herein the number 4 indicates that it is a location descriptor of the type shown in Fig. 5 (e), namely a number (immediate), namely the number 7FFF. This instruction means: "Load (FA) in the Stack Pointer Register (SPR) (D) the number (4) with value 7FFF". The number 1 is now stored in the program counter register (PCR), which means that the next instruction is located on memory 1. It should be noted that in this exemplary embodiment, the register ZEROR is each loaded with the value "00000000" and the register ONER is each loaded with the value "00000001". The constant values 0 and 1 were often used. Thus, it is convenient to have these constant values in a register so that they can be retrieved by simple register operations.

The second instruction of the computer program is located at memory location 1. This second instruction reads: FAA47F00? LOADVAL OPER, # $ 7FOO (Figure 3 (1), instr. 2).

Analogous to the first instruction, this is an instruction with normal opcode "LOADVAL". The register number "A" denotes the register OPER (Figure 1) 35. So this instruction means: "Load the number with value 7F00 in the Operation Extend Register (OPER)". The number 2 is now loaded in the register PCR -inmiHr | pl s.

The third instruction reads: * 'Λ * ’2- Ό * Λ V' w * PHN 11.228 14 FE018400; JSR $ 400 + (ZEROR] (Figure 3 (1), instr. 3).

The opcode "FE" indicates the instruction with normal opcode "JUMP SUBROUTINE" (figure 4 (d)). The location descriptor contains the number "18400", herein the number "1" indicates that it is a normal index operation 5 (Figure 5 (b)). The number "8" indicates the register ZEROR, and the number "400" indicates the displacement. Implementation of this instruction now yields: a) item [reg [SPRl]: = reg {pCr] mem Jtfff]: = 00000003 ig This means that the number 3 is written on memory location with address 7FFF. This means that the address of the next instruction (memory address 3) at memory location 7FFF is remembered. 'b) reg [spr]: = reg [SPR] + 1 reg Qspr): = 00007FFF + 1 = 00008000 15 c) reg [PC ^: = effa (LCDSC) effa (IX3DSC) stands for the effective content of the location descriptor , which for this example is given by 400 + [ZEROR). However, since 00000000 is in the ZEROR register, effa (LCDSC) = 00000400 20 reg Q? CR): = 00000400

This means that the program counter now indicates the memory location with address 400. So a jump has been made to memory location with address 400.

The fourth instruction, located at memory location with address 400, reads: FA03B001; LOADVAL R0, [PCR] ++ 1 7FfFFFFF: $ 7FFFFFFF (Figure 3 (1), instr. 4).

The register number of this instruction with normal opcode LOAD VALUE is "0". In the location descriptor with value "3BQ01", the number 3 3g indicates an index operation followed by an adaptation operation (Figure 5 (d)). The letter B indicates that the match refers to the PCR register (Figure 1) and the number "001" indicates the amount of the match. So this instruction means:

Reg | CÜ: = mem [reg iPCÖj 35 Re9 [0]: = nem [40]]

In the register R0, load the value stored at the memory address given by the contents of register PCR and increase

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f-. "V ***" · PHN 11.228 15 then the contents of register PCR with the number "OOI". The value (400 + 1 =) 401 is stored in the PCR register. At address 401 there is the value 7FFFFFFF which is now stored in the register R0. The adjustment operation then yields: 5 reg (ÈCR]: = reg [PCR] + 1 reg QaQ; = 401 +1 reg (jdTl: = 402

The fifth instruction located at memory location 402 reads: 10 FAB2DFFF; LQADVAL PCR, -1-H- [SPR) (Figure 3 (1), instr. 5).

The register number "B" designates the register PCR. In the location descriptor with value "2DFFF", the number 2 indicates an index operation, preceded by an adjustment operation (figure 5 (c)), the letter D stands for the register SPR and the hexadecimal number FFF (2-complements-15 notation ) stands for "-1", which indicates the amount of adjustment, reg (SPR): = reg (SPR) -1 reg [SPR): = 00008000 -1 reg [SPR]: = 00007FFF reg [pCR): = mem Qreg [SPrQ 20 reg [pCR): = mem 7FFF

reg ^ PCRj: = 00000003 because, as indicated in the third instruction, the value "3" is loaded on the memory location with address 7FFF. Reading from memory and loading 00000003 into the register PCR means that the subroutine has ended and that the normal program is now resumed with the instruction loaded at address 3 of the memory.

The sixth instruction then reads: FA742000; LOADVAL R7, # $ 20QQ (Figure 3 (II), instr. 6).

This instruction means: "Load in the register R7 the number with value 30 2000".

The seventh instruction reads: 00040020; ADDSTACK # $ 20 (Figure 3 (II), Instr. 7).

The opcode "00" indicates that this is an opcode from the class of virtual opcodes (00 6 ^ 00, ..., F8j). The computer system decoder decodes this virtual opcode and thus the system will perform the following operations as a result: a) reg {ICFF3: = reg [PCR] b) reg (PCQ: = mem [reg (OPER) + OPCODE) -Λ ί Λ '"too PHN 11.228 16

Application of these operations to this seventh instruction then gives: a) reg (iPCR]: = reg [PCR] reg (ÏPClÜ: = 00000005

Thus, the contents of the PCR register (original program counter-5 position) are loaded into the IPCR register. In contrast to a JUMP SUBROUTINE instruction (third instruction), therefore, no write operation is performed in the memory. In addition, loading PCR into IPCR takes considerably less processing time as this is a normal register operation.

10 b) reg [PCR]: = mem [reg (OPER) + OPCODE) reg [PCR]: = mem (JEFF + OOD reg [PCR]: = mem (jFOQ) reg [PCR]: = 00001000 as shown by Figure 2 is written in memory location with address 7F00 15 the word 00001000, which is now being loaded into the register PCR The data from the latter figure suggest that the contents of the location descriptor would be of no importance, however this is not the case in the further description of the program will show that the location descriptor is actually used with an instruction with virtual opcode, and so it is even used in such a way that it already contains so much data, more than would be possible, for example, when using the instruction JUMP SUBROUTINE , where only a memory address can be recorded.

The eighth instruction, stored in the memory location with address 1000, reads: FA027FFF; LOADVAL R0, -1 ++ (¾¾ (Figure 3 (11), instr. 8).

This instruction involves the following operations: a) Reg QÖ: = - 1+ reg (Y)

Reg 0: = -1 + 2000

30 Reg C3: = 1FFF

b) Reg Cd]: = mem [reg 0)

Reg [cQ: = mem [jFFÈ]

Reg lef): = 00000000

The memory location with address 1FFF contains the value 00000000.

These operations in fact represent a "POP" operation applied to register R7, which performs the role of stack pointer.

The ninth instruction reads: FA11CFFF; LOADVAL R1, -1 + CiP0r) (figure 3 (11), instr. 9).

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This instruction involves the following operation:

Reg ff}; = nem Q * 1 + reg (iPCRjJ Reg U]: = mem (j-1 + 5]

Reg 03: = mem yyy 5 In the register R1 the content of a memory location with address 4 is loaded. But there is exactly the seventh instruction that has machine code 00040020. This operation is intended to retrieve the location descriptor of the virtual instruction for use in a further instruction.

10 The tenth instruction reads: FA1F1000; LOADVftL R1,9R1 (Figure 3 (11), Instr. 10).

In the location descriptor "F1000", the letter "F" indicates that this is an interpretation operation (Figure 5 (f)). This instruction thus means: "Load in register R1 the meaning of the location descriptor 15 of the instruction which is loaded in register R1". The instruction loaded in register R1 during the handling of the ninth instruction has as location descriptor "40020", which in turn means: the number (4) with value 20. Consequently, the word "00000020" is now written in register R1. . This now shows the importance of the location des-20 descriptor in an instruction with virtual opcode. This location descriptor stores information that is processed in the sequence of instructions initiated by a virtual opcode instruction.

The eleventh instruction reads: FD001000; DYADIC ADD R0, R1 (Figure 3 (III), Instr. 11).

The opcode "ED" indicates a DYADIC operation (Figure 4 (cj) between a first register R0 and a second register R1. The nature of the operation (value 0 bits 16 to 19) is an addition operation. This instruction which means: "Add the contents of register R0 and register R1 together and write the result in register R0 30 Reg [O]: = Reg Qfj + Reg fjj

Reg [Ö3: = 00000000 + 00000020 Reg OÖ: = 00000020 "

The twelfth instruction reads: FB037001; STORE R0, jR7) -H-1 (Figure 3 (III), Instr. 12).

35 This instruction implies the following operations: a) mem jlreg jjzf): = reg [cf) mem ijEEF}: = 20

So in memory location with address 1FFF the number 20 is written.

> ,, 'o PHN 11.228 18 b) reg DG: = reg [7] + 1 reg Cz) = = 1FEF + 1 reg (jG: = 2000

In fact, these operations represent a "PUSH" operation applied to register R7, which performs the role of stack.

The thirteenth instruction reads: FAB0G000; LQADVAL PCR, IPCR (Figure 3 (III), instr. 13).

This is the closing instruction that concludes the sequence of instructions initiated by a virtual opcode instruction. This instruction 10 contains the operation: "Load in the register PCR, the contents of the register IPCR". Since the state of the program counter was stored in the register IPCR, this means that the instruction following the instructions with virtual opcode, which has now been completed, will now be addressed.

The overall effect of the virtual instructions (seventh instruction 15 ADDSTACKƒ 20) is that the number 20 has been added to the top of the stack associated with the stack pointer (Register 7).

The fourteenth instruction, located at memory location with address 5, reads: 00018100; ADDSTACK $ 100 + [zerOR} (Figure 3 (III), Instr. 14).

20 The opcode "00" belongs to the class of virtual opcodes. Thus, the computer system performs the following operations: a) reg (iPCR): = reg (PCR] reg (iPCRi: = 6 b) reg (PCR]: = mem [reg [OPERj + OPCODE] 25 reg (PCR]: = mem [jFOO + OO) reg [PCR]: = 00001000

The fifteenth instruction, located at memory location with address 1000, reads: FA027FFF; LOADVAL R0, -1 ++ (¾¾ (Figure 3 (III), instr. 15).

3q This instruction involves the following operations:

a) reg 0Q: = - 1+ reg yy] reg ijJ: = - 1 + 2000 reg [7}: = 00001FFF

b) reg [oj: = mem [reg (~ 7 ~ f) 35 reg βΟ: = mem YyFFF) reg [o]: = 20

The presence of the value 20 in memory location with address 1FFF is the result of the handling of the twelfth instruction.

34 0 5 6 28 PHN 11.228 19

The sixteenth instruction reads: FA11CFFF; LOADVAL R1, -1 + £ EFCR] (Figure 3 (IV), Instr. 16).

This instruction involves the following operations:

Reg Q3: - item [y1 + reg (IFCR}) 5 Reg Ij]: = item Γ-1 + 6}

Reg LÖ: = mem CO Reg 03: = 00018100

Thus, again (analogous to the ninth instruction), the code of the instruction with virtual opcode is loaded into register R1. 10 The seventeenth instruction reads: FA1F1000; LQ & DVAL R1, ÖR1 (Figure 3 (IV), Instr. 17).

This instruction is analogous to the tenth instruction. The instruction loaded in register R1 has location descriptor "18100" which represents the operation: 15 Reg [Ο; - item [$ 100 + reg (ZEROR)]

Keg Q]: = mem [100 + 5)

Reg 03: = mem Qoo}

Reg 00: = FFFFFFE0

Thus, the word FFFFFFE0 is loaded in register R1. Here, too, 20 wser shows how in a computer system according to the invention the location descriptor is used in an instruction with virtual opcode.

The current instruction reads: FD001000; DYADIC ADD R0, R1 (Figure 3 (IV), Instr. 18).

25 This instruction involves the following operation:

Reg {0J: = Reg [Ö] + Reg 03 Reg 0) 3: = 00000020 + FFFEEFE0 Reg COj: = 00000000

The fact that the result of this operation is 0000000Q results here as 3Q in that the value 00000020 is loaded into the register CCR.

The nineteenth instruction reads: FB037001; STORE R0, (R7] -h-1 (Figure 3 (IV), instr. 19).

which means the following operation: a) mem [reg Cu): = Reg [O)

35 mem (jFFF}: = Reg QQ

item 0FFÊ1: = 00000000 b) Reg L7j: = Reg | j3 + 1 Reg [7j: = 1EEF + 1 **. *% · *. '_ Λ * \ * PHN 11.228 20

Reg [i]: = 00002000

The twentieth instruction reads: FAB0C000; LOADVAL PCR, IPCR (Figure 3 (IV), instr. 20).

which means the following operations: 5 Reg [PCR): = Reg flPCR}

Reg [Ρθή: = 00000006

So again the final instruction which concludes a series of instructions initiated by a virtual opcode.

The twenty-first instruction reads: 10 01018101; ORSTACK $ 101 + [ZERO ^ (Figure 3 (V), Instr. 21).

This is again an instruction with an opcode ("01") belonging to the class of virtual opcodes. The operations to be performed are thus: a) Reg QÏPCR): = reg (PCR)

Reg (ÏPCÖ: = 00000007 15 b) Reg QpCR): = item [reg jOPER) + OPCODE)

Reg [PCR]: = mem [7F00 + OÏ)

Reg (j? CRj: = item [7F0f)

Reg [PCR]: = 00001010 (see Figure 2)

It has now emerged from this instruction that in the case of a virtual opcode, the content of this opcode serves both to recognize a virtual opcode and to determine a memory address of a main instruction of a series of instruction words that indicate the meaning of the instruction with virtual determine opcode.

The twenty-second, instruction located at memory 25 location with address 1010 reads: FA027FEF; LOADVAL R0, -1 ++ (¾] (Figure 3 (IV), instr. 22).

This instruction includes the following operations: a) Reg yyD: = mem (j-1 + Reg CQ]

Reg Ld): = mem Q-1 + 2000} 30 Reg toll 5 = mem (JFFF}

Reg [cf]: = 00000000 (see instruction 19) b) Reg Cf): = -1 + Reg (7)

Reg [7): = 00001FFF

The twenty-third instruction reads: 35 FA11CFFF; LOADVAL R1, -1 + (ICPr) (Figure 3 (V), Instr. 23).

This instruction includes the following operation:

Reg Q]: = mem f1 + Reg (jPCiJ)

Reg Qf): = brake ljj-1 + ^ 8403628 V "* ΡΗΝ Π.228 21

Reg j "3: = 11) 0111? J Reg 0j: = 01018101

The twenty-fourth instruction reads: FA1F1000; LOADVSL R1 / 2R1 (figure 3 (V), instr, 24).

5 The location descriptor of the instruction in register 1 unbeaten contains "18101". As an operation this means:

Reg Q3: = nem [$ 101 + Reg (ZERORj]

Reg 03: “icem 0 ° O Reg 03: = F0000100 IQ The twenty-fifth instruction reads: FD06100Q; DYADIC OR R0, R1 (Figure 3 (V), Instr. 25).

In this instruction, the number "6" indicates a logical "OR" operation.

Reg [0]: = Reg [O] V Reg [Q Reg [q]: = F0000100 l5 The fact that now a negative number is entered in Reg 0 (F, 2-complement notation) means that the value 00000010 in the CCR register is loaded. This instruction and the previous one now show the possibility of having a variety of operations performed by means of virtual opcodes.

20 The twenty-sixth instruction reads: FB037001; STORE R0, [R7} -H-1 (Figure 3 (VI), Instr. 26).

This instruction involves the following operations: a) mem \ Reg \ j0: = Reg (0) man [| EFf3: = F00001Q0 25 b) Reg [73: - Reg (V) + 1

Reg tj3: = 1FEF + 1 Reg: * 2000

The twenty-seventh instruction reads: FAB0C000; LOADVAL PCR, IPCR (Figure 3 (VI), Instr. 27).

30 which means:

Reg [PCr3: = Reg (IPCR)

Reg [PCr3: = 7

The computer system will now handle the instructions located at memory location with address 7 and thus continue to process the program. The elaboration of this instruction will not be further discussed since this is of no importance for describing the invention. This instruction then also terminates the computer program described to illustrate the operation of a computer system according to the invention.

Mainly, two special aspects have emerged from the description of this computer program. These are: a) Handling an instruction with virtual opcode.

5 b) Treating the location descriptor at an Instruction with virtual opcode.

The fact that instructions with virtual opcodes can be used in a computer system according to the invention offers a wide range of possibilities to the system programmer. By using a 10 instruction with. virtual opcode can initiate a series of instructions to do a particular operation. This operation can be an addition (Instruction eleven) or a multiplication or any other operation. The system programmer can thus program the computer system by means of a self-chosen definition of virtual opcodes such that new "Instructions" are created. Given the efficient storage of PCR in IPCR and the fact that IPCR is used as an index register, such new instructions are handled efficiently. Furthermore it is possible by changing OPER (pointing to another table) to offer a different set of instructions per program, taking into account 2Q the language in which the program is written (a Pascal machine for Pascal, a Cobol machine for Cobol).

The location descriptor of a virtual opcode instruction contains information that is processed in a series of instructions. The processing of this information can be done in several ways and is entirely determined by the instructions from said series. The instructions in that series are usually instructions with a normal opcode. However, it is also possible to use instructions with virtual opcodes here. In that case, however, the contents of the IPCR register must first be stacked in memory.

3Q Figure 7 shows a second computer program by means of which a second embodiment of a method according to the invention will be explained. The second program can only be executed by a computer system provided with a register architecture as shown in Figure 6, because the execution of the second program requires the presence of a register VIR (B).

The execution of the second program is very similar to the one of the first program (Figure 2), therefore only the difference will be described just the first program. Since the register architecture shown in Figure 6 is different from the one in Figure 1, some instructions had to be adapted for this. For example, the register SPR is not designated as D but down as E, and the instruction at memory location 0 now becomes FAE47FFF, instead of FAD47FFF. Since these adjustments are easily recognizable, they will not be discussed further.

Figure 8 shows the result of the execution of the second computer program shown in Figure 7. In this exemplary embodiment, the registers R8 and R9 are each loaded with the value "00000000". The elaboration of the first 6 instructions shows no difference with the elaboration of the first computer program.

At the seventh instruction, which the instruction with virtual opcode: 00060020; ADDSIACK / 20 is 15, the following operations are now being performed.

a) reg QlPCR): = reg [PCR] b) reg [PCR): = item jreg | OPER \ + OPCODE] c) reg (VHÜ: = @ .r3

Application of these operations to this seventh instruction then gives: 20 a) reg QlPCR}: = 00000005 b) reg \ PCR): = item (7FOO + 00) reg [PCR): = 00001000 c) reg 171¾: = 00060020

The difference with the elaboration of the first program is now that at least the location descriptor part of the contents of the instruction register is loaded into the register VIR. That instruction register contained the virtual opcode instruction being processed.

The eighth instruction, stored in the memory location with address 1000, is: 3fl FAQ27FFF; LOADVAL. RQ, -1-H- {R7)

This instruction is identical to the eighth instruction from the first program.

The ninth instruction stored in memory location 1001 reads:

FA1FBQ00; LOADVAL R1,3 VIR

In the location descriptor "FB000", the letter "F" indicates that it is acting on an interpretation operation here (Figure 5 (f)). This instruction thus means: "Load in register R1 the meaning of the location descriptor c * Ü C 'i 3 PHN 11.228 24 of the instruction which is loaded in register B (VIR)".

The location descriptor 60020 is now in the register VIR. The evaluation of this location descriptor yields the number 20. Consequently, the word "00000020" is now written in the register R1. The result of this ninth instruction is therefore identical to the result of the tenth instruction from the first program as healed in figure 2. The difference between that first and second computer program and thus between the heath (figure 1, figure 6) is register architectures so that by using the register VIR an instruction can be saved (namely the instruction LQADVAL R1, -1 + Qipcr}). The result of this instruction (LQADVMj R1, -1 + [IPCR]) using the second register architecture (Figure 6) is already obtained when decoding an instruction with virtual opcode (reg VIR: = jl.RT)) .

By way of illustration, figure 8 shows the further elaboration of the second computer program as shown in figure 7. Given the analogy with the first computer program, the course of this elaboration may be assumed to be clear.

20 25 30

§ k Π 1 £ 9 Q

35

Claims (7)

A method of treating machine-coded instruction words by means of a data processor provided with a memory for storing said instruction words each containing an edit part and at least one operand descriptor part, which code parts belong to a finite set contained in a first and second classes are divided, the method comprising the following steps: (a) retrieving under the control of the data processor a first instruction word indicated by a program counter; (b) decoding the coding part from the first instruction word and examining to which of the classes the coding part of the first instruction word belongs; (c1) performing the instruction word operations given by the first instruction word with a code part belonging to the first class; 15 (c2) for instruction words with a code portion belonging to the second class, perform the following steps: (c2-1) storing the current program counter in a dedicated program counter register reserved therefor; (c2-2) generating, based on the code portion from the first instruction word, a memory address to which a second instruction word is located, the second instruction word being the initial instruction of a series of instruction words determining the meaning of the first instruction word; (c2-3) setting the current program counter to said memory address; (c2-4) treating said set of instructions; (c2-5) setting the current program counter to a value determined by the program counter contained in the additional program counter register; 30, characterized in that in said series of instruction words the operand descriptor part is loaded from the first instruction word into a first index register by at least one third instruction word. 2. A method for handling machine-coded instruction words by means of a data processor provided with a memory 35 for storing said instruction words, each containing a code part and at least one operand descriptor part, which code parts belong to a finite set which In a first and a second class is divided, which method comprises the following steps: «t <·· · '- *» -i _' i 'J · V * «r PHN 11.228 26 (a) retrieval under the control of the data processor from a a program counter designated first instruction word; (b) decoding the code part of the first instruction word and examining to which of the classes the code part of the first instruction word belongs; (c1) performing the instruction word operations provided by the first instruction word with a code portion belonging to the first class; (c2) for instruction words with a code portion belonging to the second class, perform the following steps: (c2-1) storing the current program counter in a dedicated program counter register; (c2-2) generating, based on the coding portion from the first Instruction word, a memory address to which a second instruction word is located, the second instruction word being the initial instruction of a series of instruction words determining the meaning of the first instruction word; (c2-3) setting the current program counter position to said memory address; 2o (c2-4) deal with said set of instructions; (c2-5) setting the current program counter reading to a value determined by the program counter contained in the additional program counter register; characterized in that for instruction words having a coding part belonging to the second class, at least the operand descriptor part of the first instruction word is loaded into a dedicated second index register before setting the program counter value at the memory address. 3. Method according to claim 1, characterized in that in the execution of the third instruction word the contents of the additional program counter register are used for localizing in the memory of the operand descriptor part from the first instruction word. Method according to claim 1, 2 or 3, characterized in that in said series of instruction words the operand descriptor part from the first instruction word is processed by at least one fourth instruction word. Method according to any one of the preceding claims, characterized in that the generation of the memory address for the second instruction word comprises the following sub-steps: 8 4 0 3 5 2 8 PHN 11.228 27 (1) form a tahel address from a memory table by adding a value which has been previously stored in an operation extension register reserved for this purpose to the addition part of the first instruction word; (2) addressing a memory word located at the formed table address; (3) retrieving the memory word at said table address, which memory word constitutes the memory address. 6. Data processor provided with a memory for storing 10 machine-coded instruction words, each containing a code part and at least one operand descriptor part, which code parts belong to a finite set divided into a first and a second class, which data processor further comprises a program counter register , an address generator and a coding decoder, which coding decoder is provided with first means for separately recognizing coding parts of the first and the second class and of second means for controlling a recognized coding word of the second class to generate a control signal which the data processor further includes a supplementary program counter register and transfer means, the transfer means having a first control input for receiving the control signal and further provided for transferring the contents of the program counter register under the control of a received control signal. Supplementary program counter register, and wherein the address generator is provided for generating, under control of the control signal, a memory address at which an initial instruction word of a series of instruction words for treating a descriptor part is located, characterized in that the data processor is provided with an operation -extension register which contains a second control input for receiving the control signal and has an output connected to the address generator. 7. Data processor according to claim 6, characterized in that the data processor further comprises a second index register containing a third control input for receiving the control signal and a data input connected to the memory for receiving the operand descriptor part of a instruction word under control of the control signal. $ ά Λ ~ · »O * '* - Si v .. v