CA1232075A - Method of handling machine-coded instruction words and data processor for carrying out the method - Google Patents
Method of handling machine-coded instruction words and data processor for carrying out the methodInfo
- Publication number
- CA1232075A CA1232075A CA000471845A CA471845A CA1232075A CA 1232075 A CA1232075 A CA 1232075A CA 000471845 A CA000471845 A CA 000471845A CA 471845 A CA471845 A CA 471845A CA 1232075 A CA1232075 A CA 1232075A
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- instruction
- register
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- opcode
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
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- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
ABSTRACT:
The invention relates to a method of processing machine-coded instruction words. The instruction words each time comprise an opcode part and a descriptor part. The collection of opcode parts is subdivided into two classes. A first class comprises normal opcode parts which are processed in known manner, while a second class com-prises virtual opcode parts which are processed in a particular manner.
This particular manner implies inter alia that the instantaneous program counter position is temporarily stored in a supplementary program counter register and that the memory address of an interpreting series of instructions is determined. The descriptor part of an instruction with virtual opcode is used in that series of instructions.
The descriptor part can either be accessed by using the supplementary program counter register as index register in an extra instruction or is automatically made available in a specialized register.
The invention relates to a method of processing machine-coded instruction words. The instruction words each time comprise an opcode part and a descriptor part. The collection of opcode parts is subdivided into two classes. A first class comprises normal opcode parts which are processed in known manner, while a second class com-prises virtual opcode parts which are processed in a particular manner.
This particular manner implies inter alia that the instantaneous program counter position is temporarily stored in a supplementary program counter register and that the memory address of an interpreting series of instructions is determined. The descriptor part of an instruction with virtual opcode is used in that series of instructions.
The descriptor part can either be accessed by using the supplementary program counter register as index register in an extra instruction or is automatically made available in a specialized register.
Description
PUN 10.9()9C 1 3 5 17.12.1984 Method of handling machine-coded instruction words and data processor for carrying out the method.
The invention relates to a method of handling machine-coded instruction words by means of a data processor provided with a mQ~ory for storing the said instruction words, which each comprise an opaqued part and at least one operand descriptor part, which opaqued parts belong to a finite collection which is subdivided into a first and a second class, this method comprising the following steps:
(a) fetching a first instruction word indicated by a program counter position under the control of the data processor;
(b) decoding the opaqued part from the first instruction word and lo determining, to which of the classes the opaqued part of the first instruction word belongs;
(c1) carrying out the operations given by the first instruction word for instruction words having an opaqued part belonging to the first class;
(c2) carrying out the following steps for instruction words having an opaqued part belonging to the second class:
(c2-1) storing the instantaneous program counter position in a supplementary program counter register intended thereto;
(c2-2) generating on the basis of the opaqued part from the first instruction word a memory address at which a second instruction word is located, this second instruction word being the beginning instruction of a series of instruction words, which determine the meaning of the first instruction word;
(c2-3) setting the instantaneous program gaunter position to the said memory address;
(c2-4) handling the said series of instructions;
(c2-5) setting the instantaneous program counter position to a value determined by the program counter position present in the supplementary program counter register.
Such a method is known from the article "Instruction set extension" by AL Brains, AL Hoffman, GROW. Mitchell and FOG. Solutes, published in IBM Technical Disclosure Bulletin, Volume 18, No. 7, PUN 10.909C 2 17.12.1984 December 1975, p. 2250-2252. In the known method, the machine-coded instruction words are the result of translation procedures which are applied to a program text offered by a programmer. The program text is written in a known computer language, such as, for example, PASCAL
5 or Frown. The compiler and the assembler of the data processor (also designated as computer system) translate the program text into a set of machine-coded instruction words, which are then stored in the memory during handling of the program text. An instruction word has, for example, a width of 32 bits. For example, 8 bits thereof are intended 10 for the opaqued parts and 20 bits for the operand descriptor part. With an opaqued part having a width of 8 bits, a collection of opcodes come proses at most I =) 256 different opcodes. In the known method, this collection is subdivided into two classes, i.e. the valid (first) class and the invalid (second) class of opcodes. The contents of the 15 opaqued part are determinative of the kind of the operation(s) to be carried out for handling the instnlction. For example, an opccde may indicate a register charge operation or a jump to a subroutine. The decoding step has for its object to convert the opaqued part into control information for the computer system. The order in which the instruction 20 words are fetched from the computer and are handled by the data processor is indicated by the program counter position.
In the known method, the valid opaqued parts from the said collection have a fixed meaning, which is identified during decoding.
An opaqued part with a fixed meaning is carried out after decoding in 25 known manner. Depending upon the capacity of the computer system, the collection of opcodes comprises a large or a small nunnery of different elements. The system programmer has to work with the given collection of opcodes and the fixed meaning imparted thereto by the computer system during decoding. The known method provides a solution for 30 handling instruction words with an invalid opaqued (second class). When an invalid opaqued is decoded, the instantaneous program counter position is stored in a supplementary program counter register and a Ir~rory address is formed from the first instruction word on the basis of the opaqued part. This memory address is formed inter aria by making in a 35 shift register the most significant bits zero and ho using the opaqued for the least significant bits of the priory address. At that Emory address a second instruction word is located, which is the beginning instruction of a series of instruction words which determine the meaning
The invention relates to a method of handling machine-coded instruction words by means of a data processor provided with a mQ~ory for storing the said instruction words, which each comprise an opaqued part and at least one operand descriptor part, which opaqued parts belong to a finite collection which is subdivided into a first and a second class, this method comprising the following steps:
(a) fetching a first instruction word indicated by a program counter position under the control of the data processor;
(b) decoding the opaqued part from the first instruction word and lo determining, to which of the classes the opaqued part of the first instruction word belongs;
(c1) carrying out the operations given by the first instruction word for instruction words having an opaqued part belonging to the first class;
(c2) carrying out the following steps for instruction words having an opaqued part belonging to the second class:
(c2-1) storing the instantaneous program counter position in a supplementary program counter register intended thereto;
(c2-2) generating on the basis of the opaqued part from the first instruction word a memory address at which a second instruction word is located, this second instruction word being the beginning instruction of a series of instruction words, which determine the meaning of the first instruction word;
(c2-3) setting the instantaneous program gaunter position to the said memory address;
(c2-4) handling the said series of instructions;
(c2-5) setting the instantaneous program counter position to a value determined by the program counter position present in the supplementary program counter register.
Such a method is known from the article "Instruction set extension" by AL Brains, AL Hoffman, GROW. Mitchell and FOG. Solutes, published in IBM Technical Disclosure Bulletin, Volume 18, No. 7, PUN 10.909C 2 17.12.1984 December 1975, p. 2250-2252. In the known method, the machine-coded instruction words are the result of translation procedures which are applied to a program text offered by a programmer. The program text is written in a known computer language, such as, for example, PASCAL
5 or Frown. The compiler and the assembler of the data processor (also designated as computer system) translate the program text into a set of machine-coded instruction words, which are then stored in the memory during handling of the program text. An instruction word has, for example, a width of 32 bits. For example, 8 bits thereof are intended 10 for the opaqued parts and 20 bits for the operand descriptor part. With an opaqued part having a width of 8 bits, a collection of opcodes come proses at most I =) 256 different opcodes. In the known method, this collection is subdivided into two classes, i.e. the valid (first) class and the invalid (second) class of opcodes. The contents of the 15 opaqued part are determinative of the kind of the operation(s) to be carried out for handling the instnlction. For example, an opccde may indicate a register charge operation or a jump to a subroutine. The decoding step has for its object to convert the opaqued part into control information for the computer system. The order in which the instruction 20 words are fetched from the computer and are handled by the data processor is indicated by the program counter position.
In the known method, the valid opaqued parts from the said collection have a fixed meaning, which is identified during decoding.
An opaqued part with a fixed meaning is carried out after decoding in 25 known manner. Depending upon the capacity of the computer system, the collection of opcodes comprises a large or a small nunnery of different elements. The system programmer has to work with the given collection of opcodes and the fixed meaning imparted thereto by the computer system during decoding. The known method provides a solution for 30 handling instruction words with an invalid opaqued (second class). When an invalid opaqued is decoded, the instantaneous program counter position is stored in a supplementary program counter register and a Ir~rory address is formed from the first instruction word on the basis of the opaqued part. This memory address is formed inter aria by making in a 35 shift register the most significant bits zero and ho using the opaqued for the least significant bits of the priory address. At that Emory address a second instruction word is located, which is the beginning instruction of a series of instruction words which determine the meaning
2~75 PUN. 10.909C 3 of the first instruction word. Thus, an instruction word with an invalid opaqued part is translated into a practicable instruction.
A disadvantage of the known method is that with instruction words having an opoode part which belongs to the second class (invalid opaqued), during the process of translating into a practicable in-struction and the step of carrying it out, the operand descriptor part of the relevant instruction word is not taken into account. As a result, the operand descriptor part of such an instruction word is used inefficiently and this also holds for the computer system.
The invention has for its object to provide a method of handling machine-coded instruction words in which the operand descriptor part of the instruction word with an opaqued part belonging to the second class is available for encoding operand descriptors and in which the system programmer is thus given the freedom to choose the meaning of the opaqued parts of the second class. me invention further has for its object to provide a method in which a higher efficiency is also obtained for high level programming language.
A method according to the invention is for this purpose characterized in that with the said series of instruction words the operand descriptor part from the first instruction word is loaded into a first register by at least one third instruction word. me step of loading the operand descriptor part into the first register permits processing of the operand descriptor part and consequently also ensures that the operand descriptors are available for encoding. The system programmer now has the possibility to store information to be processed in the descriptor part, which information is then processed by the series of instruction words.
In an alternative embod~nt, a method according to the invention is characterized in that for instruction words having an opaqued part belonging to the second class at least the operand descriptor part of the first instruction word is loaded into a second register intended thereto before the program counter position is set to the memory address. When the operand descriptor is loaded into the second register, program instructions in said series of instruction words can be saved.
A first preferred embodiment of the method according to the invention is characterized in that, when the third instruction word is PUN. Luke 4 1~3~
carried out, the contents of the supplementary program counter register are used to locate in the memory the operand descriptor part from the first instruction word. Sue to the fact -that the instantaneous program counter position is stored in the supplementary program counter register, it is thus possible to locate rapidly and simply at which area in the memory the operand descriptor of the first instruction word is situated.
In fact, the operand descriptor is situated in the operand descriptor part of that first instruction word which was indicated by the program counter position during the fetching step under (a) of the method according to the invention.
A second preferred embodiment of a method according to the invention is characterized in that with the said series of instruction words, the operand descriptor part from the first instruction word is processed by at least one fourth instruction word. The operand descriptor of the first instruction word stored in a register is processed by means of the fourth instruction word. The descriptor part of an instruction word having an opaqued part belonging to the second class is thus used for encoding operand descriptors.
A further preferred embodiment of a method according to the invention is characterized in that the step of generating the memory address for the second instruction word comprises the following sub steps:
(1) forming a table address from a memory table by adding to the opo~de part of the first instruction word a value which is previously stored in an operation extension register intended thereto;
(2) addressing the memory word located at the table address formed;
A disadvantage of the known method is that with instruction words having an opoode part which belongs to the second class (invalid opaqued), during the process of translating into a practicable in-struction and the step of carrying it out, the operand descriptor part of the relevant instruction word is not taken into account. As a result, the operand descriptor part of such an instruction word is used inefficiently and this also holds for the computer system.
The invention has for its object to provide a method of handling machine-coded instruction words in which the operand descriptor part of the instruction word with an opaqued part belonging to the second class is available for encoding operand descriptors and in which the system programmer is thus given the freedom to choose the meaning of the opaqued parts of the second class. me invention further has for its object to provide a method in which a higher efficiency is also obtained for high level programming language.
A method according to the invention is for this purpose characterized in that with the said series of instruction words the operand descriptor part from the first instruction word is loaded into a first register by at least one third instruction word. me step of loading the operand descriptor part into the first register permits processing of the operand descriptor part and consequently also ensures that the operand descriptors are available for encoding. The system programmer now has the possibility to store information to be processed in the descriptor part, which information is then processed by the series of instruction words.
In an alternative embod~nt, a method according to the invention is characterized in that for instruction words having an opaqued part belonging to the second class at least the operand descriptor part of the first instruction word is loaded into a second register intended thereto before the program counter position is set to the memory address. When the operand descriptor is loaded into the second register, program instructions in said series of instruction words can be saved.
A first preferred embodiment of the method according to the invention is characterized in that, when the third instruction word is PUN. Luke 4 1~3~
carried out, the contents of the supplementary program counter register are used to locate in the memory the operand descriptor part from the first instruction word. Sue to the fact -that the instantaneous program counter position is stored in the supplementary program counter register, it is thus possible to locate rapidly and simply at which area in the memory the operand descriptor of the first instruction word is situated.
In fact, the operand descriptor is situated in the operand descriptor part of that first instruction word which was indicated by the program counter position during the fetching step under (a) of the method according to the invention.
A second preferred embodiment of a method according to the invention is characterized in that with the said series of instruction words, the operand descriptor part from the first instruction word is processed by at least one fourth instruction word. The operand descriptor of the first instruction word stored in a register is processed by means of the fourth instruction word. The descriptor part of an instruction word having an opaqued part belonging to the second class is thus used for encoding operand descriptors.
A further preferred embodiment of a method according to the invention is characterized in that the step of generating the memory address for the second instruction word comprises the following sub steps:
(1) forming a table address from a memory table by adding to the opo~de part of the first instruction word a value which is previously stored in an operation extension register intended thereto;
(2) addressing the memory word located at the table address formed;
(3) fetching the memory word at the said table address, which memory word constitutes the memory address.
The use of a memory table offers the possibility of making an inventory of specialized instruction collections, by which instruction words are processed which have an opoode part belonging to the second class.
The invention further relates to a data processor provided with a memory for storing machine-coded instruction words which each comprise an opaqued part and a descriptor part, which opaqued parts belong to a finite collection which is subdivided into a first and a second class, this data processor further comprising a program counter register, an address generator and an opaqued decoder, which opaqued decoder is provided with first means for separately identifying opaqued parts of the first and the suckled class and with second means for generating a HO Luke 5 I
control signal under the control of aft identified opaqued word of he second class, this data processor further comprising a supplementary program counter register and transmission means, which transmission means have a first control input for receiving the control signal and are further provided with means for transmitting the contents of the program counter register to the supplementary program counter register under the control of a received control signal, while the address generator is adapted to generate under the control of the control signal a memory address at which a beginning instruction word of a series of instruction words for processing a descriptor par-t is located.
Such a data processor is also known from the aforementioned article "Instruction set extension".
A data processor according to the invention is characterized in that the data processor is provided with an operation extension register which has a second control input for receiving the control signal and an output which is connected to the address generator. As a result, the address generator can be realized in a simple manner when the operation extension register comprises a collection of addresses or address parts.
It is favorable that the data processor is further provided with a second register which has a -third control input for receiving the control signal and a-data input connected to the memory for receiving the operand descriptor part of an instruction word under the control of the control signal.
Thus, moorer program instructions can be saved.
The invention will be described more fully with reference to the drawing, in which:
Figure 1 shows a first embodiment of a register architecture of a computer system according to the invention, Figure lo shows diagrammatically the method according to the invention with reference to a flowchart, Figure 2 shows a first computer program, with reference to which a firs-t embodiment of the method according to the invention is illustrated, Figure 3 (I to Al indusive) shows the result of execution of he computer program of Figure 2, Figure 4 (a to f inclusive) shows a few different opcodes and -their associated instruction word classification, and PUN. Luke 6 ~3~7~
Figure 5 (a to f inclusive) shows a few different descriptor parts within an instruction word, Figure 6 shows a second embodiment of a register architecture of a computer system according to the invention Figure 7 shows a second computer program, with reference to which a second embodiment of the method according to the invention is illustrated, Figure 8 (I to V inclusive) shows the result of a handling of the computer program of Figure 7.
A data processing system or a computer which has to process an instruction will do so by handling a program which is suitable for pro yessing this instruction. This program is written in a kin programming language, such as, for example, PASCAL, FORTRAN or BASIC.
These programming languages are users languages, however, which are first translated by the computer into machine-coded instructions in order to handle the program. this translation of users' language into machine-coded instructions mostly takes place in two steps. A first step comprises translating users' language into "Assembly language"
and a second step comprises translating "Assembly language" into "machine instructions". The first step is handled by a "compiler" and the second step is handled by an l'assembler'l. The compiler and the assembler are both translation programs which form part of the computer system. Wren forming the compiler and the assembler, the system programmer has taken the architecture of the computer (CA =
computer architecture, i.e. the appearance of the machine from the viewpoint of the system programmer) into account.
In computer architecture, inter aria a distinction is made between two types of architecture, i e. HULL (High Level Language and RISK (Red owed Instruction Set Computers) architecture, HULL architecture mainly implies that the computer hardware is provided with an instruction set which is suitable for professing high level language. Thus, the gap between users' language and machine instructions becomes smaller. RISK
architecture mainly implies that the instructions of the machine are so simple that the hardware can accomplish maximum performances. However, in the case of RISK architecture, the translation of a users' program is much more difficult.
The advantages of these two said types of computer architecture are now combined in a data processing system according to the invention.
PUN 10.909C 7 ~32~7~ 17.12.1984 Such a data processing system in fact comprises a simple machine, whose instruction set is made extensible in order to be able to handle efficiently operations of the HULL type.
A computer system according to the invention comprises a central processing unit (CPU) with, for example, a register architecture. Figure 1 shows a first embodiment of a register arch- -.
lecture of a computer system according to the invention. The registers Row to R7 inclusive, just like the registers ZERO (8), O'ER (9), PER (Program Counter Register) (B), SPY (Stack Pointer Register) (D), CUR (Condition Code Register) (E) end SEX (Sign Extend Register) (F), are the conventional known index registers of a computer with a conventional register architecture. The registers IPCR (Interpreter Program Counter Register and O'ER (Operation Extend Register) (A) constitute an addition to the CPU, with which a register architecture is extended for use of the invention; it should be noted, however, that the register O'ER is optional. In the simplest construction, the register IPCR is sufficient. The use of the register IPCR by the computer system during the handling of a program is controlled by the OPAQUED PART of an instruction word to be handled or briefly designated as the OPAQUED (operation code).
Figure 6 shows a second embodiment of a register architecture of a computer system according to the invention. The registers Row to R7 inclusive, just like the registers O'ER and IPCR, are identical to the same registers of the first embodiment shown in Figure 1. The registers (8) and (9) are now designated by R8 and Rug. The registers PER (D), SPY (E) and CUR (F) fulfill the same fiction as the same registers of the first embodiment, but now have a different order in the system. New for the second em oddment is the register VlR (B), whose meaning will be explained hereinafter.
In this computer system, the OPCODES are subdivided into two classes, i.e. a first class, which comprises "normal" opcodes, and a second class, which comprises "virtual" opcodes. The opaqued decoder of the computer system is implemented so that it recognizes by the bit pattern of the opcodes to which class the opaqued belongs. For example, all the opcodes, which have as most significant bits (MOB) the value "0", can be recognized as "Noreen" opcodes, while all the opcodes, which have as MOB the value "1" can be recognized as "virtual" opcodes. As a result, a division is obtained, in which each class comprises an PUN 10.909C 8 17.12.1984 equal number of opcodes. However, it should key noted that any other division is also possible. An accurately defined implementation of the opaqued is then each time associated with a given division. It will ye clear that each class has to comprise at least one okayed.
The manner in which instructions with normal or with virtual opaqued are handled by a computer system according to the invention is illustrated diagrammatically with reference to the flowchart of Figure pa. After reading (50) an instruction word, it is determined (51) whether the opaqued belongs to the class of the virtual opcodes or to the class of the normal opcodes.
In the case in which the opaqued decoder has decoded an opaqued belonging to the class of normal opcodes (N), the associated in-struction is handled in known manner (52). However, in the case in which the opaqued decoder has decoded an opaqued belonging to the class of virtual opcodes (V), irrespective of the contents of the associated instruction, each time the operations stated below are carried out:
Rug riper = Rug ~PCR3 (53) Rug PER : = mom Greg OPERA + opcodel (54).
In this case, the operation Rug ~IPCRJ : = Rug Purl means that the contents of the register PER is rewritten into the register IPCR (: =
represents in programming language "becomes"); in other words: the address of the instruction indicated by the program counter (instantaneous program counter position) is loaded into the register IPCR. The operation Rug ~PCRJ : = mom Greg OPERA + opaqued means that the memory word (in this case an address word), which is stored at the memory location with the address Rug LOPER + opaqued, is loaded into the register PER. The address Rug LOPER + opaqued is composed by adding the contents of the register O'ER to the value as given in the opaqued part of the instruction word. This operation Rug PER : =
mom Greg row + opaqued consequently means that a new address for the program counter is loaded into the register PER.
It is also possible to generate this new address by other operations than by the operation Rug rPCR~ : = mom Leg OPERA + opaqued O Possible other operations are, for example:
a) Rug LPCR3 : = Rug loper + opaqued.
In this case the new address is directly determined without a reading operation from the memory being effected.
b) Rug PER : = opaqued + fixed address.
PUN 10.909C 9 I 17.12.1984 This is an operation which is used when, as already stated, the register O'ER is not used. The new address is composed in this case by adding a fixed address to the opaqued part of the instruction word.
c) Rug R] : = mom opaqued + fixed address .
Also in this operation the register O'ER is not used. This operation on the contrary comprises, however, a memory reading operation. Now a first instruction of a series of instructions, which interpret the meaning of the instruction word with virtual opaqued (55), is present at this new address for the program counter. This series of instructions lo is always terminated by a last instruction from the program which immediately follows the instruction with virtual opaqued which has ensured that the said series is processed. Such a lust instruction is, for example, of the form Rug PER : = Rug ~IPCR~ (56).
In this case, the program counter position is then again set to the value which it had at the beginning of the execution of the instruction with virtual opaqued part.
The useful effect of a virtual opaqued is that with each virtual opaqued a piece of code is executed. In this piece of code (the "Interpretator" of the virtual opaqued) it is possible to refer in an efficient manner to the argument descriptor(s) of the virtual opaqued if IPCR is used as index register.
When the computer system now has a register architecture as shown in Figure 6, during decoding of an opaqued belonging to the class of virtual opcodes, besides the operations (53) and (54) a further operation (150) is carried out, i.e.:
fog VOYEUR : IRE
The contents of at least the location descriptor part of the instruction register LOWRY of the computer system are transferred to the register VqR.
An instruction with a virtual opaqued is mainly distinguished from an instruction JUMP SUBROUTINE, which has a normal opaqued, in that during the handling of the subroutine the program counter position is stored temporarily in the memory. On the one hand, the memory writing operation necessary to this end requires an additional amount of handling time, while on the other hand it is thus not possible to use (without an additional amount of handling time) the old program counter position as index register for reading argument desecrators.
PUN 10.909C 10 1~32~S 17.12.1984 Figure 2 shows a first computer program, with reference to which a first embodiment of the operation of a computer system according to the invention will be explained more fully. The program is given only by way of example. It will be appreciated that a computer system according to the invention is not limited to the execution of solely programs of this kind.
In Figure 2 five columns can be distinguished. The first column indicates the memory addresses of the instructions. The second column states the instructions written in machine code (hexadecimal lo notation). The third and fourth columns indicate instructions written in "Assembly language", while the fifth column comprises a comment on the instruction.
Before Figure 2 will be considered more fully, with reference to Figures 4 and 5 first a few general aspects of the instructions will be described in order to clarify the reading of the program and its processing. The Figures 4 (a to f) show opcodes and their associated instruction word classification. An instruction as written in machine code (Figure 4 or second column Figure 2) comprises 32 ( 4 x 8) bits.
The bits 31 to 24 always comprise the opaqued. Since the opaqued part comprises 8 bits, 28 = 256 different opcodes are possible. In the example of Figure 2, the opcodes 00 to F8 belong to the class of virtual opcodes and the opcodes F9 to OF belong to the class of the normal opcodes. me classification of the remaining bits (0 to 23) depends upon the kind and the class to which the opaqued belongs.
Figure I shows the pattern of an instruction which has as opaqued one of the normal opcodes LOAD ADDRESS (F9), LOAD VALUE (FAX) or STORE (FOB). With this instruction, the bits 20 to 23 comprise the number of the register (RUN), to which the operation given by the opaqued relates, while the bits 0 to 19 comprise the location descriptor (LCDSC). The contents of this location descriptor will be discussed more fully hereinafter.
Figure I shows a pattern of an instruction, which has as opaqued the normal opaqued MONADIC (FC). With this instruction, the bits 20 to 23 comprise the number of the register (RUN), to which the operation given by the opaqued relates, while the bits 16 to 19 indicate the kind of the MONADIC operation PI (increment, decrement, etc.).
The remaining bits do not comprise information essential to this in-mention.
~23~
PUN 10.909C 11 17.12.1984 Figure I shows the alert of dun instruction which has as opaqued the normal opaqued DYADIC (FC). With this instruction, the bits 20 to 23 comprise the number of the first register (RUN) and the bits 12 to 15 comprise the number of the second register (RUT) to which the operation given by the opaqued relates. The bits 16 to 19 represent the kind of the DYADIC operation (DPC) (addition, subtraction, logic AND, etc.). The remaining bits do not comprise information essential to this invention.
Figure I and Figure I, respectively, show the pattern of an instruction, which has as opaqued the normal opaqued JUMP
SUBROUTINE (FE) and JUMP CONDITIONAL (OF), wherein for the instruction with opaqued OF the condition (CUD) is given by the bits 20 to 23. The bits 0 to 19 each time comprise the location descriptor (LCDSC). When now the computer system decodes the opaqued "FE", the following operations are carried out:
mom Greg SPIRO : = Rug PER
Rug SPIRO : = Rug SPIRO + 1 Rug LPCR] : = effa (LCDSC), where "effa" represents "effective address".
When decoding the opaqued "OF", in the case in which the condition (~) is satisfied, the following operation is carried out:
Rug LPCR~ = effa (LCDSC).
(The program counter position Greg ~PCR3 ) is not held because with a Jump Conditional no return takes place.
Figure I shows the pattern of an instruction with a virtual opaqued (00; ... ; F8). The bits 0 to 23 are used herein dependence upon the interpretation routine. This will be discussed in a further part of the description.
The location descriptor describes the address associated with the instruction operand. The computer system is provided with hardwrdre means to interpret this location descriptor. Figure 5 shows a number of examples of location descriptor parts within an instruction word. For each location descriptor the bits 16 to 19 each time indicate the kind of the descriptor, which will be described below fox each of the parts (a) to (f) of Figure 5.
(1) In Figure I the word "0000" represents a register operation with respect to the register surrounded by the bits 12 to 15. The contents of the bits 0 to 11 are not essential to the description YIN. 10.909C 12 of the invention.
by In Figure I, the word "0001" represents a normal index operation.
The resulting address thereof is a + Rug no a representing the number given by the bits 0 to 11 and n representing the register number given by the bits 12 -to 15.
(c) In Figure I the word 'Lowe" represents an index operation preceded by an adaptation operation (preadjust index).
Such an operation is carried out in two steps:
me address is given by a + Rug [n]
and also Rug [no : = a + Rug [no (a and n have the same meaning as stated above).
(d) In Figure I the word "0011" represents an index operation followed by an adaptation operation (post-adjust index). Such an operation is again carried out in two steps:
The address given by Rug no : = and also Rug to = a + Rug Lo (with analogous meaning for a and n).
With an index operation accompanied by an adaptation operation, therefore both a value and an address are each time determined. The use of the address is determined by the opaqued part.
(e) In Figure I the word "0100" represents a number whose value is given by the bits 0 to 15. ("Immediate").
(f) In Figure I the word "1111" represents an interpretation operation. The contents of the register, whose number is given by the bits 12 to 15 are considered as location descriptor. The contents of the bits 0 to 11 are not essential to the description of the invention.
With reference to the data from Figures 4 and 5, the computer program illustrated in Figure 2 will now be described. The result of the elaboration of this program is illustrated in Figure 3 (I to VI). Here-after, wherever an instruction is explained, there will be an accompany in reference in parentheses indicating the place in Figure 3 where the result of the instruction is shown.
The first instruction of the computer program is located at ~3~5 `
PUN 10.909C 13 17.12.1984 the IT Emory location with the address 0 and is:
FAD47FFF; LOADVAL SPR,?~L$7E~'F (Fig. 3 I) incitory. 1).
The opaqued "FAX" indicates that an instruction with normal opaqued (Figure 4 (a)) is concerned here, i.e. the instruction "LOAD VALUE".
5 The register number "D" indicates that the register to be used is the register SPY (Figure 1). The location descriptor comprises the number "47FFF". In this number the digit 4 indicates that a location descriptor of the type shown in Figure I is concerned, i.e. a number (Immediate), in this case the number 7FFF. This instruction 10 consequently means- "load (FAX) into the Stack Pointer Register (SPY) (D), the number (4) having a value I ". The number 1 is now stored in the program counter register (PER), which means that the next instruction is located at wrier location 1. It should be noted that in this endowment the register ZERO is loaded each time with the value 15 "00000000" and the register CANER is each time loaded with the value "00000001". The constant values 0 and 1 are frequently used. Therefore, it is efficacious to have these constant values available in a register so that they can be read by simple register operations.
At the memory location 1, the second instruction of the 20 computer program is located. This second instruction is:
FIFE; LOADVAL OPER,3~$7F00 (Fig. 3 (I), incitory. 2).
Analogously to the first instruction, this is an instruction with normal Gpcode "LOADVAL". The register number "A" indicates the register O'ER (Figure 1). This instruction therefore means: "Ioadinto the 25 Operation-Extend Register (O'ER) the number having a value 7F00".
Meanwhile, the number 2 has been loaded into the register PER.
The third instruction is:
FOE; JAR $400+EZERoR1 (Fig. 3 (I), incitory. 3).
The opaqued "FE" indicates the instruction with normal opaqued JO
30 SUBROUTINE" (Figure 4 (d)). The location descriptor comprises the number "18400"; the digit "1" therein indicates that a normal index operation is concerned (Figure I). The digit "8" indicates the register ZERO and the number "400" indicates the displacelrent. When this instruction is performed, there is obtained:
35 a) mom Leg LSPR3]: = fog LPCR3 mom r7~ : = 00000003.
This means that the number 3 is written at the memory location with the address or This implies that the address of the next instruction PUN 10.909C 14 17.12.1984 (memory address 3) is held at the memory location 7FFF.
b) Rug SPURGE : = Rug LSPR~ + 1 Rug SPIRO : = 00007FFF + 1 = 00008000.
c) Rug PER : = effa (LCDSC) effa (LCDSC) represents the effective content of the location descriptor, which is given for this example by 400 + ZERO .
However, since 00000000 is present in the register ZERO, effa (LCDSC) is 00000400 Rug tPCR3 = 00000900.
This means that the program counter now indicates the memory location with the address 400. Consequently, a jump has been made to the memory location with the address 400.
The fourth instruction located at the storage location with the address 400 is:
PHOEBE; LOADVAL R0,~PCR3++1 I ok I (Fig. 3 (I), incitory. 4).
The register number of this instruction with normal opaqued LOAD VALUE
is "0". In the location descriptor having a value "3B001", the digit 3 indicates an index operation followed by an adaptation operation (Figure I). The letter B indicates that the adaptation relates to the register PER (Figure 1) and the number "001" indicates the amount of the adaptation. This instruction consequently means:
Rug OX = mom Greg ~PCRJ3 Rug row = mom Eye Rug I : = I
Load into the register R0 the value which is stored at the memory address which is given by the contents of register PER and then in creases the contents of register PER by the number "001". The value (400 + 1 =) 402 is stored in the register PER. The value 7FFFFFFF, which is now stored in the register R0, is present at the address 401.
The adaptation operation then results in:
Rug R1 : = Rug RJ + 1 Rug RJ : = 401 + 1 Rug I : = 402.
The fifth instruction, which is located at the memory location with 402 is:
FAB2DFFF; LOADVAL PCR,-1++~SPR3 (fig. 3 (I), incitory. 5).
The register number "B" indicates the register PER. In the location PUN 10.909C 15 17.12.1984 descriptor having a value ED the digit 2 indicates an index operation preceded by an adaptation operation (Figure I); the letter D indicates the register SPY and the hexadecinEl number I
(2-complement notation) represents "-1", which indicates the quantity of the adaptation.
Rug SPIRO : = Rug SPIRO -1 Rug SPIRO : = 00008000 -1 Rug Pi : = 00007 Rug rPCR~ : = mom leg SPIRO
Rug I : = mom I
Rug PER : = 00000003 In fact, as indicated with the third instruction, the value "3" is loaded at the memory location with the address I The operation of reading from the memory and loading 00000003 into the register PER
means that the subroutine is terminated and that the ordinary program is now resumed again, i.e. with the instruction loaded at the address 3 of the memory.
The sixth instruction then is:
FOE; LOADVAL R7,~$2000 (Fig. 3 (II), incitory. 6).
This instruction implies: "Load into the reviser R7 the number having a value 2000".
The seventh instruction is:
00040020; ADDSTACX $20 (fig. 3 (II), incitory. 7).
The opaqued "00" indicates that an opaqued from the class of the virtual opcodes (00~ {00, ..., F8~) is concerned here. The decoding device of the computer system decodes this virtual opaqued and consequently the system will carry out the following operations:
a) Rug LIPCR~ = Rug PER
b) Rug PER : = mom Greg opera + OKAYED.
The use of these operations in this seventh instruction then results in:
a) Rug ~IPCR~ : = Rug rPCR~
Rug LIPCR~ : = 00000005.
The contents of the register PER (instantaneous program counter position) are consequently loaded into the register IPCR.
Therefore, in contrast with a JUMP SUBROUTINE instruction (third instruction), no writing operation is carried out here in the memory.
Moreover, the operation of loading from PER into IPCR requires a considerably staller amount of processing time because this is an PUN 10.909C 16 17.12.1984 ordinary register operation.
b) Rug PER : = mom Greg OPERA + OPCODEJ
Rug rPCR~ = mom ~7F00 + 00 Rug PER : = mom l7F0 Rug PER : = 00001000 In fact, as appears from Figure 2, the word 00001000 is written at the Emory location with the address 7F00, which word is now loaded into the register PER. The data from the last-mentioned Figure suggest that the contents of the location descriptor should be of no importance.
lo However, this is not the case. In the further description of the program it will appear that the location descriptor is used indeed with an instruction with virtual opaqued, even in a manner such that it comprises already a number of data which exceeds the number of data that would be possible, for example, with the use of the instruction JUMP SUBROUTINE, in which event only a memory address can be recorded.
The eighth instruction stored at the Myra location with the address 1000 is:
FOE; LOADVAL R0,-1++ ~R7~ (Fig. 3 (II), incitory. 8).
This instruction implies the following operations:
a) Rug Lo = -1 + fog 73 Rug I l + 2000 Rug I I
b) Rug to : = mom Greg ~73 3 Rug I : = mom ~lFFF3 Rug Lo =
The value 00000000 is present at the memory location with the address 1FFF.
These operations in fact represent a "POP" operation applied to the register R7, which plays the part of a stack pointer.
The ninth instruction:
FAllCFFF; LOADVAL R1,-1+ LIPCR] (Fig. 3 (II), incitory. 9).
This instruction implies the following operation:
Rug I : = mom r-1+ Rug LIPCR~
Rug ~13 = mom Lo I
Rug [1¦ : = mom I
Consequently, the contents of the memory location with the address 4 is loaded into the register R1. However, at this very location is present the seventh instruction, which has as machine code 00040020.
~32~3~5 PUN Luke 17 17.12.1984 This operation is intended to read the location descriptor of the virtual instruction in order to utilize it in a further instruction.
The tenth instruction is:
FIFE; LARVAL R1,~R1 (Fig. 3 (II), incitory. 10).
In the location descriptor "F1000", the letter "F" indicates that here an interpretation operation is concerned (Figure 5 (f!). This in-struction therefore means: "Load into register R1 the meaning of the location descriptor of the instruction which is loaded into the register R1". The instruction loaded into the register R1 during the processing of the ninth instruction has as location descriptor "40020", which in turn means: the number (4) having a value 20. Consequently, the word "00000020" is written into the register R1~ The importance of a location descriptor in an instruction with virtual opaqued is apparent therefrom. In this location descriptor, information is stored, which is processed in the series of instructions initiated by an instruction with virtual opaqued.
The eleventh instruction is:
FD001000; DYADIC ADD R0, R1 (Fig. 3 (III), incitory. 11).
The opaqued "FED" indicates a DYADIC operation (Figure I) between a first register R0 and a second register R1. The kind of the operation (value 0, bits 16 to 19) is an adding operation. Therefore, this instruction means: "Add the contents of register R0 and of register R1 to each other and write the result into register R0".
Rug I : = Rug C + Rug [1]
Rug ox = owe + 00000020 Rug I : = 00000020 The twelfth instruction is:
FB037001; SWORE WRIER I (Fig. 3 (III), incitory. 12) .
This instruction implies the following operations:
a) mom Greg I : = Rug I
mom t1FFF~ : = 20.
Consequently, the nunnery 20 is written at the memory location with the address OF
b) Rug I : = Rug to + 1 Rug I : = 1FFF + 1 Rug I : = 2000.
These operations in fact represent a "PUSH" operation applied to the register R7, which plays the part of a stack.
1~3~
PUN 10.909C 18 17.1~.1984 The thirteenth instruction is:
PHOBIC; LOADVAL PCR,IPCR (Fig. 3 (III), incitory. 13).
This is the final instruction by which the series of instructions initiated ho an instruction with virtual opaqued is terminated. This instruction comprises the operation: "Load into the register PER the contents of the register IPCR". Since the position of the program counter was stored in the register IPCR, this therefore miens that the instruction following the instructions with virtual opaqued, which is now finished, will now be next. The overall effect of the virtual lo instructions (seventh instruction AUDACITY 20) is now that to the top of the stack belonging to the stack pointer (register 7) the number 20 is added.
The fourteenth instruction located at the memory location with the address 5 is:
00018100; ADD STACK SWEARER] (Fig. 3 (III), incitory. 14).
The opaqued "00" belongs to the class of virtual opcodes. The computer system therefore carries out the following operations;
a) Rug [IPCR~ : = Rug PER
Rug CIPCR~ : = 6 b) Rug PER : = mom Greg OPERA + opaqued Rug PER : = mom ~7F00 + 00 Rug CPCR] : = 00001000.
The fifteenth instruction located at the memory location with the address 100 is:
FOE; LOADVAL R0,-1++~R~ (Fig. 3 (III), incitory. 15).
This instruction implies the following operations:
a) Rug I : = -1 + Rug Eye Rug [73 = -1 + 2000 Rug I : = 00001FFF.
b) Rug Sol = mom Greg [7 Rug I : = mom 3 Rug Lo = 20.
The presence of the value 20 at the memory location with the address 1FFF is the result of the processing of the twelfth instruction.
The sixteenth instruction is:
FOE ; LOADVAL R1,-1+ ~IPCR~ (Fig. 3 (IV), incitory. 16).
This instruction implies the following operations:
Rug I : = mom r-1 + Rug [IPCR~]
5`
PUN 10.909C 19 17.12.1984 Rug Al = mom E-1 + 6]
Rug 113 = ~53 Rug Al = 00018100 Therefore, (analogously to the ninth instruction) the code of the instruction with virtual opaqued is again loaded into the register R1.
The seventeenth instruction is:
FIFE; LOADVAL R1,~R1 (Fig. 3 (IV), instx. 17).
This instruction is analogous to the tenth instruction. The instruction, which is loaded into the register R1, has as location descriptor "18100", which represents the operation:
Rug ~13 = mom ~$100 + Rug ~EROR~J
Rug I : = mom ~100 + 0 Rug lo = mom ~1003 Rug 0 Consequently, the word 0 is loaded into the register R1. Also in this case it again appears how in a compute system according to the invention the location descriptor is used with an instruction with virtual opaqued.
The eighteenth instruction is:
FD001000; DYADIC ADD R0,R1 fig. 3 (IV), incitory. 18).
This instruction implies the following operation:
Rug I : = Rug Lo + Rug ~13 Rug I : = 00000020 + EN 0 Rug ~03 : = 00000000.
The fact that the result of this operation is 00000000 has here the consequence that the value 00000020 is loaded into the register CUR.
The nineteenth instruction is:
FB37001; STORE R0,~R7~ I (Fig. 3 (IV), incitory. 19).
This implies the following operation:
a) mom Greg I : = Rug I
mom luff : = Rug I
r : = 00000000.
b) Rug I : = Rug I +1 Rug I + 1 Rug I : = 00000020.
'm e twentieth instruction is:
PHOBIC; LOADVAL PCR,IPCR (Fig. 3 (rev), incitory. 20).
This implies the following operations:
~32~S
PUN 10.909C 20 17.12.1984 Rug LPCR~ = Rug ~IPCR]
Rug PI : = 00000006.
Consequently, again this is the final instruction by which a series of instructions initiated by a virtual opaqued is terminated.
The twenty-first instruction is:
01018101; ORSTA~K SWEARER (Fig. 3 (V), incitory. 21).
This is again an instruction with an opaqued ( 01 ) belonging to the class of virtual opcodes. The operations to be carried out are therefore:
a) Rug ~IPCRJ : = Rug PER
Rug PER : = 00000007.
b) Rug PER : = mom Greg OPERA + opaqued Rug PER : = mom E7F00 + 01 Rug PER : = mom EF01]
Rug PI : = 00001010 (see Figure 2).
It has now appeared from this instruction that with a virtual opaqued the contents of this opaqued serve both to recognize a virtual opaqued and to determine a memory address of a beginning instruction of a series of instruction words, which determine the meaning of the instruction with virtual opaqued.
The twenty-second instruction located at the memory location with the address 1010 is:
FIFE; LOADV~L R0,-1++~R7] (Fig. 3 (IV), incitory. 22).
This instruction comprises the following operations:
a) Rug I : = mom I + Rug ~713 Rug ~03 : = mom r-1 + 20003 Rug owe: = mom ~1FFF3 Rug ox : = owe (see therefore instruction 19).
b) Rug ~73 : -1 + Rug r7 Rug I : = 00001FFF.
The twenty-third instruction is:
FA11CFFF; LOADVAL R1,-1+ ~IPCR~ (Fig. 3 (V), incitory. 23).
This instruction comprises the following operation:
Rug I : = mom I + fog ~IPCR~
Rug I : = mom I + 7 Rug Lo = mom I
Rug El = 01018101.
The twenty-fcurth instruction is:
FIFE; LOADVAL Wrier (Fig. 3 (V), incitory. 24).
1~3~5 `
PUN 10.909C 21 17.12.1984 The location descriptor of the instruction stored in the register 1 comprises "18101". This implies the operation:
Rug ~13 = mom ~$101 + Rug SWEARER 3 Rug = mom ~1013 Rug lo]: = F0000100.
The twenty-fifth instruction is:
FD061000; DYADIC OR R0,R1 (Fig. 3 (V), incitory. 25).
In this instruction, the digit "6" indicates a logic "OR" operation.
Rug Lo = Rug I V Rug I
Rug r0] = F0000100.
The fact that now a negative number is introduced into Rug 0 (F, 2-complement notation), has the consequence that the value 00000010 is loaded into the register CUR. It now appears from this instruction and the preceding instructions that it is possible to have a variety Of operations carried out by means of virtual opcodes.
The twenty-sixth instruction is:
FB037001; STORE R0,~R7J++1 (Fix. 3 (VI), incitory. 26).
This instruction implies the following operations:
a) mom Greg ~733 : = Rug [03 mom = F0000100 b) Rug I : = Rug I + 1 Rug r7~ : = 1FFF + 1 Rug I : = 2000.
The twenty-seventh instruction is:
25 PHOBIC; LOADVAL PCR,IPCR (Fig. 3 (VI), incitory. 27).
which implies:
Rug rPCR3 : = Rug ~IPCR~
Rug PI : = 7.
The computer system will now process the instructions located at the memory location with the address 7 and will thus further handle the program. The elaboration of this instruction will not key described further because this is not essential to the description of the in-mention. This instruction then also terminates the computer program, which has been described for illustration of the operation of a computer system according to the invention.
Mainly two particular aspects have appeared from the description of this computer program. These aspects are:
a) the processing of an instruction with virtual opaqued;
PUN 10.909C 22 I I 17.12.1984 b) the processing of the location descriptor with an instruction with virtual opaqued.
The fact that in a computer system according to the invention in-structions with virtual opcodes can be used offers the system programmer a wide range of possibilities. When using an instruction with virtual opaqued, a series of instructions can be initiated to carry out a given processing operation. This processing operation may be an addition (instruction eleven) or a multiplication or any other operation. The system programmer can thus program the computer system by a self-chosen definition of virtual opcodes in a manner such that new instructions are obtained. In view of the efficient storage of PER
in IPCR and the fact that IRCR is used as index register, such new instructions are handled in an efficient manner. It is further possible by modifying O'ER (referring to another table) to offer per program another collection of instructions, the language in which the program has been written being taken into account (a PASCAL machine for PASCAL, or COBOL machine for COBOL).
m e location descriptor of an instruction with virtual opaqued comprises information which is processed in a series of instructions.
I The processing of this information can take place in different ways and is fully determined by the instructions from the said series. The instructions from this series are mostly instructions provided with a normal opaqued. However, it is alternatively possible to use here instructions with virtual opcodes. In this case, however, first the content of the IPCR register should be arranged on a stack in the memory.
Figure 7 illustrates a second computer program, with refererence to which a second embodiment of a method according to the invention will key explained. The second program can be executed only by a computer system provided with a register architecture as shown in Figure 6 because the execution of the second program requires the presence of a register VIM (B).
The execution of the second program has a great resemblance to that of the first program (Figure 2). Therefore, only the difference from the first program will be described. Since the register architecture shown in Figure 6 differs from that in Figure 1, a few instructions had to be adapted to this end. For example, the register SPY is no longer designated as D, but as E, while the instruction at s PUN 10.909C 23 17.12.1984 the memory location 0 now becomes FOE instead of FOE. Since these adaptations can e simply recognized, they will not be described here further.
Figure 8 Schick the result of the execution of the second computer program show in Figure 7. In this embodiment, the registers R8 and R9 are each time loaded with the value "00000000". The elaboration of the first 6 instructions does not differ from the elaboration of the first computer program.
At the seventh instruction, which is the instruction with virtual opaqued:
00060020; ADDSTA~K~20, the following operations are now carried out:
a) fog ~IPCR~ = fog ~R3 b) fog PER = mom Greg LOPER + OPAQUED
c) fog I = IRK
The use of these operations with this seventh instruction then yields:
a) fog LIPCR~ = 00000005 b) fog PER = mom ~7F00 + 00]
fog CPC~ : = 00001000 c) fog VOW : = 00060020.
m e difference from the elaboration of the first program now is that at least the location descriptor part of the contents of the instruction register is loaded into the register VIM the instruction with virtual opaqued which is processed was present in that register.
m e eighth instruction stored at the memory location with the address 1000 is:
FOE ; LOADVAL R0, -1 ++ ~R7~
This instruction is identical to the eighth instruction from the first program.
m e ninth instruction stored at the memory location 1001 is:
FAlFB000; LOADVAL R1 VOYEUR.
In the location descriptor "FB000", the letter "F" gives an indication that here an interpretation operation is concerned (Figure 5 of)). This instruction consequently means: "Load into register R1 the meaning of the location descriptor of the instruction which is loaded into the register B (VIM)". In the register VIM, the location descriptor 60Q20 is now present. The evaluation of this location descriptor yields the number 20. Consequently, the word "00000020" is written into the PUN OKAY 24 I 17.12.1984 register R1 the result of this ninth instruction is therefore identical to the result of the tenth instruction of the first program as shown in Figure 2. The difference between the first and the second computer program and consequently between the two (Figure 1, Figure 6) register architecture is therefore that when using the register VIM, an instruction can be saved (i.e. the instruction LOADVAL R1,-1+ ~IPCR~ ) .
The result of this instruction (LOADVAL R1 ,-1+~IPCR~), when using the second register architecture (Figure 6), is already obtained during the decoding of an instruction with virtual opaqued (fog LAIR = IRE ).
For illustration, Figure 8 shows the further elaboration of the second computer program shown in Figure 7. Because of the analogy with the first computer program, this elaboration may be assumed to be clear.
The use of a memory table offers the possibility of making an inventory of specialized instruction collections, by which instruction words are processed which have an opoode part belonging to the second class.
The invention further relates to a data processor provided with a memory for storing machine-coded instruction words which each comprise an opaqued part and a descriptor part, which opaqued parts belong to a finite collection which is subdivided into a first and a second class, this data processor further comprising a program counter register, an address generator and an opaqued decoder, which opaqued decoder is provided with first means for separately identifying opaqued parts of the first and the suckled class and with second means for generating a HO Luke 5 I
control signal under the control of aft identified opaqued word of he second class, this data processor further comprising a supplementary program counter register and transmission means, which transmission means have a first control input for receiving the control signal and are further provided with means for transmitting the contents of the program counter register to the supplementary program counter register under the control of a received control signal, while the address generator is adapted to generate under the control of the control signal a memory address at which a beginning instruction word of a series of instruction words for processing a descriptor par-t is located.
Such a data processor is also known from the aforementioned article "Instruction set extension".
A data processor according to the invention is characterized in that the data processor is provided with an operation extension register which has a second control input for receiving the control signal and an output which is connected to the address generator. As a result, the address generator can be realized in a simple manner when the operation extension register comprises a collection of addresses or address parts.
It is favorable that the data processor is further provided with a second register which has a -third control input for receiving the control signal and a-data input connected to the memory for receiving the operand descriptor part of an instruction word under the control of the control signal.
Thus, moorer program instructions can be saved.
The invention will be described more fully with reference to the drawing, in which:
Figure 1 shows a first embodiment of a register architecture of a computer system according to the invention, Figure lo shows diagrammatically the method according to the invention with reference to a flowchart, Figure 2 shows a first computer program, with reference to which a firs-t embodiment of the method according to the invention is illustrated, Figure 3 (I to Al indusive) shows the result of execution of he computer program of Figure 2, Figure 4 (a to f inclusive) shows a few different opcodes and -their associated instruction word classification, and PUN. Luke 6 ~3~7~
Figure 5 (a to f inclusive) shows a few different descriptor parts within an instruction word, Figure 6 shows a second embodiment of a register architecture of a computer system according to the invention Figure 7 shows a second computer program, with reference to which a second embodiment of the method according to the invention is illustrated, Figure 8 (I to V inclusive) shows the result of a handling of the computer program of Figure 7.
A data processing system or a computer which has to process an instruction will do so by handling a program which is suitable for pro yessing this instruction. This program is written in a kin programming language, such as, for example, PASCAL, FORTRAN or BASIC.
These programming languages are users languages, however, which are first translated by the computer into machine-coded instructions in order to handle the program. this translation of users' language into machine-coded instructions mostly takes place in two steps. A first step comprises translating users' language into "Assembly language"
and a second step comprises translating "Assembly language" into "machine instructions". The first step is handled by a "compiler" and the second step is handled by an l'assembler'l. The compiler and the assembler are both translation programs which form part of the computer system. Wren forming the compiler and the assembler, the system programmer has taken the architecture of the computer (CA =
computer architecture, i.e. the appearance of the machine from the viewpoint of the system programmer) into account.
In computer architecture, inter aria a distinction is made between two types of architecture, i e. HULL (High Level Language and RISK (Red owed Instruction Set Computers) architecture, HULL architecture mainly implies that the computer hardware is provided with an instruction set which is suitable for professing high level language. Thus, the gap between users' language and machine instructions becomes smaller. RISK
architecture mainly implies that the instructions of the machine are so simple that the hardware can accomplish maximum performances. However, in the case of RISK architecture, the translation of a users' program is much more difficult.
The advantages of these two said types of computer architecture are now combined in a data processing system according to the invention.
PUN 10.909C 7 ~32~7~ 17.12.1984 Such a data processing system in fact comprises a simple machine, whose instruction set is made extensible in order to be able to handle efficiently operations of the HULL type.
A computer system according to the invention comprises a central processing unit (CPU) with, for example, a register architecture. Figure 1 shows a first embodiment of a register arch- -.
lecture of a computer system according to the invention. The registers Row to R7 inclusive, just like the registers ZERO (8), O'ER (9), PER (Program Counter Register) (B), SPY (Stack Pointer Register) (D), CUR (Condition Code Register) (E) end SEX (Sign Extend Register) (F), are the conventional known index registers of a computer with a conventional register architecture. The registers IPCR (Interpreter Program Counter Register and O'ER (Operation Extend Register) (A) constitute an addition to the CPU, with which a register architecture is extended for use of the invention; it should be noted, however, that the register O'ER is optional. In the simplest construction, the register IPCR is sufficient. The use of the register IPCR by the computer system during the handling of a program is controlled by the OPAQUED PART of an instruction word to be handled or briefly designated as the OPAQUED (operation code).
Figure 6 shows a second embodiment of a register architecture of a computer system according to the invention. The registers Row to R7 inclusive, just like the registers O'ER and IPCR, are identical to the same registers of the first embodiment shown in Figure 1. The registers (8) and (9) are now designated by R8 and Rug. The registers PER (D), SPY (E) and CUR (F) fulfill the same fiction as the same registers of the first embodiment, but now have a different order in the system. New for the second em oddment is the register VlR (B), whose meaning will be explained hereinafter.
In this computer system, the OPCODES are subdivided into two classes, i.e. a first class, which comprises "normal" opcodes, and a second class, which comprises "virtual" opcodes. The opaqued decoder of the computer system is implemented so that it recognizes by the bit pattern of the opcodes to which class the opaqued belongs. For example, all the opcodes, which have as most significant bits (MOB) the value "0", can be recognized as "Noreen" opcodes, while all the opcodes, which have as MOB the value "1" can be recognized as "virtual" opcodes. As a result, a division is obtained, in which each class comprises an PUN 10.909C 8 17.12.1984 equal number of opcodes. However, it should key noted that any other division is also possible. An accurately defined implementation of the opaqued is then each time associated with a given division. It will ye clear that each class has to comprise at least one okayed.
The manner in which instructions with normal or with virtual opaqued are handled by a computer system according to the invention is illustrated diagrammatically with reference to the flowchart of Figure pa. After reading (50) an instruction word, it is determined (51) whether the opaqued belongs to the class of the virtual opcodes or to the class of the normal opcodes.
In the case in which the opaqued decoder has decoded an opaqued belonging to the class of normal opcodes (N), the associated in-struction is handled in known manner (52). However, in the case in which the opaqued decoder has decoded an opaqued belonging to the class of virtual opcodes (V), irrespective of the contents of the associated instruction, each time the operations stated below are carried out:
Rug riper = Rug ~PCR3 (53) Rug PER : = mom Greg OPERA + opcodel (54).
In this case, the operation Rug ~IPCRJ : = Rug Purl means that the contents of the register PER is rewritten into the register IPCR (: =
represents in programming language "becomes"); in other words: the address of the instruction indicated by the program counter (instantaneous program counter position) is loaded into the register IPCR. The operation Rug ~PCRJ : = mom Greg OPERA + opaqued means that the memory word (in this case an address word), which is stored at the memory location with the address Rug LOPER + opaqued, is loaded into the register PER. The address Rug LOPER + opaqued is composed by adding the contents of the register O'ER to the value as given in the opaqued part of the instruction word. This operation Rug PER : =
mom Greg row + opaqued consequently means that a new address for the program counter is loaded into the register PER.
It is also possible to generate this new address by other operations than by the operation Rug rPCR~ : = mom Leg OPERA + opaqued O Possible other operations are, for example:
a) Rug LPCR3 : = Rug loper + opaqued.
In this case the new address is directly determined without a reading operation from the memory being effected.
b) Rug PER : = opaqued + fixed address.
PUN 10.909C 9 I 17.12.1984 This is an operation which is used when, as already stated, the register O'ER is not used. The new address is composed in this case by adding a fixed address to the opaqued part of the instruction word.
c) Rug R] : = mom opaqued + fixed address .
Also in this operation the register O'ER is not used. This operation on the contrary comprises, however, a memory reading operation. Now a first instruction of a series of instructions, which interpret the meaning of the instruction word with virtual opaqued (55), is present at this new address for the program counter. This series of instructions lo is always terminated by a last instruction from the program which immediately follows the instruction with virtual opaqued which has ensured that the said series is processed. Such a lust instruction is, for example, of the form Rug PER : = Rug ~IPCR~ (56).
In this case, the program counter position is then again set to the value which it had at the beginning of the execution of the instruction with virtual opaqued part.
The useful effect of a virtual opaqued is that with each virtual opaqued a piece of code is executed. In this piece of code (the "Interpretator" of the virtual opaqued) it is possible to refer in an efficient manner to the argument descriptor(s) of the virtual opaqued if IPCR is used as index register.
When the computer system now has a register architecture as shown in Figure 6, during decoding of an opaqued belonging to the class of virtual opcodes, besides the operations (53) and (54) a further operation (150) is carried out, i.e.:
fog VOYEUR : IRE
The contents of at least the location descriptor part of the instruction register LOWRY of the computer system are transferred to the register VqR.
An instruction with a virtual opaqued is mainly distinguished from an instruction JUMP SUBROUTINE, which has a normal opaqued, in that during the handling of the subroutine the program counter position is stored temporarily in the memory. On the one hand, the memory writing operation necessary to this end requires an additional amount of handling time, while on the other hand it is thus not possible to use (without an additional amount of handling time) the old program counter position as index register for reading argument desecrators.
PUN 10.909C 10 1~32~S 17.12.1984 Figure 2 shows a first computer program, with reference to which a first embodiment of the operation of a computer system according to the invention will be explained more fully. The program is given only by way of example. It will be appreciated that a computer system according to the invention is not limited to the execution of solely programs of this kind.
In Figure 2 five columns can be distinguished. The first column indicates the memory addresses of the instructions. The second column states the instructions written in machine code (hexadecimal lo notation). The third and fourth columns indicate instructions written in "Assembly language", while the fifth column comprises a comment on the instruction.
Before Figure 2 will be considered more fully, with reference to Figures 4 and 5 first a few general aspects of the instructions will be described in order to clarify the reading of the program and its processing. The Figures 4 (a to f) show opcodes and their associated instruction word classification. An instruction as written in machine code (Figure 4 or second column Figure 2) comprises 32 ( 4 x 8) bits.
The bits 31 to 24 always comprise the opaqued. Since the opaqued part comprises 8 bits, 28 = 256 different opcodes are possible. In the example of Figure 2, the opcodes 00 to F8 belong to the class of virtual opcodes and the opcodes F9 to OF belong to the class of the normal opcodes. me classification of the remaining bits (0 to 23) depends upon the kind and the class to which the opaqued belongs.
Figure I shows the pattern of an instruction which has as opaqued one of the normal opcodes LOAD ADDRESS (F9), LOAD VALUE (FAX) or STORE (FOB). With this instruction, the bits 20 to 23 comprise the number of the register (RUN), to which the operation given by the opaqued relates, while the bits 0 to 19 comprise the location descriptor (LCDSC). The contents of this location descriptor will be discussed more fully hereinafter.
Figure I shows a pattern of an instruction, which has as opaqued the normal opaqued MONADIC (FC). With this instruction, the bits 20 to 23 comprise the number of the register (RUN), to which the operation given by the opaqued relates, while the bits 16 to 19 indicate the kind of the MONADIC operation PI (increment, decrement, etc.).
The remaining bits do not comprise information essential to this in-mention.
~23~
PUN 10.909C 11 17.12.1984 Figure I shows the alert of dun instruction which has as opaqued the normal opaqued DYADIC (FC). With this instruction, the bits 20 to 23 comprise the number of the first register (RUN) and the bits 12 to 15 comprise the number of the second register (RUT) to which the operation given by the opaqued relates. The bits 16 to 19 represent the kind of the DYADIC operation (DPC) (addition, subtraction, logic AND, etc.). The remaining bits do not comprise information essential to this invention.
Figure I and Figure I, respectively, show the pattern of an instruction, which has as opaqued the normal opaqued JUMP
SUBROUTINE (FE) and JUMP CONDITIONAL (OF), wherein for the instruction with opaqued OF the condition (CUD) is given by the bits 20 to 23. The bits 0 to 19 each time comprise the location descriptor (LCDSC). When now the computer system decodes the opaqued "FE", the following operations are carried out:
mom Greg SPIRO : = Rug PER
Rug SPIRO : = Rug SPIRO + 1 Rug LPCR] : = effa (LCDSC), where "effa" represents "effective address".
When decoding the opaqued "OF", in the case in which the condition (~) is satisfied, the following operation is carried out:
Rug LPCR~ = effa (LCDSC).
(The program counter position Greg ~PCR3 ) is not held because with a Jump Conditional no return takes place.
Figure I shows the pattern of an instruction with a virtual opaqued (00; ... ; F8). The bits 0 to 23 are used herein dependence upon the interpretation routine. This will be discussed in a further part of the description.
The location descriptor describes the address associated with the instruction operand. The computer system is provided with hardwrdre means to interpret this location descriptor. Figure 5 shows a number of examples of location descriptor parts within an instruction word. For each location descriptor the bits 16 to 19 each time indicate the kind of the descriptor, which will be described below fox each of the parts (a) to (f) of Figure 5.
(1) In Figure I the word "0000" represents a register operation with respect to the register surrounded by the bits 12 to 15. The contents of the bits 0 to 11 are not essential to the description YIN. 10.909C 12 of the invention.
by In Figure I, the word "0001" represents a normal index operation.
The resulting address thereof is a + Rug no a representing the number given by the bits 0 to 11 and n representing the register number given by the bits 12 -to 15.
(c) In Figure I the word 'Lowe" represents an index operation preceded by an adaptation operation (preadjust index).
Such an operation is carried out in two steps:
me address is given by a + Rug [n]
and also Rug [no : = a + Rug [no (a and n have the same meaning as stated above).
(d) In Figure I the word "0011" represents an index operation followed by an adaptation operation (post-adjust index). Such an operation is again carried out in two steps:
The address given by Rug no : = and also Rug to = a + Rug Lo (with analogous meaning for a and n).
With an index operation accompanied by an adaptation operation, therefore both a value and an address are each time determined. The use of the address is determined by the opaqued part.
(e) In Figure I the word "0100" represents a number whose value is given by the bits 0 to 15. ("Immediate").
(f) In Figure I the word "1111" represents an interpretation operation. The contents of the register, whose number is given by the bits 12 to 15 are considered as location descriptor. The contents of the bits 0 to 11 are not essential to the description of the invention.
With reference to the data from Figures 4 and 5, the computer program illustrated in Figure 2 will now be described. The result of the elaboration of this program is illustrated in Figure 3 (I to VI). Here-after, wherever an instruction is explained, there will be an accompany in reference in parentheses indicating the place in Figure 3 where the result of the instruction is shown.
The first instruction of the computer program is located at ~3~5 `
PUN 10.909C 13 17.12.1984 the IT Emory location with the address 0 and is:
FAD47FFF; LOADVAL SPR,?~L$7E~'F (Fig. 3 I) incitory. 1).
The opaqued "FAX" indicates that an instruction with normal opaqued (Figure 4 (a)) is concerned here, i.e. the instruction "LOAD VALUE".
5 The register number "D" indicates that the register to be used is the register SPY (Figure 1). The location descriptor comprises the number "47FFF". In this number the digit 4 indicates that a location descriptor of the type shown in Figure I is concerned, i.e. a number (Immediate), in this case the number 7FFF. This instruction 10 consequently means- "load (FAX) into the Stack Pointer Register (SPY) (D), the number (4) having a value I ". The number 1 is now stored in the program counter register (PER), which means that the next instruction is located at wrier location 1. It should be noted that in this endowment the register ZERO is loaded each time with the value 15 "00000000" and the register CANER is each time loaded with the value "00000001". The constant values 0 and 1 are frequently used. Therefore, it is efficacious to have these constant values available in a register so that they can be read by simple register operations.
At the memory location 1, the second instruction of the 20 computer program is located. This second instruction is:
FIFE; LOADVAL OPER,3~$7F00 (Fig. 3 (I), incitory. 2).
Analogously to the first instruction, this is an instruction with normal Gpcode "LOADVAL". The register number "A" indicates the register O'ER (Figure 1). This instruction therefore means: "Ioadinto the 25 Operation-Extend Register (O'ER) the number having a value 7F00".
Meanwhile, the number 2 has been loaded into the register PER.
The third instruction is:
FOE; JAR $400+EZERoR1 (Fig. 3 (I), incitory. 3).
The opaqued "FE" indicates the instruction with normal opaqued JO
30 SUBROUTINE" (Figure 4 (d)). The location descriptor comprises the number "18400"; the digit "1" therein indicates that a normal index operation is concerned (Figure I). The digit "8" indicates the register ZERO and the number "400" indicates the displacelrent. When this instruction is performed, there is obtained:
35 a) mom Leg LSPR3]: = fog LPCR3 mom r7~ : = 00000003.
This means that the number 3 is written at the memory location with the address or This implies that the address of the next instruction PUN 10.909C 14 17.12.1984 (memory address 3) is held at the memory location 7FFF.
b) Rug SPURGE : = Rug LSPR~ + 1 Rug SPIRO : = 00007FFF + 1 = 00008000.
c) Rug PER : = effa (LCDSC) effa (LCDSC) represents the effective content of the location descriptor, which is given for this example by 400 + ZERO .
However, since 00000000 is present in the register ZERO, effa (LCDSC) is 00000400 Rug tPCR3 = 00000900.
This means that the program counter now indicates the memory location with the address 400. Consequently, a jump has been made to the memory location with the address 400.
The fourth instruction located at the storage location with the address 400 is:
PHOEBE; LOADVAL R0,~PCR3++1 I ok I (Fig. 3 (I), incitory. 4).
The register number of this instruction with normal opaqued LOAD VALUE
is "0". In the location descriptor having a value "3B001", the digit 3 indicates an index operation followed by an adaptation operation (Figure I). The letter B indicates that the adaptation relates to the register PER (Figure 1) and the number "001" indicates the amount of the adaptation. This instruction consequently means:
Rug OX = mom Greg ~PCRJ3 Rug row = mom Eye Rug I : = I
Load into the register R0 the value which is stored at the memory address which is given by the contents of register PER and then in creases the contents of register PER by the number "001". The value (400 + 1 =) 402 is stored in the register PER. The value 7FFFFFFF, which is now stored in the register R0, is present at the address 401.
The adaptation operation then results in:
Rug R1 : = Rug RJ + 1 Rug RJ : = 401 + 1 Rug I : = 402.
The fifth instruction, which is located at the memory location with 402 is:
FAB2DFFF; LOADVAL PCR,-1++~SPR3 (fig. 3 (I), incitory. 5).
The register number "B" indicates the register PER. In the location PUN 10.909C 15 17.12.1984 descriptor having a value ED the digit 2 indicates an index operation preceded by an adaptation operation (Figure I); the letter D indicates the register SPY and the hexadecinEl number I
(2-complement notation) represents "-1", which indicates the quantity of the adaptation.
Rug SPIRO : = Rug SPIRO -1 Rug SPIRO : = 00008000 -1 Rug Pi : = 00007 Rug rPCR~ : = mom leg SPIRO
Rug I : = mom I
Rug PER : = 00000003 In fact, as indicated with the third instruction, the value "3" is loaded at the memory location with the address I The operation of reading from the memory and loading 00000003 into the register PER
means that the subroutine is terminated and that the ordinary program is now resumed again, i.e. with the instruction loaded at the address 3 of the memory.
The sixth instruction then is:
FOE; LOADVAL R7,~$2000 (Fig. 3 (II), incitory. 6).
This instruction implies: "Load into the reviser R7 the number having a value 2000".
The seventh instruction is:
00040020; ADDSTACX $20 (fig. 3 (II), incitory. 7).
The opaqued "00" indicates that an opaqued from the class of the virtual opcodes (00~ {00, ..., F8~) is concerned here. The decoding device of the computer system decodes this virtual opaqued and consequently the system will carry out the following operations:
a) Rug LIPCR~ = Rug PER
b) Rug PER : = mom Greg opera + OKAYED.
The use of these operations in this seventh instruction then results in:
a) Rug ~IPCR~ : = Rug rPCR~
Rug LIPCR~ : = 00000005.
The contents of the register PER (instantaneous program counter position) are consequently loaded into the register IPCR.
Therefore, in contrast with a JUMP SUBROUTINE instruction (third instruction), no writing operation is carried out here in the memory.
Moreover, the operation of loading from PER into IPCR requires a considerably staller amount of processing time because this is an PUN 10.909C 16 17.12.1984 ordinary register operation.
b) Rug PER : = mom Greg OPERA + OPCODEJ
Rug rPCR~ = mom ~7F00 + 00 Rug PER : = mom l7F0 Rug PER : = 00001000 In fact, as appears from Figure 2, the word 00001000 is written at the Emory location with the address 7F00, which word is now loaded into the register PER. The data from the last-mentioned Figure suggest that the contents of the location descriptor should be of no importance.
lo However, this is not the case. In the further description of the program it will appear that the location descriptor is used indeed with an instruction with virtual opaqued, even in a manner such that it comprises already a number of data which exceeds the number of data that would be possible, for example, with the use of the instruction JUMP SUBROUTINE, in which event only a memory address can be recorded.
The eighth instruction stored at the Myra location with the address 1000 is:
FOE; LOADVAL R0,-1++ ~R7~ (Fig. 3 (II), incitory. 8).
This instruction implies the following operations:
a) Rug Lo = -1 + fog 73 Rug I l + 2000 Rug I I
b) Rug to : = mom Greg ~73 3 Rug I : = mom ~lFFF3 Rug Lo =
The value 00000000 is present at the memory location with the address 1FFF.
These operations in fact represent a "POP" operation applied to the register R7, which plays the part of a stack pointer.
The ninth instruction:
FAllCFFF; LOADVAL R1,-1+ LIPCR] (Fig. 3 (II), incitory. 9).
This instruction implies the following operation:
Rug I : = mom r-1+ Rug LIPCR~
Rug ~13 = mom Lo I
Rug [1¦ : = mom I
Consequently, the contents of the memory location with the address 4 is loaded into the register R1. However, at this very location is present the seventh instruction, which has as machine code 00040020.
~32~3~5 PUN Luke 17 17.12.1984 This operation is intended to read the location descriptor of the virtual instruction in order to utilize it in a further instruction.
The tenth instruction is:
FIFE; LARVAL R1,~R1 (Fig. 3 (II), incitory. 10).
In the location descriptor "F1000", the letter "F" indicates that here an interpretation operation is concerned (Figure 5 (f!). This in-struction therefore means: "Load into register R1 the meaning of the location descriptor of the instruction which is loaded into the register R1". The instruction loaded into the register R1 during the processing of the ninth instruction has as location descriptor "40020", which in turn means: the number (4) having a value 20. Consequently, the word "00000020" is written into the register R1~ The importance of a location descriptor in an instruction with virtual opaqued is apparent therefrom. In this location descriptor, information is stored, which is processed in the series of instructions initiated by an instruction with virtual opaqued.
The eleventh instruction is:
FD001000; DYADIC ADD R0, R1 (Fig. 3 (III), incitory. 11).
The opaqued "FED" indicates a DYADIC operation (Figure I) between a first register R0 and a second register R1. The kind of the operation (value 0, bits 16 to 19) is an adding operation. Therefore, this instruction means: "Add the contents of register R0 and of register R1 to each other and write the result into register R0".
Rug I : = Rug C + Rug [1]
Rug ox = owe + 00000020 Rug I : = 00000020 The twelfth instruction is:
FB037001; SWORE WRIER I (Fig. 3 (III), incitory. 12) .
This instruction implies the following operations:
a) mom Greg I : = Rug I
mom t1FFF~ : = 20.
Consequently, the nunnery 20 is written at the memory location with the address OF
b) Rug I : = Rug to + 1 Rug I : = 1FFF + 1 Rug I : = 2000.
These operations in fact represent a "PUSH" operation applied to the register R7, which plays the part of a stack.
1~3~
PUN 10.909C 18 17.1~.1984 The thirteenth instruction is:
PHOBIC; LOADVAL PCR,IPCR (Fig. 3 (III), incitory. 13).
This is the final instruction by which the series of instructions initiated ho an instruction with virtual opaqued is terminated. This instruction comprises the operation: "Load into the register PER the contents of the register IPCR". Since the position of the program counter was stored in the register IPCR, this therefore miens that the instruction following the instructions with virtual opaqued, which is now finished, will now be next. The overall effect of the virtual lo instructions (seventh instruction AUDACITY 20) is now that to the top of the stack belonging to the stack pointer (register 7) the number 20 is added.
The fourteenth instruction located at the memory location with the address 5 is:
00018100; ADD STACK SWEARER] (Fig. 3 (III), incitory. 14).
The opaqued "00" belongs to the class of virtual opcodes. The computer system therefore carries out the following operations;
a) Rug [IPCR~ : = Rug PER
Rug CIPCR~ : = 6 b) Rug PER : = mom Greg OPERA + opaqued Rug PER : = mom ~7F00 + 00 Rug CPCR] : = 00001000.
The fifteenth instruction located at the memory location with the address 100 is:
FOE; LOADVAL R0,-1++~R~ (Fig. 3 (III), incitory. 15).
This instruction implies the following operations:
a) Rug I : = -1 + Rug Eye Rug [73 = -1 + 2000 Rug I : = 00001FFF.
b) Rug Sol = mom Greg [7 Rug I : = mom 3 Rug Lo = 20.
The presence of the value 20 at the memory location with the address 1FFF is the result of the processing of the twelfth instruction.
The sixteenth instruction is:
FOE ; LOADVAL R1,-1+ ~IPCR~ (Fig. 3 (IV), incitory. 16).
This instruction implies the following operations:
Rug I : = mom r-1 + Rug [IPCR~]
5`
PUN 10.909C 19 17.12.1984 Rug Al = mom E-1 + 6]
Rug 113 = ~53 Rug Al = 00018100 Therefore, (analogously to the ninth instruction) the code of the instruction with virtual opaqued is again loaded into the register R1.
The seventeenth instruction is:
FIFE; LOADVAL R1,~R1 (Fig. 3 (IV), instx. 17).
This instruction is analogous to the tenth instruction. The instruction, which is loaded into the register R1, has as location descriptor "18100", which represents the operation:
Rug ~13 = mom ~$100 + Rug ~EROR~J
Rug I : = mom ~100 + 0 Rug lo = mom ~1003 Rug 0 Consequently, the word 0 is loaded into the register R1. Also in this case it again appears how in a compute system according to the invention the location descriptor is used with an instruction with virtual opaqued.
The eighteenth instruction is:
FD001000; DYADIC ADD R0,R1 fig. 3 (IV), incitory. 18).
This instruction implies the following operation:
Rug I : = Rug Lo + Rug ~13 Rug I : = 00000020 + EN 0 Rug ~03 : = 00000000.
The fact that the result of this operation is 00000000 has here the consequence that the value 00000020 is loaded into the register CUR.
The nineteenth instruction is:
FB37001; STORE R0,~R7~ I (Fig. 3 (IV), incitory. 19).
This implies the following operation:
a) mom Greg I : = Rug I
mom luff : = Rug I
r : = 00000000.
b) Rug I : = Rug I +1 Rug I + 1 Rug I : = 00000020.
'm e twentieth instruction is:
PHOBIC; LOADVAL PCR,IPCR (Fig. 3 (rev), incitory. 20).
This implies the following operations:
~32~S
PUN 10.909C 20 17.12.1984 Rug LPCR~ = Rug ~IPCR]
Rug PI : = 00000006.
Consequently, again this is the final instruction by which a series of instructions initiated by a virtual opaqued is terminated.
The twenty-first instruction is:
01018101; ORSTA~K SWEARER (Fig. 3 (V), incitory. 21).
This is again an instruction with an opaqued ( 01 ) belonging to the class of virtual opcodes. The operations to be carried out are therefore:
a) Rug ~IPCRJ : = Rug PER
Rug PER : = 00000007.
b) Rug PER : = mom Greg OPERA + opaqued Rug PER : = mom E7F00 + 01 Rug PER : = mom EF01]
Rug PI : = 00001010 (see Figure 2).
It has now appeared from this instruction that with a virtual opaqued the contents of this opaqued serve both to recognize a virtual opaqued and to determine a memory address of a beginning instruction of a series of instruction words, which determine the meaning of the instruction with virtual opaqued.
The twenty-second instruction located at the memory location with the address 1010 is:
FIFE; LOADV~L R0,-1++~R7] (Fig. 3 (IV), incitory. 22).
This instruction comprises the following operations:
a) Rug I : = mom I + Rug ~713 Rug ~03 : = mom r-1 + 20003 Rug owe: = mom ~1FFF3 Rug ox : = owe (see therefore instruction 19).
b) Rug ~73 : -1 + Rug r7 Rug I : = 00001FFF.
The twenty-third instruction is:
FA11CFFF; LOADVAL R1,-1+ ~IPCR~ (Fig. 3 (V), incitory. 23).
This instruction comprises the following operation:
Rug I : = mom I + fog ~IPCR~
Rug I : = mom I + 7 Rug Lo = mom I
Rug El = 01018101.
The twenty-fcurth instruction is:
FIFE; LOADVAL Wrier (Fig. 3 (V), incitory. 24).
1~3~5 `
PUN 10.909C 21 17.12.1984 The location descriptor of the instruction stored in the register 1 comprises "18101". This implies the operation:
Rug ~13 = mom ~$101 + Rug SWEARER 3 Rug = mom ~1013 Rug lo]: = F0000100.
The twenty-fifth instruction is:
FD061000; DYADIC OR R0,R1 (Fig. 3 (V), incitory. 25).
In this instruction, the digit "6" indicates a logic "OR" operation.
Rug Lo = Rug I V Rug I
Rug r0] = F0000100.
The fact that now a negative number is introduced into Rug 0 (F, 2-complement notation), has the consequence that the value 00000010 is loaded into the register CUR. It now appears from this instruction and the preceding instructions that it is possible to have a variety Of operations carried out by means of virtual opcodes.
The twenty-sixth instruction is:
FB037001; STORE R0,~R7J++1 (Fix. 3 (VI), incitory. 26).
This instruction implies the following operations:
a) mom Greg ~733 : = Rug [03 mom = F0000100 b) Rug I : = Rug I + 1 Rug r7~ : = 1FFF + 1 Rug I : = 2000.
The twenty-seventh instruction is:
25 PHOBIC; LOADVAL PCR,IPCR (Fig. 3 (VI), incitory. 27).
which implies:
Rug rPCR3 : = Rug ~IPCR~
Rug PI : = 7.
The computer system will now process the instructions located at the memory location with the address 7 and will thus further handle the program. The elaboration of this instruction will not key described further because this is not essential to the description of the in-mention. This instruction then also terminates the computer program, which has been described for illustration of the operation of a computer system according to the invention.
Mainly two particular aspects have appeared from the description of this computer program. These aspects are:
a) the processing of an instruction with virtual opaqued;
PUN 10.909C 22 I I 17.12.1984 b) the processing of the location descriptor with an instruction with virtual opaqued.
The fact that in a computer system according to the invention in-structions with virtual opcodes can be used offers the system programmer a wide range of possibilities. When using an instruction with virtual opaqued, a series of instructions can be initiated to carry out a given processing operation. This processing operation may be an addition (instruction eleven) or a multiplication or any other operation. The system programmer can thus program the computer system by a self-chosen definition of virtual opcodes in a manner such that new instructions are obtained. In view of the efficient storage of PER
in IPCR and the fact that IRCR is used as index register, such new instructions are handled in an efficient manner. It is further possible by modifying O'ER (referring to another table) to offer per program another collection of instructions, the language in which the program has been written being taken into account (a PASCAL machine for PASCAL, or COBOL machine for COBOL).
m e location descriptor of an instruction with virtual opaqued comprises information which is processed in a series of instructions.
I The processing of this information can take place in different ways and is fully determined by the instructions from the said series. The instructions from this series are mostly instructions provided with a normal opaqued. However, it is alternatively possible to use here instructions with virtual opcodes. In this case, however, first the content of the IPCR register should be arranged on a stack in the memory.
Figure 7 illustrates a second computer program, with refererence to which a second embodiment of a method according to the invention will key explained. The second program can be executed only by a computer system provided with a register architecture as shown in Figure 6 because the execution of the second program requires the presence of a register VIM (B).
The execution of the second program has a great resemblance to that of the first program (Figure 2). Therefore, only the difference from the first program will be described. Since the register architecture shown in Figure 6 differs from that in Figure 1, a few instructions had to be adapted to this end. For example, the register SPY is no longer designated as D, but as E, while the instruction at s PUN 10.909C 23 17.12.1984 the memory location 0 now becomes FOE instead of FOE. Since these adaptations can e simply recognized, they will not be described here further.
Figure 8 Schick the result of the execution of the second computer program show in Figure 7. In this embodiment, the registers R8 and R9 are each time loaded with the value "00000000". The elaboration of the first 6 instructions does not differ from the elaboration of the first computer program.
At the seventh instruction, which is the instruction with virtual opaqued:
00060020; ADDSTA~K~20, the following operations are now carried out:
a) fog ~IPCR~ = fog ~R3 b) fog PER = mom Greg LOPER + OPAQUED
c) fog I = IRK
The use of these operations with this seventh instruction then yields:
a) fog LIPCR~ = 00000005 b) fog PER = mom ~7F00 + 00]
fog CPC~ : = 00001000 c) fog VOW : = 00060020.
m e difference from the elaboration of the first program now is that at least the location descriptor part of the contents of the instruction register is loaded into the register VIM the instruction with virtual opaqued which is processed was present in that register.
m e eighth instruction stored at the memory location with the address 1000 is:
FOE ; LOADVAL R0, -1 ++ ~R7~
This instruction is identical to the eighth instruction from the first program.
m e ninth instruction stored at the memory location 1001 is:
FAlFB000; LOADVAL R1 VOYEUR.
In the location descriptor "FB000", the letter "F" gives an indication that here an interpretation operation is concerned (Figure 5 of)). This instruction consequently means: "Load into register R1 the meaning of the location descriptor of the instruction which is loaded into the register B (VIM)". In the register VIM, the location descriptor 60Q20 is now present. The evaluation of this location descriptor yields the number 20. Consequently, the word "00000020" is written into the PUN OKAY 24 I 17.12.1984 register R1 the result of this ninth instruction is therefore identical to the result of the tenth instruction of the first program as shown in Figure 2. The difference between the first and the second computer program and consequently between the two (Figure 1, Figure 6) register architecture is therefore that when using the register VIM, an instruction can be saved (i.e. the instruction LOADVAL R1,-1+ ~IPCR~ ) .
The result of this instruction (LOADVAL R1 ,-1+~IPCR~), when using the second register architecture (Figure 6), is already obtained during the decoding of an instruction with virtual opaqued (fog LAIR = IRE ).
For illustration, Figure 8 shows the further elaboration of the second computer program shown in Figure 7. Because of the analogy with the first computer program, this elaboration may be assumed to be clear.
Claims (8)
1. A method of handling machine-coded instruction words by means of a data processor provided with a memory for storing the said instruction words, which each comprise an opcode part and at least one operand descriptor part, which opcode parts belong to a finite collection which is subdivided into a first and a second class, this method comprising the following steps:
(a) fetching a first instruction word indicated by a pro-gram counter position under the control of the data processor;
(b) decoding the opcode part from the first instruction word and determining, to which of the classes the opcode part of the first instruction word belongs;
(c1) carrying out the operations given by the first instruc-tion word for instruction words having an opcode part belonging to the first class;
(c2) carrying out the following steps for instruction words having an opcode part belonging to the second class:
(c2-1) storing the instantaneous program counter posi-tion in a supplementary program counter regis-ter of the data processor;
(c2-2) generating on the basis of the opcode part from the first instruction word a memory address at which a second instruction word is located, this second instruction word being the begin-ning instruction of a series of instruction words, which determine the meaning of the first instruction word;
(c2-3) setting the instantaneous program counter posi-tion to the said memory address;
(c2-4) handling the said series of instructions;
(c2-5) setting the instantaneous program counter posi-tion to a value determined by the program counter position present in the supplementary program counter register, characterized in that with the said series of instruction words, the operand descriptor part from the first instruc-tion word is loaded into a first register by at least one third instruction word.
(a) fetching a first instruction word indicated by a pro-gram counter position under the control of the data processor;
(b) decoding the opcode part from the first instruction word and determining, to which of the classes the opcode part of the first instruction word belongs;
(c1) carrying out the operations given by the first instruc-tion word for instruction words having an opcode part belonging to the first class;
(c2) carrying out the following steps for instruction words having an opcode part belonging to the second class:
(c2-1) storing the instantaneous program counter posi-tion in a supplementary program counter regis-ter of the data processor;
(c2-2) generating on the basis of the opcode part from the first instruction word a memory address at which a second instruction word is located, this second instruction word being the begin-ning instruction of a series of instruction words, which determine the meaning of the first instruction word;
(c2-3) setting the instantaneous program counter posi-tion to the said memory address;
(c2-4) handling the said series of instructions;
(c2-5) setting the instantaneous program counter posi-tion to a value determined by the program counter position present in the supplementary program counter register, characterized in that with the said series of instruction words, the operand descriptor part from the first instruc-tion word is loaded into a first register by at least one third instruction word.
2. A method of handling machine-coded instruction words by means of a data processor provided with a memory for storing the said instruction words, which each comprise an opcode part and at least one operand descriptor part, which opcode parts belong to a finite collection which is subdivided into a first and a second class, this method comprising the following steps:
(a) fetching a first instruction word indicated by a pro-gram counter position under the control of the data processor;
(b) decoding the opcode part from the first instruction word and determining, to which of the classes the opcode part of the first instruction word belongs;
(c1) carrying out the operations given by the first instruc-tion word for instruction words having an opcode part belonging to the first class;
(c2) carrying out the following steps for instruction words having an opcode part belonging to the second class;
(c2-1) storing the instantaneous program counter posi-tion in a supplementary program counter regis-ter of the data processor;
(c2-2) generating on the basis of the opcode part from the first instruction word a memory address at which a second instruction word is located, this second instruction word being the begin-ning instruction of a series of instruction words, which determine the meaning of the first instruction word;
(c2-3) setting the instantaneous program counter posi-tion to the said memory address;
(c2-4) handling the said series of instructions;
(c2-5) setting the instantaneous program counter posi-tion to a value determined by the program counter position present in the supplementary program counter register.
characterized in that, upon determination that the opcode of said first instruction word belongs to the second class, at least the operand descriptor part of said first instruction word is loaded, prior to said handling of said series of instructions, into a second register of the data processor.
(a) fetching a first instruction word indicated by a pro-gram counter position under the control of the data processor;
(b) decoding the opcode part from the first instruction word and determining, to which of the classes the opcode part of the first instruction word belongs;
(c1) carrying out the operations given by the first instruc-tion word for instruction words having an opcode part belonging to the first class;
(c2) carrying out the following steps for instruction words having an opcode part belonging to the second class;
(c2-1) storing the instantaneous program counter posi-tion in a supplementary program counter regis-ter of the data processor;
(c2-2) generating on the basis of the opcode part from the first instruction word a memory address at which a second instruction word is located, this second instruction word being the begin-ning instruction of a series of instruction words, which determine the meaning of the first instruction word;
(c2-3) setting the instantaneous program counter posi-tion to the said memory address;
(c2-4) handling the said series of instructions;
(c2-5) setting the instantaneous program counter posi-tion to a value determined by the program counter position present in the supplementary program counter register.
characterized in that, upon determination that the opcode of said first instruction word belongs to the second class, at least the operand descriptor part of said first instruction word is loaded, prior to said handling of said series of instructions, into a second register of the data processor.
3. A method as claimed in Claim 1, characterized in that, when the third instruction word is carried out, the contents of the supplementary program counter register are used to locate in the memory the operand descriptor part from the first instruction word.
4. A method as claimed in Claim 1, 2 or 3, charac-terized in that with the said series of instruction words, the operand descriptor part from the first instruction word is processed by at least one fourth instruction word.
5. A method as claimed in Claim 1, 2 or 3, charac-terized in that the step of generating the memory address for the second instruction word comprises the following sub-steps:
(1) forming a table address from a memory table by adding to the opcode part of the first instruction word a value which is previously stored in an operation extension register of the data processor.
(2) addressing the memory word located at the table address formed;
(3) fetching the memory word at the said table address, which memory word constitutes the memory address.
(1) forming a table address from a memory table by adding to the opcode part of the first instruction word a value which is previously stored in an operation extension register of the data processor.
(2) addressing the memory word located at the table address formed;
(3) fetching the memory word at the said table address, which memory word constitutes the memory address.
6. A data processor provided with a memory for stor-ing machine-coded instruction words which each comprise an opcode part and a descriptor part, which opcode parts belong to a finite collection which is subdivided into a first and a second class, the data processor further comprising a pro-gram counter register, an address generator and an opcode decoder, which opcode decoder is provided with first means for separately identifying opcode parts of the first and the second class and with second means for generating a con-trol signal under the control of an identified opcode word of the second class, the data processor further comprising a supplementary program counter register and transfer means, which transfer means have a control input for receiving the control signal and are provided for transferring the contents of the program counter register to the supplementary program counter register under the control of a received control sig-nal, said address generator being adapted to generate under the control of the control signal a memory address at which a beginning instruction word of a series of instruction words which determine the meaning of the instruction word upon which opcode decoding the control signal are generated, characterized in that the data processor is provided with an operation extend register which has a control input for receiving said control signal, said operation extend register being provided for storing a value to be used for forming said memory address and for supplying said value to said address generator under control of a received control signal, said data processor further comprising an index register for loading therein, after decoding of an instruction word having an opcode part belonging to the second class, the operand descriptor part of that instruction word.
7. A data processor as claimed in Claim 6, charac-terized in that said index register has a control input for receiving said control signal and being provided for loading said operand descriptor part under control of a received con-trol signal, said index register comprises a data input con-nected to the memory for receiving said operand descriptor part.
8. A method as claimed in Claim 1, 2 or 3, wherein with the said series of instruction words, the operand des-criptor part from the first instruction word is processed by at least one fourth instruction word, and wherein said step of generating the memory address for the second instruction word comprises the following substeps:
(1) forming a table address from a memory table by adding to the opcode part of the first instruction word a value which is previously stored in an operation extension register intended thereto;
(2) addressing the memory word located at the table address formed;
(3) fetching the memory word at the said table address, which memory word constitutes the memory address.
(1) forming a table address from a memory table by adding to the opcode part of the first instruction word a value which is previously stored in an operation extension register intended thereto;
(2) addressing the memory word located at the table address formed;
(3) fetching the memory word at the said table address, which memory word constitutes the memory address.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL8400129A NL8400129A (en) | 1984-01-16 | 1984-01-16 | METHOD FOR PROCESSING MACHINE-CODED INSTRUCTION WORDS, AND DATA PROCESSOR FOR PERFORMING THE METHOD |
| NL8400129 | 1984-01-16 | ||
| NL8403628 | 1984-11-29 | ||
| NL8403628A NL8403628A (en) | 1984-11-29 | 1984-11-29 | Processing of machine code instructions - using instructions with two part operation code, first being of normal structure and second acting as virtual operation code |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1232075A true CA1232075A (en) | 1988-01-26 |
Family
ID=26645921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000471845A Expired CA1232075A (en) | 1984-01-16 | 1985-01-10 | Method of handling machine-coded instruction words and data processor for carrying out the method |
Country Status (5)
| Country | Link |
|---|---|
| CA (1) | CA1232075A (en) |
| DE (1) | DE3500377A1 (en) |
| FR (1) | FR2573228A1 (en) |
| GB (1) | GB2153561B (en) |
| SE (1) | SE8500156L (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7624374B2 (en) | 2005-08-30 | 2009-11-24 | Microsoft Corporation | Readers and scanner design pattern |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3685117D1 (en) * | 1986-12-30 | 1992-06-04 | Ibm | DEVICE AND METHOD FOR EXTENDING THE COMMAND SET AND THE FUNCTIONS OF A COMPUTER. |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5931734B2 (en) * | 1977-10-25 | 1984-08-03 | デイジタル イクイプメント コ−ポレ−シヨン | central processing unit that executes instructions with special operand specifiers |
| US4293907A (en) * | 1978-12-29 | 1981-10-06 | Bell Telephone Laboratories, Incorporated | Data processing apparatus having op-code extension register |
-
1985
- 1985-01-08 DE DE19853500377 patent/DE3500377A1/en not_active Withdrawn
- 1985-01-10 CA CA000471845A patent/CA1232075A/en not_active Expired
- 1985-01-11 GB GB08500682A patent/GB2153561B/en not_active Expired
- 1985-01-14 SE SE8500156A patent/SE8500156L/en not_active Application Discontinuation
- 1985-01-15 FR FR8500513A patent/FR2573228A1/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7624374B2 (en) | 2005-08-30 | 2009-11-24 | Microsoft Corporation | Readers and scanner design pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2573228A1 (en) | 1986-05-16 |
| SE8500156D0 (en) | 1985-01-14 |
| DE3500377A1 (en) | 1985-07-25 |
| GB2153561B (en) | 1987-06-17 |
| GB8500682D0 (en) | 1985-02-13 |
| SE8500156L (en) | 1985-07-17 |
| GB2153561A (en) | 1985-08-21 |
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