NL8103031A - Werkwijze voor het vervaardigen van een geintegreerde logische injectiecel met zelfgecentreerde collector en basis en gereduceerde basisweerstand en cel vervaardigd volgens deze werkwijze. - Google Patents

Werkwijze voor het vervaardigen van een geintegreerde logische injectiecel met zelfgecentreerde collector en basis en gereduceerde basisweerstand en cel vervaardigd volgens deze werkwijze. Download PDF

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Publication number
NL8103031A
NL8103031A NL8103031A NL8103031A NL8103031A NL 8103031 A NL8103031 A NL 8103031A NL 8103031 A NL8103031 A NL 8103031A NL 8103031 A NL8103031 A NL 8103031A NL 8103031 A NL8103031 A NL 8103031A
Authority
NL
Netherlands
Prior art keywords
region
polycrystalline
conductivity type
semiconductor
lateral
Prior art date
Application number
NL8103031A
Other languages
English (en)
Dutch (nl)
Original Assignee
Fairchild Camera Instr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera Instr Co filed Critical Fairchild Camera Instr Co
Publication of NL8103031A publication Critical patent/NL8103031A/nl

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65Integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
NL8103031A 1980-08-04 1981-06-23 Werkwijze voor het vervaardigen van een geintegreerde logische injectiecel met zelfgecentreerde collector en basis en gereduceerde basisweerstand en cel vervaardigd volgens deze werkwijze. NL8103031A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10642880A 1980-08-04 1980-08-04
US10642880 1980-08-04

Publications (1)

Publication Number Publication Date
NL8103031A true NL8103031A (nl) 1982-03-01

Family

ID=22311366

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8103031A NL8103031A (nl) 1980-08-04 1981-06-23 Werkwijze voor het vervaardigen van een geintegreerde logische injectiecel met zelfgecentreerde collector en basis en gereduceerde basisweerstand en cel vervaardigd volgens deze werkwijze.

Country Status (4)

Country Link
JP (1) JPS5753973A (enrdf_load_stackoverflow)
DE (1) DE3129487A1 (enrdf_load_stackoverflow)
GB (1) GB2081508B (enrdf_load_stackoverflow)
NL (1) NL8103031A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3476295D1 (en) * 1983-09-19 1989-02-23 Fairchild Semiconductor Method of manufacturing transistor structures having junctions bound by insulating layers, and resulting structures
JPH08213475A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置とその製造方法
US6352887B1 (en) * 1998-03-26 2002-03-05 Texas Instruments Incorporated Merged bipolar and CMOS circuit and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4338622A (en) * 1979-06-29 1982-07-06 International Business Machines Corporation Self-aligned semiconductor circuits and process therefor
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact

Also Published As

Publication number Publication date
JPS5753973A (enrdf_load_stackoverflow) 1982-03-31
GB2081508B (en) 1985-04-17
DE3129487C2 (enrdf_load_stackoverflow) 1987-06-04
GB2081508A (en) 1982-02-17
DE3129487A1 (de) 1982-06-24

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Legal Events

Date Code Title Description
A85 Still pending on 85-01-01
BV The patent application has lapsed