NL8003519A - LEAKAGE CURRENT COMPENSATION FOR DYNAMIC MOSS LOGIC. - Google Patents

Description

I ·! * *> EHN 9780 1 N.V. Philips' Incandescent lamp factories in Eindhoven "Leakage current compensation ^ for dynamic MDS logic"

The invention relates to a logic circuit comprising a logic network connected between a number of inputs and an output, which comprises a number of field effect transistors with an insulated control electrode and which is controlled by at least 5 signals applied to the inputs for performing a logic operation. one clock signal and during which the logic operation may cause unwanted charge loss at the output due to momentary leakage currents within the logic network.

Dynamic MOS logic circuits are characterized by the fact that there are no DC paths between the supply terminals within the circuit. This offers the advantage of low power dissipation.

The operation of this type of circuit is based on synchronized charge transport between the various points of the circuit and the fact that each point involved in the information transfer has a parasitic capacity, so that a charge once applied to such a point is preserved for some time. , provided that this point is isolated from its surroundings as far as possible after the cargo has been supplied.

Logic processing on a number of input signals is effected in this type of circuit by means of a logic network, which contains MDS transistors and whose output is first charged by means of a "charging" transistor to a first potential opposite. with a (logical "1"). Thereafter, the output is discharged through the logical network if the result of the operation yields a logic "0", while the first potential (logic "1") is maintained if the result of the operation yields "1".

Particularly in somewhat more complex logic operations, the problem arises that different signal paths in the network also provide 30 different delay times for the signals, as a result of which it is possible that certain transistors connected to the output qp lead to undesired times, so that the output nevertheless 8003515 PHN 9780 2 • t »* * is partially discharged over the logical network, although the final result of the logical operation should be a logical" 1 ". This undesired discharge of the output will hereinafter always be referred to as a leakage current effect.

An example of such a circuit can be found on pages 175 and 176 of the book "MOS / LSI Design and Application" from "Texas Instruments Electronics series" by Mc. Graw Hill publishing Corp. The circuit illustrated and discussed there is a "full adder" circuit implemented in 2-phase dynamic MOS logic, which is subject to the leakage current effect under certain conditions. In order to prevent the leakage current effect, said circuit, as discussed in the mentioned book, can be performed in 4-phase M05 logic, whereby the "full adder" operation in two steps is carried out in succession by two separate leakage-free logic networks. .

The drawback is that one then needs 4 separate clock signals, which makes the integrated circuit considerably more complicated.

The object of the invention is to provide a logic circuit which can be operated without increasing the number of clock signals without the risk of loss of charge due to leakage current effect.

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To this end, the invention is characterized in that means are present during the execution of the logical operation, at least during periods of time in which leakage currents may occur, to supply compensation charging at the output of the logical network.

This measure according to the invention offers the possibility of eliminating the disturbing influence of the aforementioned leakage current effect with very simple means. In particular, the number of clock signals need not then be extended, so that the integrated circuit can remain as simple as possible.

A preferred embodiment of the circuit according to the invention is characterized in that said means contain a capacitance, one electrode of which is coupled to the output and the other electrode is controlled with a control signal derived from the clock signal (s).

This embodiment is based on the understanding that the current leakage currents occur for a very short time, so that there is no need for continuous compensation charging, which is advantageous with regard to the power consumption of the circuit.

8003519 I * »EHN 9780 3

The mentioned capacity fulfills the function of boat trap capacitor, which at the desired moment (namely the moment that leakage currents can occur) supplies a compensation charge to the output, because a voltage jump is applied to the other electrode at that moment. . The use of bootstrap capacitors is known per se, for example from: de Man, J.H. et al .: "Circuits for Digital Filters". IEEE Journal of Solid State Circuits Vd. SC-13 No. 5 October 1978, where a bootstrap capacitor is employed to compensate for signal loss due to charge distribution between the points on either side of a However, it has not hitherto been recognized that it is possible to effect a leakage current compensation with the aid of a boat trap capacitor connected to the output of a logical network.

It may further be advantageous for said capacitance to be wholly or partly formed by the capacitance between the control electrode and the channel of an insulated control electrode field effect transistor, the control electrode being coupled to the output and at least one of the main electrodes being controlled with one of the clock signal (s) derived control signal.

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The invention will be further elucidated with reference to the following figures:

Figure 1a shows the schematic of a simple logic circuit, largely executed in 2-phase MOS logic, in which leakage currents can occur under certain circumstances.

Figure 1b shows the course of the clock signals associated with the circuit of Figure 1. 1a.

Figure 2a shows the schematic of a simple logic circuit derived from the circuit of Figure 1, but to avoid leakage currents performed in 4-phase MOS logic.

Figure 2b shows the course of the clock signals associated with the circuit of Fig. 2a.

Figure 3a shows an embodiment of the circuit according to the invention, based on the logic circuit according to Fig. 1a.

Figure 3b shows the course of the clock signals associated with oc the circuit of Fig. 3a.

Figure 4 shows the schematic of a "full adder" circuit according to the invention.

8003519 A 9780 4 »1.1

Figure 1a shows the schematic of a simple logic circuit, largely executed in 2-phase MDS logic with the switching function F = A.B.

The input signals A and B are applied to the control electrodes of the transistors and T2, respectively; the clock signal 01 is applied to the control electrode of the transistor and the clock signal 02 to the control electrodes of the transistors Tg and Tj.

Figure 1b shows how the clock signals ^ and 02 proceed in time.

Transistor T2, together with the charging transistor T1, forms a dynamic reversing circuit which, at point P, forms the inverse of signal B which is applied to the control electrode of transistor Tg.

The transistors T ^ Tg and Tg form a non-AND gate, which has the function F = A.B. realizes.

The result of the operation according to this function is applied via the transistor T ^ during the time that clock signal 02 is "high" to the input of the static switching circuit, consisting of the transistors Tg and T ^, which are the last determined value of the function F = AB buffers.

When the clock signal is "high", points P and Q are charged via transistor and transistor Tg, respectively. When the clock signal ^ becomes low again, the points P and Q are therefore qp "high" potential. As soon as the clock signal 02 becomes "high", depending on the logic levels of the signals A and B at the point Q, an undesired discharge may occur, while the potential at point Q must remain "high". For example, suppose that the signals A and B and the points P and Q are all "high". When clock signal 02 becomes "high", point P will have to be discharged via transistors T2 and Tg. That takes some (albeit short) time.

Thus, during this short period of time, Transidor Tg will still be offered a high gate potential, which will keep transistor Tg conducting, while at the same time the transistors Ti and Tg will conduct, causing the point Q to be more or less severely discharged. It will be clear that this has adverse consequences for the reliability of the circuit.

A known solution to the identified problem is shown in Figure 2a and is based on a condition which can be found 8003519 PHN 9780 5 at biz. 247 and 248 of the book "Switching and finite automata theory" by Zvi Kohavi (Me. Graw Hill). This condition says that for a synchronous circuit (in this case therefore a dynamic MOS circuit) to function correctly, it is necessary that the signal delays which occur within a certain elementary part of that circuit must not be perceptible as such outside that part. to be.

This condition is to make sure that the input signals of another part of the circuit, the input (s) of which are coupled to the output (s) of the first elementary part, do not change during the time that this other part is busy with the signal processing.

The aforementioned condition can be met by, as shown in Figure 2a, providing the switching circuit, consisting of the transistor T2 and and the non-ONE gate, consisting of the transistor, with separate "sample" transistors Respectively Tg, each of which is supplied with a separate clock signal φ ^ and (2 ^ 3331) their control electrode. The inverse of B and the non-AND function are then realized one after the other. (The course of the clock signals is shown in Figure 2b) This therefore costs an extra transistor, while the clock logic and the .1 layout of the circuit become more complicated.

The circuit works as follows: when the clock signal φ ^ is "high", the point P is charged. Then, when the clock signal φ ^ goes high, the point P must be the inverse of the input signal B, which information is retained by the clock signal φ0 on the control electrode of transistor T3 becoming low. As soon as the clock signal p3 becomes high, the logic value of the function F = A.B.

available. With the aid of clock signal 04, which in this case may be equal to clock signal φ ^, this information is transmitted via transistor T_ to the static orator circuit consisting of TQ and TQ.

Figure 3a shows an embodiment of the logic circuit according to the invention and Figure 3b shows the associated clock signals. The circuit in Figure 3a, which is substantially identical to that of Figure 1a, is provided with a capacitor, which preferably consists of the capacitance between the control electrode and the channel of a MOS 35 transistor, in this case T ^, arranged between the point Q and the line carrying the clock signal 02. The operation of this bootstrap capacitor is as follows: 8003519, V »PHN 9780 6

Suppose that as the clock signal φ ^ becomes "high", unwanted discharge of point Q occurs as a result of a short-circuit short-circuit current through the transistors Tg, and Tg, as described earlier in this text. During the rising edge of clock signal φ0, 5 ^ is then charged through the bootstrap capacitor to point Q, thereby compensating for the charge leakage from point Q as a result of said short-term leakage current.

If no leakage current occurs and a "1" appears at point Q as a result of the logic operation, the bootstrap capacitor will also provide additional charge supply to point Q, but this will not hurt, as it is only d ® potential of point Q increases, which does not affect the interpretation of the logic level of point Q. If the result of the logic operation yields a "0" at point Q, the additional charge supplied by the bootstrap capacitor discharged via the transistors, Tg and Tg, which are then conductive, so that this also has no consequences for the interpretation of said logic level. As the timing diagram of the clock signals in FIG. 3b shows the clock signals may be inverse of each other here, which is advantageous with regard to the clock logic.

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Figure 4 shows the diagram of a so-called "full adder" circuit with leakage current compensation according to the invention. In this circuit, the transistors T1, Tg and Tg form Tg and T7, respectively, for the logic signals A, D and B respectively.

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The transistors Tg through T ^ g form 4 non-AND gates, the outputs of which are connected at point 2.

Based on the input signals A, B and D and the inverse A, B and D, they realize the logical function:

30 S = ABD + ABD + ABD + ABD

The operation of the circuit is as follows: During the time when the clock signal φ is "high", points 1, 2, 3 and 4 are made through the respective. charging transistors T ^, Tg, Tg and T ^ charged. When the clock signal φ becomes "high", the inversions of the input signals, A, B and D, are formed by the shifter circuits and at the same time the non-AND gates of the input signals and their inverses form the logic function, the result of which is S appears at point 2. The fact that short-term leakage currents may occur in the non-AND gates will be 8003519 EHN 9780 7

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are explained by the following example.

For example, suppose that the input signal A is "low", that the input signals B and D are "high" and that the points 1, 2, 3 and 4 are charged ("high"). If the clock signal 0 is "high", a logical "1" will have to be possible at point 2.

Point 1 will remain "high" during the realization of the said logic function. Points 3 and 4 will have to be discharged through the respective transistors T2 and Tg. This takes time, it being very likely that either of the points 3 and 4 will discharge faster than the other due to difference in capacitance and / or difference between transistors Tg and Tg. For example, if point 4 discharges faster than point 3, the transistor will be able to conduct for a very short time. Transistor T ^ is conductive, so that in this case the input signal A is "low", so point 1 is "high". The point 2 could thus be partially discharged, and that a transient leakage current flows through the transistors T 1, T 2 g and 2. However, the bootstrap capacitor in the form of Tg ensures that the point is supplied with additional charge at the moment that this short-term leakage current can occur, so that the logic level at this point nevertheless yields a logic "1".

Finally, the signal at point 2 during the time the clock signal h ° ° 9 is passed through transistor T ^ to the static inverter consisting of transistors T ^ g and T ^ g, which functions as a buffer.

25 30 35 ___________________ ________, J_ 800 3 5 1 9

Claims (3)

1. Logic circuit with a logic network between a number of inputs and an output, which comprises a number of field-effect transistors with an insulated control electrode and which is controlled for transmitting a logic operation to signals applied to the & inputs by at least one clock signal and wherein agitating the logic operation unwanted charge loss at the output may occur due to momentary leakages within the logic network, which is characterized in that means are present during the logging operation of the logic operation at least during periods in which leakage currents 10 may occur. stir at the output of the logic network. Logic circuit according to claim 1, characterized in that said means comprise a capacitance, one electrode of which is coupled to the output and the other electrode is controlled with a control signal derived from the clock signal (s). Logic circuit according to claim 2, characterized in that said capacitance is formed wholly or partly by the capacitance between the control electrode and the channel of a field effect transistor with an insulated control electrode, the control electrode being coupled to the output and at least one of the main electrodes is controlled with a control signal derived from the clock signal (s). 25 30 35 8003519