GB2078459A - Leakage current compensation for dynamic MOS logic - Google Patents

Abstract

A leakage current compensation arrangement which can compensate for loss of charge at the output of a logic network realized in dynamic MOS technique, which loss is caused by the occurrence of brief leakage currents in the network during a logic operation. The use of this leakage current compensation in 2-phase dynamic MOS-logic makes it readily possible to handle 2 logic functions per clock period, which clock signals may be each other's inverse, which results in faster operation and a simpler design of the logic. As shown, bootstrap capacitor T11 raises the potential at node Q when phi 2 goes high to compensate for transient leakage which could be caused by T3 conducting while node P reaches its steady-state potential. If no such transient occurs, and no discharge path is established, the potential of node Q will remain at the raised level, or else be discharged, depending on the inputs A,B. <IMAGE>

Description

SPECIFICATION Leakage-current compensation for dynamic MOS logic The invention relates to a logic circuit with a logic network included between a plurality of inputs and an output, which network comprises a plurality of insulated-gate field-effect transistors and, for subjecting the signals applied to the inputs to the logic operation, is controlled by at least one clock signal.

A characteristic feature of dynamic MOS logic circuits is that within the circuit there are no d.c. paths between the power supply terminals, This has the advantage of a low power dissipation.

The operation of this type of circuit is based on the synchronized charge transfer between the various points or nodes of the circuit and the fact that each point involved in the information transfer has a parasitic capacitance, so that a charge once applied to such a point is preserved for some time, provided that after the application of the charge said point is suitably isolated from its environment.

In this type of circuit a logic operation is applied to a plurality of input signals by means of a logic network, which comprises MOS transistors and whose output is first charged to a first potential corresponding to a logic "1" by means of a "pre-charging" transistor. Subsequently, the output is discharged via the logic network if the result of the operation is a logic "0", whilst the first potential ("logic ''1"'') is maintained if the result of the operation is a "1".

Especially in the case of more complex logic operations the problem occurs that different signal paths in the network also result in different propagation delays for the signals, so that it may happen that specific transistors which are connected to the output are conductive at undesired instants, as a result of which the output is still partly discharged via the logic network, although the ultimate result of the logic operation should have been a logic "1". This undesired discharging of the output will be referred to hereinafter as the leakage-current effect.

An example of such a circuit can be found on pages 175 and 176 of the book "MOS/LSI" Design and Application" of the "Texas Instruments Electronics series" by McGraw Hill Publishing Corp. The circuit shown and described therein is a full adder circuit in 2-phase dynamic MOS logic, which under certain circumstances suffers from the leakage-current effect. In order to preclude the leakage-current effect this circuit, as is discussed in the said book, may be realized in 4phase MOS-logic, so that the full adder operation is effected in two successive steps by two separate logic networks, which themselves are exempt of leakage currents. The drawback is that then 4 separate clock signals are required, which substantially complicates the integrated circuit.

It is an object of the invention to provide a logic circuit, which, without increasing the number f clock signals, can be operated without the risk of loss of charge owing to the leakage current effect.

According to the present invention there is provided a logic circuit comprising a logic network included between a plurality of inputs and an output, which network comprises a plurality of insulated-gate field-effect transistors, means for applying one clock signal to the logic network for controlling the logic operation applied to the signals on said inputs and means for applying a compensating charge to the output of the logic network during the logic operation in order to compensate for any undesired loss of charge which may occur at the output during the logic operation as a result of brief leakage currents within the logic network, said compensating charge being applied at least during time intervals in which leakage currents may occur.

This step of applying a compensating charge to the output of the logic network at least during the logic operation makes it possible to eliminate the undesired consequences of the said leakage current effect by very simple means. In particular, the number of clock signals need not be increased, so that the integrated circuit can remain as simple as possible.

In an embodiment of the circuit in accordance with the invention said compensating charge applying means comprise a capacitance, whose one electrode is coupled to the output and whose other electrode is controlled by a control signal derived from the clock signal or signals.

This embodiment is based on the recognition that said leakage currents occur during a very short time, so that it is not necessary to apply continuously the compensating charge, which is of advantage in view of the current consumption of the circuit.

The said capacitance functions as a bootstrap capacitor, which at a desired instant (namely at the instant that leakage currents may occur) supplies a compensating charge to the output through the application of a voltage transient to the other electrode at this instant. The use of bootstrap capacitors is known per se, for example from: de Man, J.H. et al.: "NMOS Circuits for Digital Filters", IEEE Journal of Solid State Circuits, Vol. SC-13, No.5 October 1 978, where a bootstrap capacitor is used in order to compensate for the signal loss owing to charge distribution between the points on both sides of a transfer gate. However, until now it was not recognized that leakage current compensation can be obtained by means of a bootstrap capacitor connected to the output of a logic network.

If desired said capacitance may be partly or completely constituted by the capacitance between the gate electrode and the channel of an insulated-gate field-effect transistor, the gate electrode being coupled to the output and at least one of the main electrodes being controlled by a control signal derived from the clock signal or signals.

The present invention will now be explained and described, by way of example, with reference to the accompanying drawings, wherein: Figure la shows the circuit diagram of a simple logic circuit, largely realised in 2-phase MOS logic, in which under certain circumstances leakage currents may occur, Figure ib represents the clock signals associated with the circuit of Fig. 1 a, Figure 2a shows the circuit diagram of a simple logic circuit, derived from the circuit shown in Fig. 1, but realized in 4-phase MOSlogic in order to preclude leakage currents, Figure 2b represents the clock signals associated with the circuit of Fig. 2a, Figure 3a shows an embodiment of the circuit in accordance with the invention, based on the logic circuit of Fig. 1a, Figure 3b represents the clock signals associated with the circuit o Fig. 3a, and Figure 4 shows the circuit diagram of a "full adder" circuit in accordance with the invention.

Fig. la shows the circuit diagram of a simple logic circuit, which is mainly realized in 2-phase MOS logic and which has the switching function F = A.B.

The input signals A and B are respectively applied to the gate electrodes of transistors T and T2; the clock signal qi1 is applied to the gate electrode of transistor T4 and the clock signal 02 to the gate electrodes of transistors T6 and T7.

Fig. 1 b represents the clock signals 01 and +2 as a function of time.

Transistor T2 together with the charging transistor T4 constitutes a dynamic inverter circuit, which generates the inverse of signal B on point P, which signal is applied to the gate electrode of transistor Ts.

Transistors T1, T3 and T5 constitute a NAND-gate, which generates the function F = A.B.

During the time that the clock signal +2 is "high" the result of the operation in accordance with said function is applied, via transistor T7, to the input of the static inverter circuit, comprising transistors T8 and T9, which buffers the last value determined in accordance with the function F = A.B.

During the time that the clock signal 01 is "high" points or nodes P and Ct are charged via transistor T4 and transistor T5 respectively.

If the clock signal f1 becomes low again, points P and Q will therefore be at a "high" petential. As soon as the clock signal +2 becomes high an undesired discharge may occur at point Q depending on the logic levels of the signals A and B, whilst the potential of the point Q should remain "high". Assume for example that signals A and B and points P and Q are all "high". When clock signal +2 becomes "high" point P should be discharged via transistors T2 and T6. This takes a finite (though a very short) time.

Thus, during this very short time transistor T3 still receives a high gate potential, so that transistor T3 remains conducting, whilst simultaneously transistors T1 and T6 are turned on, so that point Q is partially or completely discharged. It will be evident that this has an adverse effect on the reliability of the circuit.

A known solution for said problem is represented in Fig. 2a and is based on a requirement which can be found on pages 247 and 248 of the book "Switching and finite automata theory" by Zvi Kohavi (McGraw Hill). In accordance with this requirement, for a correct operation of a synchronous circuit (that is in the present case a dynamic MOS circuit), it is necessary that the signal delays which occur within a specific elementary part of said circuit should not manifest themselves outside said part. In other words the delay of said part should be determined by the clock signal(s).

This requirement is necessary to ensure that input signals from another part of the circuit, whose input(s) is (are) coupled to the output(s) of the first-mentioned elementary part do not vary during the time that said other part is engaged in signal processing.

As is shown in Fig. 2a, said requirement can be met by providing the inverter circuit comprising the transistors T2 and T4 and the NAND-gate comprising transistors T1, T3 and T5 with separate sampling transistors T10 and T6, respectively, which each receive a separate clock signal +2 and fs respectively at their gate electrodes. The inverse of B and the NAND-function are then realized after each other. (The clock signals are represented in Fig. 2b). This demands an additional transistor, whilst the clock logic and the lay-out of the circuit become more. intricate. The circuit operates as follows: if the clock signal +, is "high" point P is charged. If subsequently the clock signal 02 becomes high, the inverse of the input signal B will appear on point P, which information is maintained on the gate electrode of transistor T3 after the clock signal +2 becomes low. As soon as the clock signal fs becomes high, the logic value of the function F = A.B will appear on point Q. By means of clock signal 4, which in this case may be identical to the clock signal sss, this information is transferred to the static inverter circuit comprising T8 and T9 via transistor T7.

Fig. 3a shows an embodiment of the logic circuit in accordance with the invention and Fig. 3b shows the associated clock signals.

The circuit in Fig. 3a, which is substantially identical to that of Fig. 1 a, is provided with a capacitor, which suitably comprises the capacitance between the gate electrode and the channel of a MOS transistor, in the present case T11, included between point Ct and the line carrying clock signal 02. The operation of this bootstrap capacitor is as follows.

Assume that when the clock signal +2 becomes "high" an undesired discharging of point Q occurs owing to a brief short-circuiting current through the transistors Ts, T1 and T6, as described previously. During the risingedge of the clock signal 02 charge is transferred to point Q via the bootstrap capacitor, so that the charge which leaks away owing to the said brief leakage current is compensated for.

If no leakage current occurs and a "1" appears on point Q as the result of the logic operation, the bootstrap capacitor will also supply additional charge to point Ct, but this can have no adverse effect, because it merely raises the potential of point Q, which does not affect the interpretation of the logic level of point Ct. If the result of the logic operation yields a "O" on point Q, the additional charge supplied by the bootstrap capacitor is drained via transistors Ts, T4 and T6, which are then conducting, so that neither of these conditions has any consequences for the interpretation of the said logic level. As is apparent from the timing diagram of the clock signals in Fig. 3b, the clock signals may be each other's inverse, which is advantageous for the clock logic.

Fig. 4 represents the circuit diagram of a so-called "full adder" circuit with leakage current compensation. In this circuit transistors T1 and T4, T2 and Te, and T3 and T7 respectively constitute inverter circuits for the logic signals A, B and D.

Transistors Te to T,5 constitute 4 NANDgates, whose outputs are connected to point 2.

Starting from the input signals A, B and D and the inverse signals A, B and D they realize the logic function: S = ABD + ABD + ABD + ABD The operation of the circuit is as follows: In the time that the clock signal f is "high", points 1, 2, 3 and 4 are charged via the respective charging transistors T4, Te, Te and T7. If the clock signal f becomes "high", the inverter circuits form the inverse A, B and D of the input signals and simultaneously the NAND-gates generate the logic function from the input signals and their inverse signals, the result S appearing on point 2. The possibility that short leakage currents may then arise in the NAND-gates, will be explained by means of the following example.

Assume for example that the input signal A is "low", that the input signals B and D are "high" and that points 1, 2, 3 and 4 are charged ("high"). If the clock signal (P is "high" this should ultimately result in a logic "1" on point 2.

During the execution of said logic function point 1 will remain "high". Points 3 and 4 should be discharged via the respective transistors T2 and T3. This takes time, whilst it is likely that one of the two points 3 and 4 discharges faster than the other one owing to the difference in capacitance and/or a difference between transistors T2 and Ts. If for example point 4 discharges faster than point 3, transistor Tie can be turned on for a very short time. Transistor T14 conducts, because in this case the input signal A is "low" and hence point 1 is "high". Thus point 2 could be partly discharged, because there is a brief leakage current via transistors Tri4, Tie and T2 However, the bootstrap capacitor in the form of transistor Tie ensures that point 2 receives additional charge at the instant that said brief current occurs, thereby ensuring that the logic level on this point results in a logic "1".

Finally, during the time that the clock signal ss is high the signal on point 2 is transferred, via transistor T17, to the static inverter stage comprising transistors Tie and T19, which stage functions as a buffer.

Claims (4)

1. A logic circuit comprising a logic network included between a plurality of inputs and an output, which network comprises a plurality of insulated-gate field-effect transistors, means for applying at least one clock signal to the logic network for controlling the logic operation applied to the signals on said inputs and means for applying a compensating charge to the output of the logic network during the logic operation in order to compensate for any undesired loss of charge which may occur at the output during the logic operation as a result of brief leakage currents within the logic network, said compensating charge being applied at least during time intervals in which leakage cirrents may occur.

2. A logic circuit as claimed in Claim 1, wherein said compensating charge applying means comprise a capacitance having one electrode coupled to the output and another electrode controlled by a control signal derived from the clock signal(s).

3. A logic circuit as claimed in Claim 2, wherein said capacitance is partly or completely constituted by the capacitance between the gate electrode and the channel of an insulated-gate field-effect transistor, the gate electrode being coupled to the output and at least one of the main electrodes being controlled by a control signal derived from the clock signal(s).

4. A logic circuit with a logic network included between a plurality of inputs and an output, constructed and arranged to operate substantially as hereinbefore described with reference to Figs. 3a and 3b or Fig. 4 of the accompanying drawings.