GB2092850A - Pulse generating circuit - Google Patents

Abstract

A plurality of normally non-conducting, input signal responsive, transistors (N1-Nm) have conduction paths connected in parallel between a first point of operating potential (for example, ground) and an output line, (121) so that when any one of them is rendered conductive the potential on the output line is driven to a first value of potential at the first point (Ground). Load means including the conduction paths of a first, normally on, transistor (P1) and a second, normally off, transistor (P2) are connected in parallel between the output line (12) and a second point at a second value (for example, VDD) of potential. Means (18, 20) responsive to the potential on the output line (12) control the impedance of the load means by applying a turn-off signal to the first transistor (P1) followed by a delayed turn-on signal to the second transistor (P2) when the potential on the output line is driven towards the first value of potential (Ground) and by applying a turn-on signal to the first transistor (P1) followed by a delayed turn-off signal to the second transistor (P2) when the potential on the output line is being restored to the second value of potential (VDD). <IMAGE>

Description

SPECIFICATION Pulse generating circuit This invention relates to circuitry for generating a well-defined narrow pulse having sharp leading and trailing edges.

In the accompanying drawing like reference characters denote like components; and FIGURE 1A is a schematic diagram of a prior art circuit; FIGURE 1B includes waveform diagrams of a typical output of the circuit of FIGURE 1A and of a desired output signal; FIGURES 2, 5, 6, and 8 are schematic diagrams of circuits embodying the invention; FIGURE 3 includes waveform diagrams of a signal applied to, and of an output signal produced by, the circuit of FIGURE 2, and graphs illustrating the turnon and turn-off sequence of load transistors in the circuit of FIGURE 2; FIGURE 4A is a schematic diagram of a delay network suitable for use in the circuit of FIGURE 3; FIGURE 48 is a diagram of waveforms associated with the circuit of FIGURE 4A; and FIGURE 7 shows waveform diagrams of signals discussed in connection with the circuit of FIGURE 6.

In many applications it is necessary to produce a signal indicating that one or more of a multiplicity of events or conditions has occurred. By way of example, in a high speed memory it is desirable to quickly sense (detect) a voltage (or current) change on any of the many word and bit address lines and to then to produce a pulse or signal to precharge various portions of the memory circuit and to perform certain housekeeping functions prior to the read-out of information from the memory or the writing of information into the memory.

A known circuit suitable to perform the desired gating function and which may be characterized as a passive WIRE-OR circuit is shown in FIGURE 1A. The circuit includes a grounded gate transistor T1, of P-conductivity type, functioning as a passive load, having its conduction path connected between a point of positive operating potential of VDD volts and an output line 12. Transistors N1 through N4, of N-conductivity type, responsive to respective input signals S1 through S4, have their conduction paths connected in parallel between line 12 and ground.

Transistors N1 through N4are normally turned-off while T1 is biased into conduction to normally maintain line 12 at, or close to, VDD volts. When any of transistors N1 through N4 is turned-on, it conducts to ground the current flowing into line 12 via T1 and also discharges capacitance CL towards ground potential. Thus, a negative-going pulse is generated.

When the signal responsive transistors are turnedoff, line 12 is recharged towards VDD volts via T1, terminating the negative-going pulse.

The circuit of FIGURE 1A has been used successfully in many applications but suffers from various problems best explained by reference to the typical output waveform in FIGURE 1 B.

1. Conduction through Ti slows down the leading (falling) edge of the negative-going pulse on the WIRE-OR line when one or more of the signal responsive transistors (N1-N4) is turned-on.

2. The signals on the WIRE-OR line cannot go all the way to ground, due to the voltage divider action between T1 and the signal responsive transistors N1-N4. The low level of the output signal is not well defined and circuits responsive to the signal may not be fully or quickly turned-on or off.

3. The trailing (rising) edge of the output pulse has a very long time constant due to the high ON impedance of T1 having to charge up the relatively large capacitance, CL, associated with line 12. In large memories, more transistors, than the four signal responsive transistors shown in FIGURE 1A by way of example, are normally connected in parallel, further increasing CL. This results in a very slow rising potential on the WIRE-OR line.

4. The dynamic power dissipation is quite high since T1 is always ON.

The problems discussed above arise primarily because of the use of a passive load (i.e. grounded gate transistor T1). This type of load is used because the input signals (e.g. changes in the voltage level on the address lines) are randomly applied to the system. Thus, it is impractical to clock the load and switch-it-off prior to the turn-on of the signal responsive transistors.

In circuits embodying the present invention, the above-discussed problems associated with the prior art circuit are eliminated or at least greatly reduced.

As in the case of the prior art circuit, the present invention is a circuit for producing on an output line a pulse in response to the turning-on of any one of a plurality of input transistors, whose conduction paths are connected in parallel to each other between the output line and a first point of operating potential (for example, ground). Whenever one of the input transistors is turned on, it tends to clamp the output line to the first potential.The circuit also has load means which connects the output line to a second point of operating potential (for example, voltage VDD) According to the invention, the impedance of the load is controllable and there is provided means responsive to the voltage on the output line and coupled to the load means for: a) maintaining the load means in a relatively high impedance state when none of the input signal responsive transistors is turned-on; b) switching the load means to a very high impedance state when an input signal responsive transistor is turned-on; and c) switching the load means to a relatively low impedance state for a given time period some time after an input signal responsive transistor is turned-on.

The illustrative embodiments of the invention next are described.

The circuit of FIGURE 2 includes insulated-gate field-effect transistors (IGFETs) N1 through Nm, of N-conductivity type, having their conduction paths connected in parallel between a WIRE-OR BUS 12 and ground potential. The gate electrode of each one of the transistors Ni, where 1 si sm, is connected to the output of a corresponding transition detector (TDi).

The input of each TDi is connected to an address line Li to which is applied an address signal Ai. The trans ton detectors may be, for example, of the type shown in FIGURES 1 or 3 of U.S. patent 4,039,858 titled TRANSITION DETECTOR, although any suit able transition detector may be used instead.

Whenever an address Ai on any one of the address lines changes from a "high" to a "low" or from a "low" to a "high" its corresponding transition detectorTDi produces a positive going pulse Si, as shown in FIGURE 3, which is applied to the gate electrode of its corresponding Ni transistor. [The signal Si is the inverse or complement of the "C" output shown in FIGURE 1 of the cited patents Thus, a positive going input pulse Si is produced per signal transition on address line Li. Each input signal responsive transistor Ni is normally turned-off, being turned-on only when its corresponding Si signal is high.

The circuit load includes IGFETs P1 and P2, of P-conductivity type, having their main conduction paths connected in parallel between line 12 and a terminal 16 to which is applied a positive operating potential of VDD volts. The ON impedance (ZPi) of P1 is substantially greater than the ON impedance (ZP2) of P2. That is, in terms of their geometries, P1 is a smaller device than P2. A circuit 18 connected between line 12 and the gate of P1 produces a signal at the gate of P1 which is the inverse or complement of the signal on line 12. In this embodiment circuit 18 is an inverter 11 connected at its input to BUS 12 and at its output to the gate of transistor P1.Inverter1 pro- duces at its output a signal which is the complement or inverse of, and which is only slightly delayed with respect to, the signal at its input. Three inverters 12, 13, and 14 are connected in cascade between the output of inverter 11 and the gate electrode of P2.

Inverters 12, 13, and 14form a circuit 20 which functions to delay the output of 11 while amplifying and inverting it prior to applying it to the gate of P2. The propagation delay through inverter 12, 13 and 14 is, in parts, a function of the sizes of the transistors forming the inverters. Inverters 11,12, 13 and 14 may be formed using transistors of complementary conductivity type, as shown in FIGURE 4A; but alternatively could be formed employing transistors of single conductivity type or be a suitable inverter.

The combination of circuits 18 and 20 functions to provide a signal at the gate electrode of P2 which is of the same polarity as the signal on line 12 but which is delayed therefrom by the combined propagation delays of 11, 12,13 and 14. Additional delays could be introduced in circuit 20 (or in circuit 18) so long as the signal at the gate of P2 is delayed with respect to, but of the same polarity as, the signal on line 12 and the signal at the gate of P1 remains the complement ofthe signal on line 12.As will be evident from the discussion below, the out-of-phase signal produced and applied to the gate electrode of P1 by means of 11 could as well be produced by any other suitable circuit and the delayed in-phase signal applied to the gate of transistor P2 by means of circuits 18 and 20 could also be produced by any other suitable circuit.

Note that a circuit performing the function of circuits 18 and 20 could be connected directly between out put line 12 and the gate of P2; where this circuit is independent of the circuit connected between line 12 and the gate of Pi.

The initial or static conditions (i.e. in the absence of an address change or a considerable time after an address change) of the circuit of FIGURE 2 are as follows: (a) The Ni transistors are turned-off; (b) the voltage, V12, on BUS 12 is high (i.e. at VDD); (c) the output, V1, of inverter1 is low (i.e. at ground); (d) therefore P1 is turned-on; (e) the output V4, of inverter 14 is high (i.e. at VDD}; and (f) P2 is turned-off.

In response to the turn-on of any one of the Ni transistors by means of an Si signal as shown in FIGURE 3, the voltage V12 on BUS 12 starts to go relatively negative, that is, toward ground. When V12 starts going relatively negative, inverter 11 amplifies and inverts the change and the output of 11 starts going from low to high. Since V1 is going positive the gate-to-source potential of P1 is reduced and its conduction is significantly reduced. Recall that P1 is, preferably, a very small device and its ON impedance is substantially greater than that of any Ni transistor. As P1 is being turned-off, its impedance increases further and the low current passing through its conduction path into line 12 is further decreased.The positive feedback loop comprising 11 and P1 ensures that after the initial drop in V12, V1 rises close to VDD, and the turn-off of P1 is accelerated. Hence, the voltage V12 on line 12 can be quickly discharged towards ground via the turnedon Ni transistor with little counteracting effect via P1 which rapidly cuts off. The result is a fast falling leading edge in waveform V12 of FIGURE 3 from time t1, tot2.

After P1 is turned-off and with P2 off, there is no low impedance path connected between lines 12 and 16. The WIRE-OR bus 12 and its associated capacitance can then be quickly discharged all the way to ground potential via a turned-on Ni transistor conducting in the common source mode as is shown in waveform V12 of FIGURE 3 for time t2 tot5.

After P1 is turned-off P2 will remain turned-off for the period of time that it takes the low-to-high output voltage transition of 11 to propogatethrough 12,13 and 14. After the propagation delay through 12,13 and 14, the output of 14 (which is complementary to the output of Ii) goes from high-to-low and P2 is turned-on. P2 is, preferably, a relatively large device and when it turns on it very quickly charges or pulls line 12 towards VDD volts, as is shown in waveform V12 of FIGURE 3 fo r time t,to ts. The initiating pulse Si is typically very narrow and normally terminates on or before the time that P2 is turned-on as shown fortime t3 tot, in FIGURE 3. The pulse delay will normally be designed to be slightly greater than the Si pulse width so that it is assumed that P2 does not turn-on until the transistor Ni responsive to Si has turned-off. As soon as V12 is driven towards VDD, the output of 11 begins to go low and transistor P1 is turned-on, further aiding in bringing V12 back towards VDD. The high-to-low output transition of 11 is propagated via inverters 12, 13 and 14 causing, after the propagation delay, an amplified positive going signal to be applied to the gate of P2, which turns P2 off completely. The voltage on line 12 is then held at the high (VDD) level only by means of transistor Pi.

Shortly after an Ni transistor is turned-on (between time t, and tut ), P1 is turned-off (at time t,) while P2 remains turned-off. The turn-off of P1 while P2 is off during the first portion of the period discussed above enables the WIRE-OR BUS 12 to be discharged quickly to ground, because the voltage drop across the conduction path of transistor Ni (operating in common source mode) is negligible. The above-explained positive4eedback gives the pulse V12 its steep leading (falling) edge. Note that while both P1 and P2 remain turned-off, the pulse reaches (or comes down to) 0 volts for a predetermined period (i.e. time t, tot5) which corresponds to the propagation delays through 12, 13, and 14.This assures that the low or zero level of the output pulse is well defined. Also note that because P1 and P2 are turned-off during most of the time that a negativegoing pulse is being generated, little power is being dissipated. After the delay (at time t5) P2 turns-on and, due to its very low ON impedance, quickly charges up the WIRE-OR BUS towards VDD volts, so that shortly thereafter (at time tb), P1 again turns on.

Because P2 is turned-on after the turn-off of the Ni transistor and the initiation of the precharge cycle, little average power is dissipated in the circuit. This is true, even though substantial power is dissipated when P2 is ON and CL is being recharged, because the recharging of CL occurs only for a short time. For example, where the pulse width is 6 to 10 nanoseconds, P2 will be ON also for 6 to 10 nanoseconds. Therefore, the circuit has a very low average power dissipation, and its output response is extremely fast. Where the input signals Si are applied in such a sequence that an Ni transistor is turned-on during the time that P2 is turned-on (from time t5 to t, in FIGURE 3) the power dissipation in the system increases. But, the time period during which P2 is turned-on is very very short.Therefore, the average power dissipation remains low.

In order to reduce the time that P2 is ON, the delay introduced by 12, 13 and 14 does not need to be symmetrical (i.e., the same for both high-to-low and low-to-high transitions in signals generated on line 12). As illustrated in FIGURES 4A and 4B, inverters 12, 13 and 14, which form delay network 20, are detailed using complementary IGFETs. The P-conductivity type transistors (Pl2 and Pl4) of inverters 12 and 14 are made larger than their corresponding N-conductivity type transistors (Nl2 and Nl4), and Nl3 of inverter 13 is made large in comparison to Pl3.As a result the delay (TDF) in responseto highto-low (negative-going) transition on line 12 is greater than the delay (TDB) in response to a low-to-high (positive going) transition on line 12.

The invention has been illustrated using two active (dynamically driven) transistors (P1 and P2). But, instead, the circuit could include a single load transistor (or other controllable impedance means) whose impedance or conductance is controlled by the voltage level on line 12. When all the inputs (Al Am) are low (defining a state condition) the combination of P2 and P1 functions as a high impedance load connected between line 12 and VDD. The impedance of the load (Pi) during the static condition is designed to compensate for leakage currents (from line 12) to ground and to prevent line 12 from floating. The load impedance can, therefore, be very high. When an Ni transistor is turned-on, an output pulse is produced and P1 is turned-off (P2 already is off).As both P1 and P2 are off, they function as an extremely high impedance load. Following the generation of the output pulse of desired pulse width, P2 is turned-on for a short period of time (and P1 is also turned-on) to terminate the output pulse and to provide a sharp trailing edge (fast return to VDD). The combination of P1 and P2 then functions as a low ON impedance circuit designed to restore quickly the output line to its original (static) condition, when P2 is turned-off and P1 is again turned-on.

This is in sharp contrast to the Prior Art circuit where: a) the leading edge is restricted from falling sharply; b) the final level of the pulse cannot reach the supply rail; and c) the trailing edge cannot return quickly to its original level.

By dynamically driving the load with a signal generated on the output line of the circuit rather than using a passive pull up transistor (or a resistor) as in the Prior Art, extremely fast operation with low average power dissipation is achieved.

Thus, in circuits embodying the invention, although the input signals (e.g. changes on address lines) are randomly applied to the system, an output pulse or signal is produced quickly after the occurrence of a change on an address line. The pulse or signal is well defined (i.e. goes from a full "low" to a full "high", or vice versa), has a sharp leading edge to define the start of the precharge and housekeeping function, and has a sharp trailing edge to terminate the precharge and housekeeping functions and to initiate a read-out or write cycle.

In the circuit of FIGURE 5 three circuits 2a, 2b, and 2c (each of which is similar to the circuit of FIGURE 2) have their respective outputs V12a, V12b, and V12c connected via lines 12a, 12b and 1 2c to the gate electrodes of respective input transistors P41, P42 and P43. The number of address inputs (Ala to AXa, Alb to ANb, Al to AXc) applied to circuits 2a, 2b and 2c need not be the same. For example, in the circuit of FIGURE 2 a multiplicity (m) of input signals responsive transistors Ni are shown connected at node 12.

In order to minimize the capacitance associated with node 12 and to obtain higher speed of operation it may be advantageous to limit the number of input signals in each subcircuit (2a, 2b, 2c). In any event, the outputs of two or more circuits of the type shown in FIGURE 2 may be combined or gated in common as shown in FIGURE 5. The WIRE-ON circuit 40 in FIG. 5 is the complementary version of the circuit of FIGURE 2. The signal responsive transistors are transistors P4i of P-conductivity type having their conduction paths connected in parallel between VDD volts and a WIRE-OR line 42. The dynamic load includes a transistor N41 (corresponding to P1 of FIGURE 2) and a transistor N42 (corresponding to P2 in FIGURE 2) having their conduction paths connected in parallel between line 42 and ground. An inverter 141 (corresponding to 11) is connected at its input to line 42 and at its output to the gate of N41.

Three inverters 142, 143 and 144 (corresponding to 12, 13 and 14) are connected in cascade between the output of 141 and the gate electrode of N42.

The circuit 40 of FIGURE 5 functions in a com plementary but otherwise similar manner to the cir cuit of FIGURE 2 and is not described in detail. Thus, when a negative-going pulse is produced on lines 1 2a, 1 2b or 1 2c a positive going output pulse is produced on output line 42. The pulse produced on line 42 may be directly connected to various portions of a subsequent circuit (not shown), or connected via a buffer to subsequent circuits.

It is evident from the circuit of FIGURE 5 that the input signals can be combined in many different ways in an effort to optimize the system response.

The circuit of FIGURE 5 also demonstrates that circuits embodying the invention can be combined to perform combination logic.

A circuit embodying the invention, shown in FIG URE 6, includes insulated-gate field effect transistors (IGFETs) Nli through Nlm, of N conductivity type, having their conduction paths connected in parallel between a WIRE-OR BUS 12 and a point of reference potential shown as ground. The gate electrode of each one of the transistors Nli, where l si sm, is con- nected to the output of a corresponding transition detector (TDi). The input of each TDi is connected to an address line Li to which is applied an address signal Ai. The transition detectors may be, for example, of the type shown in FIGURES 1 or 3 of U.S.

patent 4,039,858 titled TRANSITION DETECTOR; although any other suitable transition detector may be used instead. Whenever an address Ai on any one of the address lines changes from a "high" to a "low" or from a "low" to a "high", its corresponding transition detectorTDi produces a positive going pulse Si, as shown in FIGURE 3 which is applied to the gate electrode of its corresponding Nli transistor.

[ The signal Si is the inverse or complement of the "C" output shown in FIGURE 1 of the cited patent. ] Thus, a positive going input pulse Si is produced per signal transition on address line Li. Each input signal responsive transistor Nli is, therefore, normally turned-off, being turned-on only when its corresponding Si signal is high.

The circuit load includes IGFETs P3 and P5, of P conductivity type, having their main conduction paths connected in parallel between line 12 and a terminal 16 to which is applied a positive operating potential of VDD volts. The ON impedance (ZP3) of P3 is designed to be substantially greater than the ON impedance (ZP5) of P5. This is readily achieved by making P3 a smaller device than P5. The value of ZP3, when P3 is ON, is designed to allow the passage of sufficient current between terminal 16 and line 12 to supply the leakage current drawn by the Nli transistor connected to line 12 in the static condition, i.e.

when none of the Nli transistors is conducting. This maintains the voltage, V12, on line 12 at, or close to, VDDvolts. A circuit 18 connected between line 12 and the gate of P 1 produces a signal at the gate of P1 which is the complement of the signal on line 12. In this embodiment the circuit is a single inverter 11, preferably of the complementary conductivity type, connected at its input to BUS 12 and at its output to the gate of transistor P1 and to the input of an inverter 12. Inverter 11 produces at its output a signal which is the complement or inverse of the signal at its input and which is only slightly delayed with respect to the signal at its input.

Inverter 12 is comprised, or formed, of two transistors (N2 and P2) of complementary conductivity type having their conduction paths connected in series between VDD and ground. The gate electrodes of P2 and N2 are connected in common and define the input of 12. The drains of N2 and P2 are connected in common at node 22 which defines the output of 12, and to which are connected the gate and drain electrodes of a transistor P4 and the gate electrode of P5 In addition to amplifying and inverting the signals at their inputs, inverters 11 and 12 function as a delay network and provide enough phase shift at high frequencies to make the loop formed by it, 12, P4, P5 and Nli unstable.That is, the signal on line 12 is delayed through 11 and 12 prior to being applied to the gate and drain of P4 and to the gate of P5. 12 functions to delay, amplify, and invert the output of 11 prior to generating a signal at node 22. The propagation delay through inverter 12, is, in part, a function of the sizes of the transistors forming the inverter. Inverter1 like inverter 12, may be formed of transistors of complementary conductivity type.

However, either, or both inverters, could be formed employing transistors of single conductivity type.

The source electrodes of transistors P4 and P5 are connected to terminal 16, their gates and the drains of P4 are connected in common to node 22, and the drain of transistor P5 is connected to output line 12.

As detailed below, P4 and P5 function as a current mirror whose output current, 15, is controlled by the source-to-drain current, 12, through N2.

The initial or static conditions of the circuit of FIG URE 6 are as follows: 1. The Ni transistors are turned-off; 2. Consequently, the voltage, V12, on BUS 12 is high (i.e. at Odd); 3. Therefore, the output V1 of inverter 11 is low (i.e. at ground potential); 4. Therefore, P3 is turnedon and provides a conduction path between node 16 and output BUS 12. But, recall that ZP3 is a relatively high impedance; 5. Transistor N2 is turned-off; and 6. Transistor P2 is turned-on applying VDD volts to the gates of transistors P4 and P5 thereby maintaining transistors P4 and P5 turned-off.

In response to the turn-on of any one of the Nli transistors by means of an Si signal as shown in FIGURE 7 the voltage on line 12 begins to go negative. Each one of the signal responsive transistors (Nli) has a lower ON impedance than P5 and, of course, P3. Therefore, as soon as an Nli transistor is turned-on, the output of V12 can go, and does go, from the high level (VDD) towards the low level (ground). As soon as V12 starts going negative, inverter 11 amplifies and inverts the negative going transition and the output (V1) of 11 goes from low to high. Since V1 is going positive, the gate-to-source potential of P3 is reduced and the already high source-to-drain impedance of P3 is further increased. V1 quickly reaches VDD volts at which time P3 is completely turned-off. With P5 off and P3 turned-off, any Nli transistor can discharge node 12 all the way to ground potential without opposition or contention from any load device, as shown for time t1 tot, in FIGURE 7. Therefore, as shown in FIGURE 7 for time t1 to t,, the signal on line 12 is very quickly brought from VDD to, or close to, zero volts. This is done with very little power dissipation since P3 and P5 are turned-off.

The low to high (VDD) signal transition generated at the output of 11 is applied to the input of 12 turningoff P2 and turning-off N2. The voltage applied to the gate of N2 causes a current 12 to flow through its source-to-drain path. When V1 is at or close to VDD, P2 is turned-off and the current 12 through N2 is equal to the current 14 drawn through the sourceto-drain path of transistor P4. The current 14 flowing through the source-drain path of P4 causes a certain gate-to-source potential (VGS4) to be developed across the source and gate of P4. This gate-to-source potential is identically applied across the gate and source of transistor P5.Accordingly, the circuit P4-PS operates as a "current mirror", that is, since the VGS across P5 is the same as the VGS across P4, the current 15 through the source-to-drain path of P5 is directly proportional to 14. As is well known the degree of proportionality (k) is determined by the relative sizes of transistors P4 and P5. In this embodiment P5 was made 10 times the size of P4 whereby 15 is 10 times 14. However, the minimum effective impedance of P5 ON is greater than the minimum effective impedance of any Nli transistor.The ratio of the impedance of P5-ON to the impedance of any turned-on Nli transistor is such that if any Nli transistor is on while P5 is on, the maximum voltage on line 12 is less than the threshold voltage drop (VT) of a transistor of N-conductivity type. Hence so long as any Nli transistor is ON, V12 remains below VT volts as illustrated for time t2 to 5 in FIGURE 7. Also, V1 remains at VDD, maintaining P2-off and N2 conducting a current 12 equal to 14 which produces a current 15 into line 12.

The time delay controlling the turn-on of P5 follow- ing the turn-on of an Nli transistor may be adjusted by relative sizing of the transistors forming 11 and 12 or by adding an even number of inverters or other delay devices such as an RC time constant, between the output of 11 and the input of 12.

Following the turn-off of all the Nli transistors, current source transistor P5 keeps on supplying a constant current 15 to the output line 12. As a result the output is quickly brought back to VDD volts via the constant current linearly charging the output capacitance CL, as shown for time t5 to t6 in FIGURE 7. As soon as V12 comes within a threshold voltage drop of VDD, the output of 11 switches from high to low turning on P3. Both P3 and P5 then contribute to restoring the potential on line 12 to VDD. As the highto-low transition at the output of 11 is amplified and inverted by 12 (with the propagation delay of 12) N2 is turned-off and P2 is turned-on.This drives the gates of the current mirror transistors P4 and P5 to VDD, turning off the current mirror, that is, terminating the relatively constant current 15. By this time V12 is at, or very close to, VDD volts and has thus been restored to its original (initial) condition.

When P5 and an Nli transistor are conducting, the potential on line 12 is a function of how much current P5 is supplying to the line and how much current the Nli transistor is sinking from the line.

Assuming inverter 11 to be a complementary inverter of the type shown for 12, it is extremely important that V12 be kept below the VT of the N channel transistors to prevent the circuit from oscillating. This is achieved in the circuit of FIGURE 6 by making 15 a known ratio of 14, the current 14 being directly proportional to the current 12 through N2. The value of 12 is a function of the potential applied between the gate and source of N2. Normally, when N2 is conducting, its gate electrode is driven to VDD (turning P2 OFF) while its source electrode is grounded. The VGS of N2 is then approximately equal to VDD and its source-to-drain voltage VSD is less than 1 volt. Note, that when an Nli transistor is turned-on approximately VDD volts are applied to its gate while its source electrode is grounded.Consequently, the ON condition of N2 is very similar to the ON condition of a turned-on Nli transistor. Note also, that N2 and the Nli transistors are of the same conductivity type.

Thus, where N2 and the Ni transistors are formed as part of an integrated circuit, or under similar processing conditions, the variations in N2 and in the Nli transistors track each other as a function of time, temperature, and voltage. Consequently, very stable operation can be, and is, achieved in the circuit of FIGURE 6.

Thus, in circuits embodying the invention a pulse can be generated having relatively sharp leading and trailing edges, and also having a very stable level between edges.

The load portion of the circuit of FIGURE 6 may be modified as shown in FIGURE 8. The load device P3 is part of an inverter 13 which includes a transistor, N3, of N-conductivity type whose drain is connected to line 12 whose source electrode is returned to ground and whose gate is connected to the gate of P3. The input (gates of P3 and N3) of inverter 13 is connected to the output of a two input logic gate G1.

Depending on the type of function to be performed G1 may be a NAND gate or a NOR gate.

The output line is connected to one input of G1 and a chip select signal is applied to the other input of G1. If G1 is a NAND gate, when the chip select is "low", G1 is inhibited and the output of G1 is clamped to VDD. When the chip select is "high", G1 functions as an inverter connected between line 12 and the input of 13. When V12 is high the output of G1 is low P3 is turned-on and N3 is turned-off. When V12 goes low, the output of G1 goes high, P3 gets turned-off while N3 gets turned-on further aiding in the discharge of line 12 to ground.

The relatively constant current source and mirror arrangement may be controlled as shown in FIGURE 8. Note that the precharge pulse produced on WIRE-OR line 12 is applied to the sense circuitry and to the memory portion of the memory array. An inverter 17 responsive to the chip select signal is connected at its output to the gate electrodes of transistors P6 and N6 of P and N conductivity type, respectively. The conduction path of P6 is connected in series with the conduction path of a transistor P1A, of P conductivity type, between terminals 16 and node 26. The conduction paths of transistors N6 and a transistor N1A, of N conductivity type, are connected in parallel between node 26 and ground.

The gate electrodes of P1A and N1A are connected to line 12.

When the chip select is "low" the output of 17 is high and node 26 is driven "low" maintaining P2 ON, and N2 OFF, and the current mirror and source non conducting. When the chip select is "high", the out put of 17 is low turning on P6 and turning off N6. P1A and N1Athen function as an inverter responsive to the signal on line i2andtheoutputofthe P1A, N1A inverter then drives the input of 12 in a similar man ner to that described for 11 in FIGURE 6.

Claims (19)

1. A circuit for generating on an output line a well defined pulse having relatively sharp leading and trailing edges in response to turning on any one of a plurality of input transistors wherein the conduction paths of said input transistors are connected in parallel between said output line and a first point of operating potential so that said input transistors when turned on tend to clamp said output line to said first potential load means connects said output line to a second point of operating potential the impedance of said load means being controllable; and there are means responsive to the voltage on said output line and coupled to said load means for: (a) maintaining the impedance of said load means at a first, high value when all of said signal responsive transistors are NON-conductive; 1 (b) switching the impedance of said load means to a second value higher than said first value for a given predetermined period of time when any one of said signal responsive transistors becomes conductive; and i (c) switching the impedance of said load means to a value lower than said first value to enable substantial conduction therethrough for a given time following said given predetermined period of time.

2. The circuit as claimed in claim 1 wherein: said controllable impedance load means includes first and second load transistors, each having a conduction path and a control electrode; and the conduction paths of said first and second load transistors are connected in parallel between said output line and said second point of operating potential.

3. The circuit as claimed in claim 2 wherein the conduction path of said first load transistor, when conductive, has an impedance higher than that of said second load transistor.

4. The circuit as claimed in claim 2 or 3 wherein: said means responsive to the voltage on said output line coupled to said load means includes: (a) a first means coupled between said output line and the control electrode of said first load transistor for applying to said control electrode thereof a signal which is out-of-phase with the signal on said output line; and (b) a second means responsive to the signal on said output line coupled between said output line and said control electrode of said second load transistor for applying to said control electrode thereof a signal which is of the same polarity as, and delayed with respect to, the signal on said output line.

5. The circuit as claimed in claim 4 wherein said first means includes an odd number of inverters connected in cascade between said output line and the control electrode of said first transistor, and wherein said second means includes an additional odd number of inverters connected in cascade between the control electrode of said first transistor and the control electrode of said second transistor.

6. The circuit as claimed in any one of claims 1-5, wherein each of said signal-responsive transistors is turned-on by a relatively narrow pulse.

7. The circuit as claimed in claim 1 and wherein: said load means comprises a controllable impedance means and a controllable relatively constant current source connected in parallel with said controllable impedance means between said line and a second point of potential; said means responsive to the voltage on said line includes: means for switching said controllable impedance means to said second value when the voltage on said line is being clamped to said first point of potential; and meansforturningon said currentsourcea given time delay afterthevoltage on said line is clamped to said first point of potential, in orderto supplyto said line current in a direction tending to restore voltage on said line to the level at said second point of potential.

8. The circuit as claimed in claim 7, wherein said meansforswitching said controllable impedance means includes a first inverting means (11) and wherein said means for turning on said current source includes second inverting means (12) connected between the output of said first inverting means and said current source.

9. The circuit as claimed in claim 7 or 8 wherein: said controllable impedance means includes a first transistor having a conduction path connected between said line and said second point of potential; and said relatively constant current source includes second and third, transistors connected as a current mirror with the conduction path of said second trans istorconnected between said line and said second point of potential the conduction path of said third transistor is connected between the said second point of potential and said means forturning on the current source.

10. The circuit as claimed in claim 9, when appended to claim 8, wherein the second inverting means comprises a fourth transistor, the conduction path of which is connected between the said first part of potential and the conduction path ofthethird transistor.

11. The circuit as claimed in claim 10 wherein said first, second and third transistors are of one conductivity type, and wherein said plurality of input transistors and said fourth transistor are of second conductivity type.

12. The circuit as claimed in claim 9, 10 or 11 wherein the impedance of said first transistor when conductive is significantly greater than the impedance of said second transistor when conductive and wherein the impedance of said second transistor when conductive is greater than the impedance of each one of the transistors of said first plurality of transistors when conductive.

13. The circuit as claimed in any preceding claim, wherein transistors of said plurality of input transistors are coupled via respective transition detectors (TD1, TD2, etc) to input lines (awl, A2 etc), and wherein each of said transition detectors turns-on a respective input transistor for a short duration each time there is a change in level of the signal on its associated input line.

14. A memory array in which a circuit in accordance with 13 responds to randomly generated address signals on said input lines by producing on said output line a precharge pulse each time one of said address signals changes state.

15. A pulse generating circuit substantially as hereinbefore described with reference to Figures 2 and 3 optionally as modified by Figure 4A and/or Figure 4B.

16. A pulse generating circuit substantially as hereinbefore described with reference to Figure 5.

17. A pulse generating circuit substantially as hereinbefore described with reference to Figures 6 and 7.

18. A pulse generating circuit substantially as hereinbefore described with reference to Figure 8.

19. A memory array comprising a pulse generating circuit according to any one of claims 1 to 13 and 15 to 18.