FR2499788A1 - PULSE GENERATOR CIRCUIT USING POWER SOURCE AND MEMORY ASSEMBLY USING SUCH CIRCUIT - Google Patents

Abstract

THE INVENTION RELATES TO A PULSE GENERATOR CIRCUIT USING A CURRENT SOURCE. A P1, P2 CHARGING MEDIA IS CONNECTED BETWEEN AN OUTPUT LINE 12 AND A POTENTIAL POINT, WITH A SECOND POTENTIAL V VALUE. WHEN ANY OF THE NORMALLY NON-CONDUCTIVE NM TRANSISTORS N1, WHICH ARE CONNECTED BETWEEN A FIRST OPERATING POTENTIAL POINT (EARTH) AND THE OUTPUT LINE IS VALID, THE POTENTIAL OF THE OUTPUT LINE GOES TO A FIRST POTENTIAL VALUE. A MEDIUM 18, 20 CONTROLS THE IMPEDANCE OF THE LOAD MEDIA BY APPLYING A NON-CONDUCTIVE SIGNAL TO THE FIRST NORMALLY CONDUCTIVE TRANSISTOR P1 BELONGING TO THE LOAD MEDIA, THEN A DELAYED CONDUCTION SIGNAL AT THE SECOND NORMALLY CONDUCTIVE TRANSISTOR P2 AT THE NORMALLY CONDUCTIVE MOTOR P2 CHARGE, THEN A CONDUCTION SIGNAL TO THE FIRST TRANSISTOR P1, AS WELL AS A DELAYED NO CONDUCTION SIGNAL TO THE SECOND TRANSISTOR.

Description

The present invention relates to a circuit for producing a

  well-defined narrow impulse having flanks

anterior and posterior stiff.

  In many applications, it is necessary to produce a signal indicating that one or more events or conditions have occurred among several possible ones. For example, in a fast memory, it is desirable to quickly pick up (detect) a change in voltage (or current) on any of the many word and bit address lines, and then produce a pulse or a signal for preloading various parts of the memory circuit and performing certain layout functions

  before reading or writing information into memory.

  A known circuit making it possible to perform the desired function of logical encapsulation, this circuit being able to be characterized

  as a passive OR CABLE circuit, is shown in FIG.

  The circuit comprises a grounded tripping transistor T 1, of conductivity type P, operating in passive load, whose conduction path connects a positive operating potential point, a voltage VDD, to an output line 12 Transistors N1 to N4, of conductivity type N, respectively corresponding to input signals S1 to S4, are such that their conduction paths are connected in parallel between line 12 and earth. Transistors N1 to N4 are normally non-conductive, while transistor T1 is conduction biased so as to normally maintain line 12 at or near a voltage VDD. When any of the transistors N1 to N4 become non-conductive, it conducts the current passing through line 12 via Tl and further discharges capacitance CL towards the ground potential. Thus, a negatively oriented pulse is produced. When the transistors responding to signals are made non-conductive, the line 12 is recharged to the voltage VDD via the transistor T1, which terminates the negatively oriented pulse. The circuit of FIG. 1A has been used successfully

  in many applications, but it suffers from various

  which will be better explained in relation to the waveform

typical output of Figure LB.

  1. Conduction Through transistor T1 slows down the forward (downward) flank of the negatively oriented pulse on the OR CABLE line when one or more of the transistors

  responding to the signals (Ni to N4) is made conductive.

  2. The signal present on the OR CABLE line can not go completely to the earth potential, because of the voltage divider effect existing between the transistor T1 and the transistors N1 to N4. The low level of the output signal is not well defined and circuits responding to signals may not be

  completely or rapidly rendered conductive or non-conductive.

  3. The posterior (upright) side of the output pulse has a very long time constant due to the high impedance, in conduction, of transistor T1, which has to charge up to the relatively large capacitance CL associated with line 12. In large memories, there are a larger number of transistors, than the four transistors responding to the signals shown in FIG ILA by way of example, which are normally connected in parallel, this further increasing the capacitance CL. This results in a very slow increase in potential on the OR line

CABLE.

  4. Dynamic power dissipation is extremely

  high, since transistor T1 is still conducting.

  The problems discussed above have as their main origin the use of a passive load (i.e. tripping transistor T1 grounded). This type of load is used because the input signals (e.g., variations in the voltage level on the address lines) are randomly applied to the system. Thus, it is impractical to put the load clockwise and switch it to non-conduction before

  transition to the conductive state of the transistors responding to the signals.

  In the circuits constituting embodiments of the invention, the problems discussed above which are associated with the prior art circuit are eliminated or, for the

less, strongly attenuated.

  As for the circuit of the prior art, the invention relates to a circuit for producing on an output line a pulse in response to the transition to the conducting state of any one of several input transistors, whose the conduction paths are connected in parallel with each other

  between the exit line and a first potential point of

  (eg earth). Whenever one of the input transistors goes to the conductive state, it tends to lock the output line to the first potential. This circuit also has a charging means which connects the output line to a second point

  operating potential (for example the voltage V DD).

  According to the invention, the impedance of the load can be adjusted and there is provided a means which responds to the potential present on the output line and which is coupled to the charging means so as to (a) maintain the charging means in a relatively high impedance state when none of the transistors responding to input signals are in the conductive state; (b) passing the load means into a state of very high impedance when a transistor responsive to the input signals is turned on; and (c) passing the charging means into a relatively low impedance state

  for a given period of time some time after a transistor responds

  the input signals has been put in the conductive state.

  The following description, designed as an illustration

  of the invention, aims to give a better understanding of its features and advantages; it is based on the accompanying drawings, among which: - Figure lA is a simplified diagram of a circuit of the prior art; FIG. 1B shows waveform diagrams of an output signal typical of the circuit of FIG. 1A and a desired output signal; FIGS. 2, 5, 6 and 8 are simplified diagrams of circuits constituting embodiments of the invention; FIG. 3 shows waveform diagrams of a signal applied to the circuit of FIG. 2 and of an output signal produced by the circuit of FIG. 2, as well as graphs.

  illustrating the sequence of conduction and non-conduction

  charging sistors of the circuit of Figure 2; FIG. 4A is a simplified diagram of a delay network that can conveniently be used in the circuit of FIG. 3; FIG. 4B is a diagram of ion forms associated with the circuit of FIG. 4A; and - Figure 7 shows waveform diagrams

  of signals cited in relation to the circuit of FIG.

  It is noted that in the accompanying drawings, characters

  The same reference numbers designate identical components.

  The circuit of FIG. 1A, representative of the prior art, has already been described in connection with the waveforms of FIG.

Figure 1B.

  The circuit of FIG. 2 comprises insulated-gate field-effect transistors Ni to Nm, of conductivity type N, whose conduction paths are connected in parallel between

  a common line OR CABLE 12 and the potential of the earth. The elec-

  gate trode of each of the transistors Ni (it is noted that i denotes the rank of the transistor, or an associated device, and varies from 1 to m) is connected to the output of a corresponding transition detector TDi. The input of each detector TDi is connected to a line of address Li to which is applied an address signal Ai. Transition detectors may be, for example, of the type shown in Figures 1 and 3 of U.S. Patent No. 4,039,858 although any suitable transition detector may be used as well. Whenever an address Ai present on any of the address lines goes from a "high" level to a "low" level, or from a "low" level to a "high" level, its corresponding transition detector TDi produces a positively oriented pulse Si, as can be seen in FIG. 3, which is applied to the gate electrode of its transistor Ni

  corresponding. (Note that the signal Si is the opposite, or

  the output signal "C" appearing in FIG. 1 of the cited patent. Thus, a positively oriented input pulse Si is produced at each signal transition occurring on a Li address line. Each transistor Ni responds to input signals.

  is normally in the non-conductive state, and is not made conductive

  only when its corresponding signal Si is of high level.

  The load of the circuit comprises insulated gate field effect transistors P 1 and P 2 of conductivity type P, the main conduction paths of which are connected in parallel between line 12 and a terminal 16, to which a potential of positive operation of a VDD voltage. The impedance in conduction (denoted ZPI) of the transistor F1 is substantially greater

  higher than the conduction impedance (denoted ZP2) of the transistor P2.

  Thus, in geometrical terms, the transistor P1 is a device smaller than the transistor P2. A circuit 18 connected between the line 12 and the gate of the transistor P1 produced on the gate of Pl

  a signal which is the opposite, or complement, of the signal of line 12.

  In this embodiment, the circuit 18 is an invertor

  nected by its input to the common line 12 and, by its output, to the gate of the transistor Pl. The inverter It produces at its output a signal which is the complement, or inverse, of the signal present on its input,

  and which is slightly delayed with respect to this input signal.

  Three inverters I2, I3 and I4 are connected in cascade between the

  output of the inverter II and the gate electrode of the transistor P2.

  Inverters I2, I3 and I4 form a circuit 20 whose function is to delay the output signal of Il while amplifying and inverting it before applying it to the gate of transistor P2. The propagation delay d0 to the inverters I2, I3 and I4 is partly

  function of the dimensions of the transistors constituting the inverters.

  Inverters I1, I3 and I4 may be formed by transistors having complementary conductivity types, as shown in FIG. 4, but they may also be formed by transistors of a single conductivity type or

  well be any suitable inverters.

  The circuits 18 and 20 have the function, in combination, of producing a signal to the gate electrode of P2 which has the same polarity as the signal present on the line 12 but which is delayed with respect to it by the delays. combined propagation of inverters Il, I2, I3 and I4. It is possible to introduce additional delays in the circuit 20 (or in the circuit 18) insofar as the signal present on the gate of the transistor P2 is delayed with respect to the signal present on the line 12 and has the same polarity as it, while the signal present on the grid of Pl remains the complement of the signal present on the line 12. As will become clearer in the discussion given below, the phase-shifted signal that is produced and applied to the gate electrode of the transistor P1 by the inverter It could equally well be produced by any other suitable circuit, and likewise the phase-delayed signal which is applied to the gate of the transistor P2 by the circuits 18 and 20 could be produced. by any other suitable circuit. Note that a circuit performing the function of the circuits 18 and 20 could be directly connected between the output line 12 'and the gate of the transistor P2, this circuit then being independent of the circuit connected between the line 12 and the gate of the

transistor Pl.

  The initial conditions, or static conditions (that is, in the absence of an address change or a long time after an address change), of the circuit of FIG. 2 are as follows: (a) the Ni transistors are in the non-conductive state; (b) the voltage V12 present on the common line 12 is high (i.e., is at the VDD level); (c) the output signal VI of the inverter I1 is low (i.e., is at ground level); (d) thus, the transistor P1 is in the conductive state; (e) the output signal V4 of the inverter I4 is high (i.e., is at the VDD level); and (f) the transistor P2 is in

the non-conductive state.

  In response to the conduction of any of the Ni transistors by a signal Si as shown in Figure 3, the voltage V12 of the common line 12 begins to go in the direction

  relatively negative, that is to say towards the potential of the earth.

  When V12 begins to go in the relatively negative direction, the inverter II amplifies and reverses the change, and the output signal of the inverter begins to go from the low level to the high level. Since the potential VI moves in the positive direction, the gate-source voltage of the transistor P1 decreases and its conduction undergoes a significant reduction. It is recalled that the transistor P1 is preferably a very small device and that its impedance in conduction

  is substantially larger than that of any of the

  249978i sistors Ni. When the transistor P1 goes into the non-conductive state, its impedance increases further, and the small current flowing through its conduction path in the line 12 decreases further. The positive feedback loop comprising the inverter II and the transistor P 1 ensures that, after the initial voltage drop of V12, the potential V1 rises to the vicinity of V DD and the transition to the non-state.

  Trans transistor driver accelerates. Thus, the voltage V12 pre-

  feel on the line 12 can quickly discharge to the ground via the transistor Ni become conductive, without much effect

  contrary by the transistor P1, which becomes rapidly non-conductive

  tor. The result is expressed by the anterior flank with rapid descent

  of the waveform V12 of Figure 3, between times t1 and t2.

  After the transistor PI has become non-conducting and while the transistor P2 is non-conductive, there is no path of low impedance between the lines 12 and 16. The line

  OR CABLE 12 and its associated capacity can then rapidly

  to be fully discharged to the earth potential via a turned-on Ni transistor that operates in the common source mode, as shown in FIG.

  waveform V12 of FIG. 3 between times t2 to t5.

  After the transistor P1 has become non-conductive,

  the transistor P2 remains non-conducting for the duration

  Inverter output voltage output low-high It needs to propagate in 12, 13 and 14. After the propagation delay in I2, 13 and 14, the output signal of I4 (which is complementary to the signal of output of Il) goes from high to low and

  the transistor P2 becomes conductive. The transistor P2 is preferably

  a relatively large device and, when it becomes

  it is very fast, that is to say very quickly pulls the line 12 towards the potential VDD, as this is shown in

  the waveform V12 of Figure 3 between times t5 to t6.

  The initiating pulse Si is typically very narrow and normally terminates at the instant or before the moment when the transistor P2 has been made non-conductive, as indicated for the duration from t3 to t4 in FIG. The delay of the pulse is normally designed to be slightly larger than the width of the pulse Si, so that it is assumed that the transistor P2 does not become conductive until the transistor Ni responding to Si has become non driver. As soon as V12 has been driven to VDD, the output signal of the inverter It starts to go low and the transistor P1 becomes conductive, which again helps to bring V12 back to VDD. The up-down output transition of the inverter It propagates in the inverters I2, I3 and I4 and has the effect, after the propagation delay, of the application of a positively oriented signal amplified to the gate of the transistor P2, which renders the transistor P2 completely non-conductive. The voltage present on the line 12 is then maintained at the high level (VDD) by the only means of the transistor P1. In short, after a transistor Ni has been turned on (between the instant t0 and t1), the transistor P1 becomes non-conductive (at time t2) while transistor P2 remains non-conductive. The nonconduction of Pl, while P2 is no

  during the first part of the period examined above.

  above, allows fast discharge of the common line OR CABLE 12 to the ground, because the voltage drop across the conduction path of the transistor Ni (operating in common source mode) is negligible. The positive reaction explained above gives the V12 pulse its steep leading edge (amount). Note that, while the two transistors P1 and P2 remain in the non-conductive state, the pulse reaches (or descends to) the zero voltage in a predetermined time (i.e. between times t2 and t5), which corresponds to the propagation delays introduced by 12, I3 and I4. This ensures that the low, or zero, level of the output pulse is well defined. It is also noted that, since the transistors P1 and P2 are non-conductive for most of the time during which a negative impulse

  oriented is being created, there is little

  Pee. After the delay (at time t 5), the transistor P2 becomes conductive and, because of its very low impedance in conduction, it quickly charges the common OR CABLE line towards the voltage VDD 'so that soon after (at moment t6), the transistor

Pl becomes a driver again.

  Since the transistor P2 becomes conductive after the arrival of the transistor Ni in the non-conductive state and the start of the precharge cycle, the average power dissipated in the circuit is low. This is true even if significant power is dissipated when the transistor P2 is conducting and the capacitance CL recharges, because the recharge of the capacitor CL only occurs for a short time. For example, when the pulse width is 6 to 10 ns, transistor P2 is also conductive for 6 to 10 ns. Thus, the circuit has a very low dissipation of

  average power, and its output response is extremely fast.

  If the input signals Si are applied at a rate such that a transistor Ni becomes conductive while the transistor P2 is in the conducting state (between times t5 and t7 in FIG. 3), the power dissipation in the system increases. But the duration

  during which the transistor P2 is conductive is very very brief.

  Thus, the average power dissipation remains low.

  To reduce the time during which the transistor F2 is conductive, it is not necessary that the delay introduced by the inverters I2, I3 and 14 be symmetrical (ie the same for the high-to-low transition). and the low-to-high transition in the signals produced on line 12). As illustrated in FIGS. 4A and 4B, the inverters I2, I3 and 14, which form the delay grating 20, consist of complementary insulated gate field effect transistors. Transistors of conductivity type P (PI2 and P14) of inverters I2 and 14 are

  larger than their N-type transistors corresponding to

  (NI2 and NI4), and the transistor NI3 of the inverter I3 is large compared with P13. As a result, the delay (TDF) produced in response to the up-down (negatively oriented) transition on line 12 is larger than the delay (TDB) produced in response to

  a low-to-high transition (positively oriented) on line 12.

  The invention has been illustrated using two active (dynamically excited) transistors (PI and P2). But it would also be possible for the circuit to include a single load transistor (or other adjustable impedance means) whose impedance or conductance would be controlled by the voltage level of the line 12. When all the input signals (AI to Am) are low level (defining a static state), the combination of transistors P2 and P1 plays the role of a high impedance load connected between the line 12 and the potential VDD. During the static state, the load impedance (P1) is intended to compensate for leakage currents (from line 12) to earth and to prevent the potential of line 12 from floating. The load impedance can therefore be very high. When a transistor Ni becomes conductive, an output pulse is generated and the transistor P1 becomes non-conductive (the transistor P2 is already non-conductive). When the transistors P1 and P2 are both non-conductive, they play the role of an extremely high impedance load. As a result of producing the output pulse of desired width, the transistor P2 becomes

  driver for a short time (and the transistor Pi also becomes

  driver) to terminate the output pulse and

  to produce a stiff posterior flank (fast return to the VDD voltage).

  The combination of transistors P1 and P2 then plays the role of a

  low impedance circuit in conduction designed to bring back fast-

  the output line to its initial state (static), when the transistor P2 has become non-conducting and the transistor P1 is

again become a driver.

  This is a complete contrast with the prior art circuit in which: (a) there is a limitation to the stiffness of the anterior flank; (b) the final level of the pulse can not reach the potential of the power rail; and (c) the posterior flank can not return quickly to its initial level. By dynamically exciting the load by means of a signal produced on the output line of the circuit instead of using a passive upward pull transistor (or resistor) as in the prior art, operation is achieved.

  extremely fast with low average power dissipation.

  Thus, in the circuits forming modes of

  of the invention, although the input signals (e.g., changes appearing on the address lines) are randomly applied to the system, a pulse or an output signal * It is rapidly produced after the appearance a modification on

  the address line. The pulse or signal is well defined (ie

  that is, going from a complete "low" level to a full "high" level, or vice versa), has a steep leading edge to define the beginning of the preload and layout function, and has a posterior sidewall to terminate the preload and layout functions and start a reading or writing cycle. In the circuit of FIG. 5, three circuits 2a, 2b and 2c (each of which is identical to the circuit of FIG. 2) are connected by their respective outputs V12a, V12b and V12c, via lines 12a, 12b and 12c, to the electrodes gate of respective input transistors P41, P42 and P43. The numbers of address input signals (Ala to AXa, AB to ANb, Alc to AQc) applied to the circuits 2a, 2b and 2c are not necessarily the same. For example, in the circuit of FIG. 2, a multiplicity (m) of Ni transistors responding to the input signals are represented in connection with the node 12. To minimize the capacity associated with the node 12 and to obtain a higher speed of functioning, it can be

  advantageous to limit the number of input signals of each subset

  circuit (2a, 2b, 2c). In any case, the outputs of two or more circuits of the type shown in FIG. 2 can be combined

  or treated in common, as shown in Figure 5.

  The OR CABLE circuit 40 of FIG. 5 is a complementary version of the circuit of FIG. 2. The transitors responding to the signals are P4i transistors of conductivity type P whose conduction paths are connected in parallel between the voltage VDD and a line OR CABLE 42. The dynamic load comprises a transistor N41 (corresponding to the transistor P1 of FIG. 2) and a transistor N42 (corresponding to the transistor P2 of FIG.

  conduction are connected in parallel between the line 42 and the earth.

  An inverter I41 (corresponding to I1) is connected by its input to the line 42 and, by its output, to the gate of N41. Three inverters I42, 143 and 144 (respectively corresponding to I2, 13 and I4) are

  connected in cascade between the output of the inverter I41 and the elec-

transistor gate N42.

  The circuit 40 of FIG. 5 has a complementary function.

  ment, but otherwise identical to that of the circuit of Figure 2 and will not be described in detail. Thus, when a negatively oriented pulse is produced on one of the lines 12a, 12b and 12c, a positively oriented output pulse is produced on the output line 42. The pulse produced on the line 42 can be directly connected to various parts. of a subsequent circuit (not shown), or connected via a buffer to

subsequent circuits.

  The circuit of Figure 5 makes it clear that the input signals can be combined in many different ways to optimize the system response. The circuit of FIG. 5 also demonstrates that circuits consisting of embodiments of the invention can be combined to perform

  logical combination functions.

  A circuit embodying the invention, shown in FIG. 6, comprises insulated gate field effect transistors.

  NIi to NIm, of conductivity type N, whose conductivity paths

  are connected in parallel between a common OR CABLE line 12 and a reference potential point in the form of earth. Knowing that i is such that 1 C i <m, the gate electrode

  of each of the transistors NIi is connected to the output of a detector

  corresponding transition TDi. The input of each detector TDi is connected to a line of address Li to which is applied an address signal Ai. Transition detectors may be, for example, of the type shown in Figures 1 and 3 of U.S. Patent No. 4,039,858, but any other suitable transition detector may be used in their place. Whenever an address Ai present on any of the address lines goes from a "high" level to a "low" level, or from a "low" level to a "high" level, its corresponding transition detector TDi produces a positively oriented pulse Si, as shown in FIG. 3, which is applied to the gate electrode of its corresponding transistor Ni. (The signal Si is the opposite, or complement, of the output signal "C" shown in Figure 1 of the cited patent.) Thus, a positively oriented input pulse Si is produced for each signal transition on the d-line. Li address. Each transistor Nli responding to the input signals is normally in the non-conductive state, and it is turned on only when its corresponding signal Si is high level. The load of the circuit comprises insulated gate field effect transistors P3 and P5, of conductivity type P, whose main conduction paths are connected in parallel between line 12 and a terminal 16 to which an operating potential is applied. positive voltage VDD. The conduction impedance (ZP3) of the transistor P3 is designed to be substantially greater

  large than the conduction impedance (ZP5) of P5. We will easily

  this result by taking for the transistor P3 a device

  smaller than the P5 transistor. The value of ZP3, when the

  sistor P3 is conductive, is designed to pass enough current between the terminal 16 and the line 12 to produce the leakage current extracted by the transistor Nli connected to the line 12 in the static state, that is to say when none of the transistors Nli is conductive. This maintains the voltage V12 of the line 12 at the value VDD or a value close to it. A circuit 18 connected between the line 12 and the gate of the transistor PI produced at the gate of Pl

  a signal which is the complement of the signal present on line 12.

  In this embodiment, the circuit is a single inverter 11, preferably of the complementary conductivity type, connected by its input to the common line 12 and by its output to the gate of the transistor P1 and to the input of an inverter. 12. The inverter It produces at its output a signal which is the complement, or inverse, of the signal present at its input and which is only slightly delayed compared

to the existing signal at its entrance.

  The inverter 12 is constituted or formed of two

  sistors (N2 and P2) of complementary conductivity types whose conduction paths are connected in series between the VDD potential and the earth. The gate electrodes of transistors P2 and N2

  are connected together and define the input of the inverter 12.

  The drains of the transistors N2 and P2 are connected in common to the node 22, which defines the output of the inverter I2, and to which are connected the gate and drain electrodes of a transistor P4 and the gate electrode of a P5 transistor. In addition to amplifying and reversing the signals present on their inputs, the inverters

  It and I2 act as a delay network and

  good enough b high frequency to make the loop unstable

  formed by inverters II and I2 and transistors P4, P5 and Ni.

  Thus, the signal present on line 12 is delayed in II and 12 before being applied to the gate and the drain of transistor P4 and b the gate of transistor P5. The function of the inverter I2 is to delay, amplify and invert the output signal of the inverter Il before producing a signal at the node 22. The propagation delay introduced into the inverter I2 is, in part, a function of the dimensions of the transistors forming the inverter. Inverter II, like the inverter

  I2, may be formed of transistors of complete conductivity types

  mentary. However, one or both of these inverters could

  be formed using transistors of a single type of conductivity.

  The source electrodes of the transistors P4 and P5 are connected to the terminal 16, their gates and the drain of P4 are connected in common to the node 22, and the drain of the transistor P5 is connected to the output line 12. As it will be detailed below, the transistors P4 and P5 act as a current-ratio amplifier whose output current, 15, is controlled by

  the source-drain current 12, via the transistor N2.

  The initial-or static-conditions of the circuit of FIG. 6 are as follows: (1) The Ni transistors are non-conductive; (2) therefore, the voltage V12 of the common line 12 is of high level (i.e. of equal level b VDD); (3) thus, the output signal Vl of the inverter II is low (ie, the earth potential); (4) therefore, the transistor P3 is in the conductive state and provides a conduction path between the node 16 and the common output line 12 (but remember that ZP3 is a relatively high impedance); (5) transistor N2 is non-conductive; and (6) the transistor P2 is conductive and applies the voltage VDD to the gates of the transistors P4 and P5 so as to keep the latter non-conductive. In response to the conduction of any of the Ni transistors under the effect of a signal Si as shown in FIG. 7, the voltage of the line 12 starts to go into the

  negative sense. Each of the transistors NIi has an impedance of

  less than P5 and, of course, P3. Thus, as soon as a transistor Ni has become conductive, the output voltage V12 can and does go from the high level (V DD) to the low level (the earth). As soon as V12 begins to go in the negative direction, the inverter It amplifies and reverses the negatively oriented transition and the output signal (VI) of the inverter It goes from the low level to the high level. Since the signal VI moves in the positive direction, the gate-source potential of the transistor P3 decreases and the already high source-drain impedance of the transistor P3 increases further. Voltage VI quickly reaches the VDD value and, at this time, transistor P3 is completely non-conducting. Since the transistors P5 and P3 are non-conductive, any transistor NIi can completely discharge the node 12 to the potential of the earth, without opposition or restraint because of any charging device, as illustrated between times t1 and t2 in FIG. 7. Thus, as illustrated in FIG. 7 between the instants t1 and t2, the signal carried by the line 12 passes very rapidly from VDD to a zero voltage, or to a neighboring value. This is done with a very low power dissipation since the P3 transistors and

P5 are non-conductive.

  The signal transition from the low level to the high level (VDD) produced at the output of the inverter II is applied to the input of the inverter I2, which renders the transistor P2 nonconductive by turning on the transistor N2. The voltage applied to the gate of the transistor N2 circulates a current 12 in its source-drain path. When the voltage Vl is equal to or close to VDD, the transistor P2 becomes non-conductive and the current 12 flowing in the transistor N2 is equal to the current I4 extracted from the source-drain path of the transistor P4. The current I4 passing in the source-drain path of P4 leads to the creation of a certain potential

  gate-source (VGS4) between the source and the gate of transistor P4.

  This gate-source potential is identically applied between the gate gate and the source of the transistor P5. Consequently, the circuit formed by the transistors P4 and P5 operates as a current-ratio amplifier in geometrical relationship, that is to say, since the voltage VGS4 existing across P5 is the same as the voltage VCs across P4. Current I5 flowing in the source-drain path of transistor P5 is proportional to current I4. As is well known, the degree of proportionality (k) is determined by the relative dimensions of transistors P4 and P5. In this embodiment, the

  transistor P5 received a dimension worth ten times that of the transistor

  tor P4, so that the current I5 is ten times the current I4.

  However, the minimum effective impedance of transistor P5 in the conductive state is greater than the minimum effective impedance of any transistor NIi. The ratio of the impedance of the transistor P5 conducting to the impedance of any transistor NIi conductor is such that, if any of the transistors NIi is conducting while the transistor P5 is conducting, the maximum voltage present on the line 12 is lower than the threshold voltage drop (VT) of a N-type conductivity transistor. Therefore, as long as any of the Ni transistors are conductive, the voltage V12 remains lower than the voltage VTi

  as it appears between times t2 and t5 in FIG.

  In addition, the voltage Vl remains at the VDD level, which keeps the transistor P2 nonconductive and causes the transistor N2 to conduct

  a current 12 equal to 14 producing a current 15 on line 12.

  It is possible to adjust the delay controlling the conduction of the transistor P5 following the conduction of a transistor NIi by adjusting the relative dimensions of the transistors forming the inverters II and I2 or by adding an equal number of inverters or other delaying devices such as RCA time-lapse circuits, between the output of

  the inverter II and the input of the inverter I2.

  As a result of the transition to the non-conductive state of all the transistors Nli, the current source transistor P5 continues to deliver a constant current 15 to the output line 12. As a result, the output voltage quickly returns to the VDD value. via the constant current which linearly charges the output capacitance CL, as indicated between the instants t5 and t6 in FIG. 7. As soon as the voltage V12 arrives within the limits of a threshold voltage drop of V DD the inverter output signal It goes from the high level to the low level by making transistor P3 conductive. The two transistors P3 and P5 then contribute to reducing the potential of the line 12 to the value V DD As the up-to-down transition present at the output of the inverter It is amplified and inverted by the inverter I2 (with the propagation delay specific to 12), the transistor N2 becomes non-conductive and the transistor P2 becomes conductive. This brings the gates of the transistors P4 and P5 forming the current amplifier in a geometrical ratio up to the potential VDD, which renders the amplifier b currents in a geometrical ratio, that is to say which interrupts the current. 15 relatively constant. At this moment, the voltage V12 is at the VDD level, or at a very similar value,

  and was thus restored to its original state.

  When the transistor P5 and a transistor NIi are conductive, the potential existing on the line 12 is a function of the amount of current that the transistor P5 delivers to the line and the amount of current that the transistor NIi extracts from the

  line. If we assume that the inverter It is a complete inverter

  Of the type illustrated for the inverter I2, it is extremely important that the voltage V12 be maintained above the threshold voltage VT of the N-channel transistors in order to prevent the circuit from oscillating. This result is obtained in the circuit of FIG. 6 by giving the current I5 a value in a known ratio with the current I4, this current being proportional to the current I2 flowing in the transistor N2. The value of the current 12 is a

  function of the potential applied between the gate and the source of N2.

  Normally, when the transistor N2 leads, its gate electrode is brought up to the voltage VDD (which renders non-conductive

  transistor P2), while its source electrode is at potential

  tiel of the earth. The voltage VGS of the transistor N2 is then approximately

  it is equal to the voltage VDD and its source-drain voltage VSD is less than 1 volt. Note that when a transistor NIi is turned on, a voltage approximately equal to VDD is applied to its gate, while its source electrode is at

  potential of the earth. Consequently, the conductive state of the

  N2 is quite similar to the conductive state of a tran-

  sistor Ni who switched to the conductive state. It is also noted that the transistor N2 and the transistors Nli are of the same type of conductivity. Thus, when the transistor N2 and the Ni transistors

  formed as part of an integrated circuit, or in

  Analogous processing conditions, the variations appearing in transistors N2 and Ni follow each other as a function of time, temperature and voltage. Therefore, one can obtain, and one obtains, a very stable operation

for the circuit of Figure 6.

  Thus, in the circuits embodying the invention, it is possible to produce an impulse having a relatively steep front flank and a posterior flank, as well as a very high level.

stable between the flanks.

  The charging part of the circuit of FIG. 6 can be modified in the manner shown in FIG. 8. The charging device P3 is part of an inverter 13 which comprises a transistor N3, of N conductivity type, the drain of which is connected to line 12, whose source electrode is connected to the earth potential, and whose gate is connected to the gate of transistor P3. The input (gates of transistors P3 and N3) of the inverter 13 is connected to the output of a two-input logic gate G1. Depending on the type of function to be performed, the door G1 may be a NAND gate or

an NI door.

  The output line is connected to an input of the gate C1 and a component selection signal is applied to the other input of the gate GI. If the gate Gi is a NAND gate, when the component selection signal is "low", the gate C1 is disabled and the output voltage of the gate C1 is locked to the voltage VDD. When the component selection signal is "high", the gate C1 operates as an inverter connected between the line 12 and the input of the inverter 13. When the voltage V12 is high, the output of the gate Cl is low level, the

  transistor P3 is conductive and transistor N3 is non-conductive.

  When the voltage V12 goes low, the output of the gate G1 goes high, the transistor P3 becomes non-conductive, while the transistor N3 becomes conductive, which again helps

  to unload line 12 to the potential of the earth.

  It is possible to control, in the manner illustrated in FIG. 8, the relatively constant current source and current-ratio amplifier assembly in geometrical relationship. It is noted that the precharge pulse produced on the OR CABLE line 12 is applied to the detection circuit D and to the storage part M of the storage unit. An inverter 17 responding to the component selection signal is connected by its output to the gate electrodes of transistors P6 and N6, respectively of conductivity types P and N. The conduction path of transistor P6 is connected in series with the conduction path of a PIA transistor, of conductivity type P, between the terminal 16 and the node 26. The conduction paths of the transistors N6 and of a transistor NLA, of conductivity type N, are connected in parallel between the node 26 and Earth. PIA and NIA gate electrodes

are connected to line 12.

  When the component selection signal is "low", the output of the inverter 16 is high and the node 26 is brought to the "low" level, which keeps the transistor P2 conductive and the transistor N2 non-conductive, while the current-ratio amplifier and the current source are non-conductive When the component selection signal is "high",

  the output of the inverter 17 is low, which makes the

  sistor P6 conductor and the transistor N6 non-conductive. Transitions

  PIA and NLA sistors then play the role of an inverter responding to the signal present on the line 12, and the output of the inverter PLA, NIA then excites the input of the inverter 12 in a similar manner.

  to that described for the inverter II in relation to FIG. 4.

  Of course, those skilled in the art will be able to imagine

  from the circuits whose description has just been given for

  merely illustrative and in no way limitative, various other

  variants and modifications that are not outside the scope of the invention.

Claims (13)

R E V E N D I C A T IO N S   1. Circuit (FIGS. 2, 6, 8) for producing, on an output line (12), a well-defined pulse (V12) having relatively stiff anterior and posterior flanks in response to the transition to the conductive state of the any one of a plurality of input transistors (N1, N2, etc., NI1, NI2, etc.), wherein (a) the conduction paths of said input transistors are connected in parallel between said output line. and a first operating potential point (the ground) so that, when said input transistors are turned on, they tend to lock said output line to said first potential, and (b) a charging means (P1, P2, P3, P5) connects said output line to a second operating potential point (V DD), the circuit being characterized in that: the impedance of the charging means is adjustable; and means (18, 20; 11, P2, N2, P4; G1, I7, PIA, NIA, P2, N2, P4, P6, N6) responsive to the voltage on said output line is coupled to said output means; charging in order to (a) maintain the impedance of the load means at a first high value when all said transistors responsive to signals are in the non-conductive state; (b) passing the impedance of the charging means to a second value, higher than the first value, for a given predetermined duration (t2 to t5) when any of said signal-responding transistors are in the state driver; and (c) passing the impedance of the charging means b a value lower than said first value so as to allow the conduction of a significant current therethrough for a given duration following said predetermined predetermined duration (t5 to t7, t5 to t6).   The circuit of claim 1, characterized in that said adjustable impedance charging means comprises a first and a second charge transistor (P1, P2; P3, P5) each having a conduction path and a control electrode, and in that the conduction paths of the first and second load transistors are connected in parallel between said output line   and said second operating potential point.   3. Circuit according to claim 2, characterized in that the conduction path of the first load transistor has, when in the conductive state, an upper impedance b   that of the second load transistor.   Circuit according to Claim 2, characterized in that said means responsive to the voltage on the output line coupled to said charging means comprises: (a) first means (18, GI) connected between the output line and the control electrode of said first charge transistor ( PI; P3) so as to apply to said control electrode thereof a signal (V1) which is out of phase with the signal present on said output line; and (b) second means (18, 20; 18, 12, P4; 17, PIA, NIA, P2, N2, P4, P6, N6) responsive to the signal on the output line which is connected between the output and the control electrode of the second load transistor (P2; P5) so as to apply to the control electrode thereof a signal which has the same polarity as the signal present on the output line and which   is delayed in relation to this one.   5. Circuit according to claim 4, characterized in that said first means comprises an odd number of inverters (11) connected in cascade between said output line and the control electrode of said first transistor, and in that said second means comprises an odd number of additional inverters (12, 13, I4, I2) connected in cascade between the control electrode of said first transistor and the control electrode of the second transistor.   Circuit according to one of Claims 1 to 5,   characterized in that each of said transistors responsive to signals is made conductive by a relatively narrow pulse (Sl; Si).   7. Circuit according to claim 1, characterized in that said charging means comprises an adjustable impedance means (P3) and an adjustable constant current source (P5) connected in parallel with the adjustable impedance means between said line and a second potential point, and in that the means responding to the voltage present on said line comprises means (18, Gl) for passing said adjustable impedance means to   said second value when the voltage present on the line is.   locked to said first potential point, and means for putting said current source with a given delay (t2 to t5) in the conductive state with respect to the latching on said first potential point of the voltage present on said line, to supply said line with a current having a direction which tends to reduce the voltage present on said line to the existing level at the second point of potential.   8. Circuit according to claim 7, characterized in that said adjustable impedance means comprises a first transistor (P3) whose conduction path is connected between said line and said second potential point, and said relatively constant current source comprises a second, third and fourth transistors (F4, P5, N2) each having source and drain electrodes which define the ends of a conduction path and an electrode of control, and in that:   (a) the conduction path of said second transistor (P5) is connected between said line and said second potential point; (b) the conduction path of said third transistor (P4) is connected between the gate and source electrodes of said second transistor; (c) the source electrode of said fourth transistor (N2) is connected to said first potential point, and its drain electrode is connected to the drain and gate electrodes of said third transistor; and (d) means (18; P6, PIA, NIA, N6) are provided for applying to the gate electrode of said fourth transistor a signal   which is the inverse of the signal present on said line.   9. Circuit according to claim 8, characterized in that the conduction impedance of said first transistor is significantly higher than the conduction impedance of said second transistor, and in that the conduction impedance of said second transistor is higher than the impedance in conduction of said first input transistors.   Circuit according to claim 9, characterized in that said first, second and third transistors are of a first conductivity type, and said input transistors and said   fourth transistor are of a second type of conductivity.   11. Circuit according to claim 8, characterized in that said means responsive to the voltage present on said line and connected to said adjustable impedance means comprises a first inversion means (II), and in that said means responding to the voltage present on said line and coupled to said current source comprises a second inversion means (I2) connected between the output of said   first inversion means and said current source.   Circuit according to any one of Claims 1 to 11,   characterized in that some of said input transistors are coupled to the input line (A1, A2, etc.) via respective transition detectors (TD1, TD2, etc.), and in that each of said input transistors transition detectors turns a respective input transistor into a conductive state for a short time each time a signal level change occurs on its line associated entry.   13. A storage assembly, characterized in that it comprises a circuit according to claim 12 which responds to the presence on said input lines of address signals produced randomly by producing on said output line a precharge pulse whenever one of said address signals changes state.