NL7113723A - - Google Patents
Info
- Publication number
- NL7113723A NL7113723A NL7113723A NL7113723A NL7113723A NL 7113723 A NL7113723 A NL 7113723A NL 7113723 A NL7113723 A NL 7113723A NL 7113723 A NL7113723 A NL 7113723A NL 7113723 A NL7113723 A NL 7113723A
- Authority
- NL
- Netherlands
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/026—Deposition thru hole in mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/113—Nitrides of boron or aluminum or gallium
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/114—Nitrides of silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/122—Polycrystalline
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/923—Diffusion through a layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7846870A | 1970-10-06 | 1970-10-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
NL7113723A true NL7113723A (de) | 1972-04-10 |
Family
ID=22144214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL7113723A NL7113723A (de) | 1970-10-06 | 1971-10-06 |
Country Status (3)
Country | Link |
---|---|
US (1) | US3717514A (de) |
DE (2) | DE7137787U (de) |
NL (1) | NL7113723A (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5538823B2 (de) * | 1971-12-22 | 1980-10-07 | ||
US3847687A (en) * | 1972-11-15 | 1974-11-12 | Motorola Inc | Methods of forming self aligned transistor structure having polycrystalline contacts |
US3904454A (en) * | 1973-12-26 | 1975-09-09 | Ibm | Method for fabricating minute openings in insulating layers during the formation of integrated circuits |
US3933541A (en) * | 1974-01-22 | 1976-01-20 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor planar device |
US4109273A (en) * | 1974-08-16 | 1978-08-22 | Siemens Aktiengesellschaft | Contact electrode for semiconductor component |
US4074304A (en) * | 1974-10-04 | 1978-02-14 | Nippon Electric Company, Ltd. | Semiconductor device having a miniature junction area and process for fabricating same |
US4052251A (en) * | 1976-03-02 | 1977-10-04 | Rca Corporation | Method of etching sapphire utilizing sulfur hexafluoride |
FR2454697A1 (fr) * | 1979-04-20 | 1980-11-14 | Thomson Csf | Procede de formation d'une couche epitaxiee homopolaire sur un substrat semiconducteur |
US5134090A (en) * | 1982-06-18 | 1992-07-28 | At&T Bell Laboratories | Method of fabricating patterned epitaxial silicon films utilizing molecular beam epitaxy |
EP0164976B1 (de) * | 1984-06-02 | 1990-10-24 | Fujitsu Limited | Verfahren zum Herstellen eines Kontaktes für eine Halbleiteranordnung |
US4898838A (en) * | 1985-10-16 | 1990-02-06 | Texas Instruments Incorporated | Method for fabricating a poly emitter logic array |
USH665H (en) | 1987-10-19 | 1989-08-01 | Bell Telephone Laboratories, Incorporated | Resistive field shields for high voltage devices |
US5017999A (en) * | 1989-06-30 | 1991-05-21 | Honeywell Inc. | Method for forming variable width isolation structures |
US5234861A (en) * | 1989-06-30 | 1993-08-10 | Honeywell Inc. | Method for forming variable width isolation structures |
TW205603B (de) * | 1990-09-21 | 1993-05-11 | Anelva Corp | |
EP0620586B1 (de) * | 1993-04-05 | 2001-06-20 | Denso Corporation | Halbleiteranordnung mit Dünnfilm-Widerstand |
US5851923A (en) * | 1996-01-18 | 1998-12-22 | Micron Technology, Inc. | Integrated circuit and method for forming and integrated circuit |
US6242792B1 (en) | 1996-07-02 | 2001-06-05 | Denso Corporation | Semiconductor device having oblique portion as reflection |
TW468271B (en) * | 1999-03-26 | 2001-12-11 | United Microelectronics Corp | Thin film resistor used in a semiconductor chip and its manufacturing method |
US6399465B1 (en) * | 2000-02-24 | 2002-06-04 | United Microelectronics Corp. | Method for forming a triple well structure |
US8012830B2 (en) * | 2007-08-08 | 2011-09-06 | Spansion Llc | ORO and ORPRO with bit line trench to suppress transport program disturb |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3189973A (en) * | 1961-11-27 | 1965-06-22 | Bell Telephone Labor Inc | Method of fabricating a semiconductor device |
US3234058A (en) * | 1962-06-27 | 1966-02-08 | Ibm | Method of forming an integral masking fixture by epitaxial growth |
GB1030540A (en) * | 1964-01-02 | 1966-05-25 | Gen Electric | Improvements in and relating to semi-conductor diodes |
US3477886A (en) * | 1964-12-07 | 1969-11-11 | Motorola Inc | Controlled diffusions in semiconductive materials |
DE1544273A1 (de) * | 1965-12-13 | 1969-09-04 | Siemens Ag | Verfahren zum Eindiffundieren von aus der Gasphase dargebotenem Dotierungsmaterial in einen Halbleitergrundkristall |
US3490964A (en) * | 1966-04-29 | 1970-01-20 | Texas Instruments Inc | Process of forming semiconductor devices by masking and diffusion |
US3514845A (en) * | 1968-08-16 | 1970-06-02 | Raytheon Co | Method of making integrated circuits with complementary elements |
-
1970
- 1970-10-06 US US00078468A patent/US3717514A/en not_active Expired - Lifetime
-
1971
- 1971-10-05 DE DE19717137787U patent/DE7137787U/de not_active Expired
- 1971-10-05 DE DE19712149766 patent/DE2149766A1/de active Pending
- 1971-10-06 NL NL7113723A patent/NL7113723A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
DE2149766A1 (de) | 1972-04-13 |
US3717514A (en) | 1973-02-20 |
DE7137787U (de) | 1972-01-05 |