NL6501038A - - Google Patents

Info

Publication number
NL6501038A
NL6501038A NL6501038A NL6501038A NL6501038A NL 6501038 A NL6501038 A NL 6501038A NL 6501038 A NL6501038 A NL 6501038A NL 6501038 A NL6501038 A NL 6501038A NL 6501038 A NL6501038 A NL 6501038A
Authority
NL
Netherlands
Prior art keywords
bit
word
store
address
latches
Prior art date
Application number
NL6501038A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL6501038A publication Critical patent/NL6501038A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

1,038,704. Error detection. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1964 [Feb. 14, 1964], No. 6273/64. Heading G4A. In a data store, a word comprises (a) bits for addressing the next word, (b) a check bit for the bits (a), and (c) a check bit for the address of the current word (" true address "), and the bit (b) of a word read from the store or a bit derived from it is delayed for one store cycle and then compared with the bit (c) of the next word read out to check that this latter word is the required one. The invention is applied to a read-only microprogramme store. In order to allow address modification in accordance with machine conditions, a word read from the store and placed in latches also supplies condition bits to a " condition test " unit also responsive to machine condition signals to produce signals for modifying or supplementing the address bits (a) from the word in the latches. Fig. 3 (not shown) shows the " condition test " unit as a single exclusive-or gate receiving a carry indication, and a single condition bit from the latches, and producing a bit which together with the address bits (a) from the latches constitutes the address of the next word in the store. If the bit from the " condition test " unit is ONE, the check bit (b) from the latches is inverted (details in Fig. 3, not shown) before reaching the delay.
NL6501038A 1964-02-14 1965-01-28 NL6501038A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB627364A GB1038704A (en) 1964-02-14 1964-02-14 A self-addressed data store

Publications (1)

Publication Number Publication Date
NL6501038A true NL6501038A (en) 1965-08-16

Family

ID=9811523

Family Applications (1)

Application Number Title Priority Date Filing Date
NL6501038A NL6501038A (en) 1964-02-14 1965-01-28

Country Status (2)

Country Link
GB (1) GB1038704A (en)
NL (1) NL6501038A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2533995A1 (en) * 1975-07-30 1977-02-17 Bodenseewerk Geraetetech DEVICE FOR MONITORING A DIGITAL FLIGHT CONTROLLER
US4019033A (en) * 1975-12-29 1977-04-19 Honeywell Information Systems, Inc. Control store checking system and method
IT1058706B (en) * 1976-03-30 1982-05-10 Honeywell Inf Systems MICROPROGRAMMED GOVERNMENT APPARATUS EQUIPPED FOR VERIFYING THE ADDRESSING OF MICROPROGRAMMING MEMORY
DE3224885A1 (en) * 1982-07-03 1984-01-05 Paul 7032 Sindelfingen Merkle SERIAL TETRAD ADDING SUBTRACTING MACHINE IN BCD-8421 CODE
US5241547A (en) * 1987-08-31 1993-08-31 Unisys Corporation Enhanced error detection scheme for instruction address sequencing of control store structure
WO1989002125A1 (en) * 1987-08-31 1989-03-09 Unisys Corporation Error detection system for instruction address sequencing

Also Published As

Publication number Publication date
GB1038704A (en) 1966-08-10

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