GB1038704A - A self-addressed data store - Google Patents
A self-addressed data storeInfo
- Publication number
- GB1038704A GB1038704A GB627364A GB627364A GB1038704A GB 1038704 A GB1038704 A GB 1038704A GB 627364 A GB627364 A GB 627364A GB 627364 A GB627364 A GB 627364A GB 1038704 A GB1038704 A GB 1038704A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bit
- word
- store
- address
- latches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
1,038,704. Error detection. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1964 [Feb. 14, 1964], No. 6273/64. Heading G4A. In a data store, a word comprises (a) bits for addressing the next word, (b) a check bit for the bits (a), and (c) a check bit for the address of the current word (" true address "), and the bit (b) of a word read from the store or a bit derived from it is delayed for one store cycle and then compared with the bit (c) of the next word read out to check that this latter word is the required one. The invention is applied to a read-only microprogramme store. In order to allow address modification in accordance with machine conditions, a word read from the store and placed in latches also supplies condition bits to a " condition test " unit also responsive to machine condition signals to produce signals for modifying or supplementing the address bits (a) from the word in the latches. Fig. 3 (not shown) shows the " condition test " unit as a single exclusive-or gate receiving a carry indication, and a single condition bit from the latches, and producing a bit which together with the address bits (a) from the latches constitutes the address of the next word in the store. If the bit from the " condition test " unit is ONE, the check bit (b) from the latches is inverted (details in Fig. 3, not shown) before reaching the delay.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB627364A GB1038704A (en) | 1964-02-14 | 1964-02-14 | A self-addressed data store |
NL6501038A NL6501038A (en) | 1964-02-14 | 1965-01-28 | |
FR5146A FR1424317A (en) | 1964-02-14 | 1965-02-11 | Parity check in an automatically addressed data memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB627364A GB1038704A (en) | 1964-02-14 | 1964-02-14 | A self-addressed data store |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1038704A true GB1038704A (en) | 1966-08-10 |
Family
ID=9811523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB627364A Expired GB1038704A (en) | 1964-02-14 | 1964-02-14 | A self-addressed data store |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB1038704A (en) |
NL (1) | NL6501038A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2319938A1 (en) * | 1975-07-30 | 1977-02-25 | Bodenseewerk Geraetetech | INSTALLATION FOR MONITORING |
FR2337374A1 (en) * | 1975-12-29 | 1977-07-29 | Honeywell Inf Systems | CONTROL MEMORY VERIFICATION SYSTEM AND METHOD |
FR2346770A1 (en) * | 1976-03-30 | 1977-10-28 | Honeywell Inf Systems Italia | MICROPROGRAMM CONTROL UNIT EQUIPPED WITH MEANS TO CHECK THE ADDRESSING OF THE MICROPROGRAMMATION MEMORY |
EP0098539A2 (en) * | 1982-07-03 | 1984-01-18 | Paul Merkle | Serial tetrad adding-subtracting circuit in the BCD-8421 code |
WO1989002125A1 (en) * | 1987-08-31 | 1989-03-09 | Unisys Corporation | Error detection system for instruction address sequencing |
US5241547A (en) * | 1987-08-31 | 1993-08-31 | Unisys Corporation | Enhanced error detection scheme for instruction address sequencing of control store structure |
-
1964
- 1964-02-14 GB GB627364A patent/GB1038704A/en not_active Expired
-
1965
- 1965-01-28 NL NL6501038A patent/NL6501038A/xx unknown
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2319938A1 (en) * | 1975-07-30 | 1977-02-25 | Bodenseewerk Geraetetech | INSTALLATION FOR MONITORING |
FR2337374A1 (en) * | 1975-12-29 | 1977-07-29 | Honeywell Inf Systems | CONTROL MEMORY VERIFICATION SYSTEM AND METHOD |
FR2346770A1 (en) * | 1976-03-30 | 1977-10-28 | Honeywell Inf Systems Italia | MICROPROGRAMM CONTROL UNIT EQUIPPED WITH MEANS TO CHECK THE ADDRESSING OF THE MICROPROGRAMMATION MEMORY |
EP0098539A2 (en) * | 1982-07-03 | 1984-01-18 | Paul Merkle | Serial tetrad adding-subtracting circuit in the BCD-8421 code |
EP0098539A3 (en) * | 1982-07-03 | 1986-06-11 | Paul Merkle | Serial tetrad adding-subtracting circuit in the bcd-8421 code |
WO1989002125A1 (en) * | 1987-08-31 | 1989-03-09 | Unisys Corporation | Error detection system for instruction address sequencing |
US5241547A (en) * | 1987-08-31 | 1993-08-31 | Unisys Corporation | Enhanced error detection scheme for instruction address sequencing of control store structure |
Also Published As
Publication number | Publication date |
---|---|
NL6501038A (en) | 1965-08-16 |
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