NL2006171C2

NL2006171C2 - A photovoltaic cell device and a solar panel.

Info

Publication number: NL2006171C2
Application number: NL2006171A
Authority: NL
Inventors: Wijnand Michiel Godfried Hooff; Klaas Heres
Original assignee: Tsc Solar B V
Priority date: 2011-02-09
Filing date: 2011-02-09
Publication date: 2012-08-10

Description

A photovoltaic cell device and a solar panel

FIELD OF THE INVENTION

5 The invention relates to a photovoltaic cell device comprising a semiconductor substrate with a first side and an opposed second side, which first side is to be exposed to radiation, which cell device comprises a plurality of subcells that each comprise a first doped region and a 10 second doped region of opposite conductivity type for defining a light sensitive element, the first doped region being located adjacent to the first side and the second doped region being located adjacent to the second side.

The invention further relates to a solar panel comprising a 15 backsheet with conductors and a plurality of such photovoltaic cell devices.

BACKGROUND OF THE INVENTION

W003/073517 discloses a multi-junction, monolithic, 20 photovoltaic cell comprising an array of subcells, i.e. active p/n junctions that are grown on a compliant substrate. The array of subcells is based on III-V semiconductor materials as known in the art, such as GalnAs, GalnAsP, AlInAs and the like. The compliant substrate 25 accomodates greater flexibility in matching lattice constants to the adjacent III-V semiconductor material. The compliant substrate comprises typically a base substrate of Si and a perovskite layer, such as Barium titanate (BaTiCt) and the like. The base substrate has a thickness of 30 approximately 30 nm.

Suitably, the subcells in the photovoltaic cell are voltage-matched to subcells in a different photovoltaic cell to form voltage-matched, monolithic, tandem, bi-junction 2 and/or two-subcell (BT-MIM) photovoltaic devices. Voltage matching of two separate subcell strings is accomplished through a biaxial interconnection scheme that takes advantage of the two degrees of freedom available on a 5 planar surface too make two independent, orthogonal, serially interconnected subcell strings. Subcells in a subcell string in a voltage matched photovoltaic device are simultaneously electrically isolated from the other subcells within the photovoltaic cell by an isolation layer.

10 This known photovoltaic device provides an example of a new architecture, wherein a photovoltaic cells are subdivided into subcells that are coupled together into a serially interconnected subcell string. While it is common to assemble a plurality of cells into a photovoltaic device 15 (panel) in accordance with a certain circuit topology, the further subdivision is used in this W003/073517 to obtain voltage matching on a higher level. Additionally, the subcells are monolithically integrated on a single substrate, which is beneficial from manufacturing and 20 handling perspective.

However, overall, the known photovoltaic device is rather a research prototype than an industrially viable device. A 30 nm thick substrate is indeed compliant or even flexible, but therewith it is too thin to act as a carrier 25 during manufacture. Providing the perovskite layer on top of the silicon base substrate requires a process that is industrially not so easy to control. The growth of III-V semiconductor material thereon, typically at high temperatures of above 1000 °C with CVD, may affect the 30 consistency of the perovskite layer, leading to migration of elements thereof and/or recrystallisation. It goes without saying that the shown device is not optimized for cost 3 and/or for yield purposes, which are essential for an industrially viable process.

SUMMARY OF THE INVENTION

5 It is therefore an object of the present invention, to provide an industrially viable process for manufacturing a photovoltaic cell that is subdivided into a plurality of subcells, which subcells are to be arranged in a desired circuit topology and wherein such subcells are to operate 10 independently of neighbouring cells.

It is a further object of the invention to provide a photovoltaic cell and a resulting device subdivided into subcells .

This is achieved in accordance with the invention in a 15 method of manufacturing a photovoltaic cell device provided with a plurality of subcells, each provided with a p-i-n diode, which method comprises the steps of: providing a semiconductor substrate with a first side and an opposed second side, which first side is to be 20 exposed to radiation, the substrate comprising charge carriers of a first conductivity type; providing a plurality of first doped regions of the second conductivity type adjacent to the first side of the substrate, neighbouring first doped regions being separated 25 by at least substantially insulating or semiconductor areas; defining a second doped region of the first conductivity type adjacent to the second side of the substrate, an intermediate region extending between the first and second doped regions, the first doped region, the 30 intermediate region and the second doped region jointly defining the p-i-n diode, and providing a second doped region of the first conductivity type adjacent to the second side of the 4 semiconductor substrate, an intermediate region extending between the first and second doped regions, which second doped region is subdivided by at least substantially insulating or semiconducting subdivisions located 5 correspondingly to the at least substantially electrically insulating or semiconductor areas, therewith defining the subcells .

According to a further aspect of the invention, a photovoltaic cell device is provided, comprising a 10 semiconductor substrate with a first side and an opposed second side, which first side is to be exposed to radiation, which cell device comprises a plurality of subcells each comprising a first doped region and a second doped region of opposite conductivity type and an intermediate region 15 extending between the first and the second doped region, which intermediate region is provided with charge carriers of a first conductivity type in a concentration lower than the concentration of the first conductivity type in either the first or the second doped region, wherein the 20 intermediate region is mechanically continuous between the subcells, wherein subdivisions are present between the second doped regions of neighbouring subcells and wherein substantially insulating or semiconductor areas are present between the first doped regions of neighbouring subcells.

25 In accordance with the invention, the semiconductor substrate constitutes both the carrier and an active portion of the solar cell. The provision of the electrically semiconducting or insulating areas between the first doped regions and the application of subdivisions through the 30 second doped region into the intermediate regions ensures decoupling of the neighbouring regions and the junctions with the intermediate region.

5

The subdivisions of the second doped region may be defined prior to and/or subsequent to the step of applying charge carriers to form the second doped region. When defined prior to the application of charge carriers, it is 5 suitably applied in the form of a mask, so as to prevent the formation of the second doped region in accordance with the subdivisions. This method is further described in the copending application 'patterned field region', that is included herein by reference. When defined after the 10 application of charge carriers, the second doped region is locally removed in accordance with the subdivisions.

In one embodiment, the subdivisions and/or the electrically insulating or semiconductor areas between the first doped regions are trenches extending into the 15 intermediate regions. The term trenches is used herein to refer to a removed and thereafter filled or unfilled substrate portion of any shape and includes are for instance grooves, trenches, channels and the like. The shape and depth does not need to be uniform along the trench. The 20 trench may be filled with a suitable, electrically insulating material. Such material may be provided with a printing technique directly into the subdivisions, and suitably at limited locations only. Due to its fluid composition the printed fluid will be distributed through 25 the channels without contaminating the substrate surface. Suitable printing techniques include screenprinting and inkjet printing. A heat treatment for curing may follow the provision of the filler material as known to the skilled person. The trench suitably has an annular extension so as 30 to extend fully around a subdivided portion of either the first doped region or the second doped region. The trenches could be present between the first doped regions and/or as subdivisions in the second doped region. Most suitably, at 6 least some, and preferably all of the subdivisions of the second doped region are embodied as trenches. The second doped region is doped with the same conductivity type as the substrate, whereas the first doped regions are doped with an 5 opposed conductivity type. Therefore, the provision of the subdivisions as trenches more strongly enhances the resistance between individual subcells.

Although trenches provide suitable isolation, it is a disadvantage that it reguires additional process steps, and 10 that the provision of trenches generates the risk of initiation of cracks into the semiconductor substrate. In an alternative embodiment, thus, no trenches areapplied on the first side. This may be achieved, for instance, by application of a mask corresponding to a border between 15 neighbouring subcells, prior to the provision of the first doped regions. The mask should be able to withstand any temperature used during the provision of the first doped regions, typically a step of above 700 °C.

In order to minimize leakage between subcells, the 20 first doped regions are embodied, in one implementation, as a combination of a selective emitter and a diffusion region surrounding the selective emitter. The selective emitter suitably has a higher dopant concentration than the diffusion region, and is intended as a contact region to a 25 conductor on top of the first side of the semiconductor substrate. As a result thereof, the effective distance on the first side between the first doped regions is egual to the distance between the selective emitters. This distance is larger than the distance between the first doped regions. 30 It therefore appears that the local absence of the diffusion region in the at least substantially electrically insulating or semiconductor area is sufficient.

7

Suitably, the first doped regions are p-type doped and the intermediate region and the second doped regions are n-type doped. The doping of the p-type first doped regions is suitably provided with boron implantation or boron 5 diffusion. Diffusion processes are preferred for solar cell manufacture for cost reasons. By application of a suitable barrier layer overlying the electrically insulating areas, the diffusion of boron into those areas can be minimized. Particularly nitrides are suitable barrier layers.

10 Alternatively, high temperature oxide layers of sufficient thickness may be used).

In a further embodiment, the subcells are grouped into subcell groups, the subcells within one group constituting one string. It has been found that the organization of 15 subcells into strings allows appropriate control of the output current and output voltage. Moreover, the string leads only to a limited leakage current from one subcell to any neighbouring subcell through the intermediate region which does not appear to disturb operation or lifetime of 20 the photovoltaic cell device. The string of subcells in one subcell group is particularly a series connection of subcells. It is however not excluded that the string comprises one or more sections with parallel subcells.

Suitably, the subcell groups are mutually separated 25 through intermediate regions with sufficient electrical insulation. A first and second subcell group may thus carry different voltage levels, and be switched either in series or in parallel. Implementations of such sufficient electrical insulation, which do not disturb the mechanical 30 continuity will be discussed below.

Additionally, the voltage differences between neighbouring subcells in different subcell groups are suitable kept limited to a maximum voltage difference, for 8 instance in the order of 10V, more preferably 8V, most preferably 5V. This maximum voltage difference between neighbouring subcells in different subcell groups is a design rule that allows a designer to arrive at an 5 appropriate design. It is herein observed that a solar panel typically comprises a plurality of photovoltaic cell devices manufactured on different substrates. The electrical isolation between those photovoltaic cell devices is anyhow appropriate, such that the design rule within a single 10 photovoltaic cell device may be more strict.

The resulting subdivision of a photovoltaic cell device into several subcell groups with subcells in series allows the generation of an output voltage and output current at any desired level, particularly a voltage level that will 15 not be too high. Moreover, this subdivision reduces the risk for malfunctioning during to shadow effects during use of the solar panels. Shadows falling on the solar panel, for instance due to trees, lead to a higher resistance through some of the cells or subcells. When all are coupled in 20 series, the generated voltage will be significantly reduced as a consequence of the internal resistance due to the shadow effect. With the subdivision in accordance to the invention, the malfunctioning subcells will simply be noncontributing, whereas the other subcells will function 25 appropriately.

Several options are available for the definition of electrically insulating or semiconductor zones within the intermediate region at locations substantially corresponding to the subdivisions between cell groups.

30 In a first implementation, use is made of local implantation or irradiation so as to damage the crystal lattice. A first suitable embodiment is an implantation with Argon or another noble or inert gas. Such an implantation 9 will increase the resistance of the silicon. It could even lead to amorphous regions in the silicon substrate. A second suitable embodiment is the irradiation with electron beams or the like. Use of electron beam writing has the further 5 advantage that no separate masking is needed, which reduces process steps.

In a second implementation, trenches (or through-holes) are defined at the reguired locations. Subsequently, the substrate with the trenches is subjected to a thermal 10 oxidation treatment, wherein the first and second sides of the substrate are substantially covered. The oxidation will then occur in the created trenches. Since the thermal oxidation process consumes silicon, the electrically insulating zones will be extended, while at the same time 15 the trenches may get a reduced diameter or may be filled completely. It is one specific advantage that a single mask may be used for definition of the trenches and for protection of the first side of the substrate against the thermal oxidation.

20 In a further implementation, trenches are defined over a major portion of the subdivisions. As a result thereof, the intermediate region will be limited between the subcells to mechanical bridges. The trenches could extend completely through the intermediate region, so as to create a through-25 hole from the one side to the other side of the substrate.

In this case, the trenches will be limited in lateral extension. Alternatively, the trenches may extend merely into the intermediate region, for instance to at least 50% of the intermediate region. In this case, the trenches could 30 be, but need not to be, ring shaped around one or more subcells. In this case, it is preferable that the intermediate region is continuous adjacent to the second side, rather than adjacent to the first side.

10

In an even further implementation, the mechanical bridges defined by thinned silicon, preferably in combination with through-holes, effectively defines a temporary state. That is: after assembly and fixation to a 5 carrier, the mechanical bridges are punched through, such that the subcells will be completely isolated from each other. It is to be understood that such removal of mechanical bridges could be limited to certain subdivisions only. As will be discussed hereinafter, the subcells are to 10 be ordered into units of subcells. The isolation of a first subcell to a third subcell may be more important from that functional perspective than the isolation of the first subcell to a second subcell.

Suitably, these treatments are carried out prior to 15 defining the doped regions of the first and second conductivity type adjacent to the substrate sides. However, particularly the further embodiment based on the generation of mechanical bridges could alternatively be carried out substantially after completion of the processing.

20 In a preferred embodiment, the first doped regions are defined as selective emitters. The use of selective emitters is a suitable manner optimizing the design of the subcell. Suitably, the selective emitters are provided in a grid type design. Such a grid type of design comprises emitters 25 extending in at least two mutually crossing directions.

Preferably, the directions include an angle of 90 degrees, but that is not necessary. The number of emitters in the at least two directions need not to be equal.

Most suitably, a first terminal is provided on the 30 second side of the semiconductor substrate and is coupled to the first doped region exposed on the first side with a through-silicon vias extending from the first to the second side. A second terminal is also provided on the second side 11 and contacts the second doped region on the second side. Such a type of cell is known as a back-contacted solar cell. The through silicon via could for instance located at an edge of the subcell, but also within the subcell. The latter 5 arrangement, suitably in combination with the use of more than one through silicon via per subcell, is deemed most beneficial. A suitable number is less than 10 per subcell. Typically, the at least one through silicon via is present at a crossing of said selective emitters.

10 The first conductivity type may be either p or n, and is preferably n-type, so that also the intermediate region is n-type doped. Solar cells based on n-type silicon are deemed to provide a higher efficiency. The semiconductor substrate is most suitably a monocrystalline silicon 15 substrate. The doping level of the n-type substrate is preferably in the range of 1.1015-1.1017 (cm-3). The doping level of the first and second doped regions is suitably higher than 1.1018 cm-3.

The mutual distance between neighbouring subcells is 20 suitably in the range of 10-100 microns. The number of subcells per cell of an 8 inch (20 cm) format as typically used in semiconductor processing, is suitably in the range of 4 to 64, more preferably in the range of 9 to 25.

Suitably, the subcells all have same dimensions, but this is 25 not deemed necessary. The form of a single subcell may be square, circular, hexagonal, octagonal, but also rectangular or oval, such that a first dimension of the subcell is larger than a second dimension (in a direction perpendicular to the first dimension). The subcell size is preferably 30 optimized such that a single via 12

BRIEF DESCRIPTION OF THE FIGURES

These and other aspects of the invention will be further elucidated with reference to the Figures, in which: Fig 1-6 are diagrammatical, cross-sectional views of 5 consecutive steps for manufacture of a photovoltaic cell device in accordance with the invention;

Fig. 7 is a diagrammatical, cross-sectional view of the photovoltaic cell device in accordance with the invention; Fig. 8 is a diagrammatical top view of a first 10 embodiment of the photovoltaic cell device in accordance with the invention;

Fig. 9 is a diagrammatical top view of a second embodiment of the photovoltaic cell device in accordance with the invention; 15 Fig. 10-13 are diagrammatical figures for representing the circuit topology used in the photovoltaic cell device in accordance with the invention, and.

Fig. 14-17 are diagrammatical, cross-sectional views of consective stages of one embodiment of the method in 20 accordance with the invention.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

The Figures are not drawn to scale and merely intended for illustrative purposes. Equal reference numerals in 25 different figures refer to like or equal parts. The terms 'first side' and 'front side' will be used hereinafter interchangeably. The terms 'second side' and 'rear side' will be used herein interchangeably.

Fig 1-6 show in cross-sectional, diagrammatical view 30 several stages of a method for manufacturing a photovoltaic cell device according to one embodiment of the invention.

The resulting preferred embodiment of the cell device as shown in Fig. 6 comprises through-silicon vias 40 enabling 13 the location of first and second terminals 51, 52 on the second side 12 of the semiconductor substrate 10 with intermediate region 35, first doped region 30, 31 and second doped region 33. The first doped region comprises herein a 5 selective emitter region 30 and a diffusion region 31.

Fig. 7 shows on a larger scale the device as shown in Fig. 6, with additionally the subdivisions 151, 152 applied into the semiconductor substrate 10 from the first side 11 and from the second side 12. These subdivisions 151, 152 10 clearly indicate the arrangement of the photovoltaic cell device 100 with a plurality of subcells 200. The subcells 200 are mutually mechanically coupled through the intermediate region 35 of the substrate 10. The first doped regions 31 and second doped regions 33 are however mutually 15 insulated through the subdivisions 151, 152 here in the form of trenches. The manufacture of the Figures 1-6 will now be discussed in more detail.

As a first step, Fig. 1 shows a semiconductor substrate 10 with a front side 11 and a rear side 12. The front side 20 is the side that is intended for receiving irradiation during use; the solar cell will be assembled on its rear side 12 to a carrier. It typically has been texturized in advance of doping processes. The semiconductor substrate 10 of this example is a monocrystalline silicon substrate.

25 While silicon substrates constitute the best available compromise between manufacturing costs and quality, it is not excluded that alternative substrates are used. Such alternative substrates could be made of III-V materials, but more likely incorporate one or more layers of a different 30 material, such as a III-V material, or SiGe, SiC and the like as known to the skilled person. The semiconductor substrate is doped with a dopant of the first conductivity type, which is in the preferred example n-type. The doping 14 concentration is moderate, for instance 1016 /cm3. The semiconductor substrate 10 is provided at both the front side 11 and the rear side 12 with a region of n++-doped material. Suitably, use is made of phosphorous doping in a 5 manner known to the skilled person, for instance by vapor deposition. According to one embodiment, the phosphorous doping is diffused into the regions 13A, 13B of the substrate 10 by a heat treatment of approximately 800 °C for 5-50 minutes in an atmosphere containing O2 and P2O5 vapour. 10 This results in the formation of a silicon oxide film (not shown) which incorporates P2O5. At the interface the substrate and the silicon oxide film, the P2O5 is reduced to elemental phosphorous, which diffuses into said regions 13A, 13B. Subsequently, the silicon oxide film is removed by 15 dipping the substrate in a 1-50% HF solution for about 0.5-10 minutes, or exposing the substrate to a HF vapour.

Fig.2 shows the substrate 10 in a second stage, after an etching treatment. Herein, the region 13A at the front side 11 is removed by etching, for instance using a mixed 20 solution of 1-30% HF and 0.1-50% HNO3. This result in a substrate 10 that has been doped at its rear side 12 with a dopant species of the first conductivity type to define at least one field region 13B. Moreover, a through-hole 20 is provided into the semiconductor substrate 10, and extends 25 from the front side 11 to the rear side 12 thereof.

Typically, a plurality of through-holes 20 is applied in a single solar cell, so as to reduce a lateral distance over which generated current has to be transported to a terminal. The through-holes are typically applied by laser etching, 30 although other forms of etching, such as reactive ion etching or a combination of reactive ion etching and wetetching are not excluded. While the through-hole 20 is shown to be straight, it is not excluded that the through-hole 20 15 is further modified to have a varying diameter, or that any sharp edges at its top and bottom side, i.e. on the front side 11 and the rear side 12 are removed. The diameter of the through-hole is typically in the order of 5-400 microns.

5 Fig. 3 shows the substrate 10 in a third stage, after application of a diffusion resistance layer 22. The diffusion resistance layer 22 is suitably applied by chemical vapour deposition or thermal oxidation, and more preferably by low pressure chemical vapour deposition 10 (LPCVD), atomic layer deposition (ALD) or a rapid thermal anneal (RTA). Such state of the art techniques can be applied to provide a diffusion resistance layer of good thickness uniformity which covers the substrate sides. The diffusion resistance layer suitably comprises an inorganic 15 material such as an oxide or a nitride of silicon, titanium, tantalum, tungsten, mixtures thereof (TiWN, SiON), combinations thereof (a sublayer of Si02, and a sublayer of SiN). Use of an oxide layer, particularly a silicon oxide film, is preferred, as it allows diffusion of boron into the 20 semiconductor substrate 10 at a reduced rate. The exact composition as well as density of the diffusion resistance layer may be varied by tuning of the composition of the gas. In the present embodiment, the diffusion resistance layer 22 is particularly intended so as to prevent a boron rich layer 25 that is believed to be responsive for fast carrier lifetime degradation in the bulk of the substrate 10. The diffusion resistance layer is further intended to create selective emitter regions. However, it is not excluded, and it may even be advantageous, that outside the selective emitter 30 regions p+ material is present but in a lower dopant concentration, particularly resulting from diffusion through the diffusion resistance layer. The diffusion resistance 16 layer 22 may have a relatively low thickness, for instance in the order of 2-30 nm.

It is not excluded that the diffusion resistance layer is applied with an alternative technique, such as a low 5 temperature oxide, for instance a Plasma enhanced chemical vapour deposition (PECVD). Upon providing a boron oxide - in situ converted from a boron source such as boron tribromide (BBr3) - the boron oxide then tends to be absorbed, at least partially, in the low temperature oxide, resulting in a 10 boron silicate glass. Reduction of the boron diffusion may then be achieved by operating in an atmosphere substantially free of hydrogen, and more particularly in an inert atmosphere such as nitrogen (N2) or argon.

As shown in Fig. 3, the diffusion resistance layer 22 15 of this embodiment extends both on the front side 11, the rear side 12 and on walls of the through-holes 20. This is the consequence of application thereof in a chemical vapour deposition step without blocking of any of the sides to prevent the application of the barrier layer 22. However, 20 that is not deemed necessary. For instance, either the front side 11 or the rear side 12 may be blocked from deposition of the chemical vapour, particularly in a back-to-back arrangement of the semiconductor substrates 10. It is even possible, in line therewith, to apply a stacked arrangement 25 such that both the front side 11 and the rear side 12 of the stacked substrates 10 will not be exposed. This provides freedom to deposit alternative layers on the front side than in the through-hole. For instance, the through-hole 20 may contain a nitrogen-containing diffusion resistance layer 22, 30 while the front side 11 is provided with a high temperature oxide layer as diffusion resistance layer 22 allowing boron diffusion at a reduced rate. The diffusion resistance layer 17 22 is then subsequently opened in accordance with a predefined pattern so as to create apertures 25.

The provision of such pattern is suitably carried out with photolithography, typically by using a mask, as known 5 to the skilled person. In the present domain of solar cells, high resolution patterning such as known from integrated circuit manufacturing is however not required. A more simplistic solution as the screenprinting of a local mask around an aperture area, and thereafter providing an etchant 10 liquid in the thus created, screenprinted basin, is not excluded. Such a mask is suitably removed again prior to the subsequent high temperature doping step. Alternatively, one could use a screenprinting slurry or an inkjet printing slurry, which includes an etchant in itself. One 15 particularly preferred embodiment, is the use of a screenprinting slurry or paste based on a borate acid etchant. This enables to etch the diffusion resistance layer 22 and to provide doping into the semiconductor substrate 10 in a single step.

20 Fig. 4 shows the substrate 10 in a fourth stage, after the provision of the doping species of a second type, in this case p+ type. The Boron diffusion source may be a vapour source or a coating source. In the oven the substrate is heated for a certain period of time and to a certain 25 temperature so as to diffuse Boron into the front side of the substrate 10, and create selective emitter regions 30, and around those diffusion regions 31 of a lower concentration. While the present figures show the selective emitter regions 30 and the diffusion regions 31 are separate 30 regions, it will be understood that these are portion of a continuous emitter. Simultaneously, the phosphorous doping at the rear side 12 of the substrate 10 is diffused as well, so as to create a double-diffused field region 33.

18

Successful results have been obtained with a Boron vapour source for the diffusion. Two substrates are put back-to-back into the oven and heated at 900-1000°C for 30-120 minutes, for instance at 950 °C for 1 hours in an atmosphere 5 including an O2 and boron oxide (B2O3) vapor. As explained above, this B2O3 vapor is typically in situ created from a Boron tribromide (BBr3) vapour in the presence of oxygen. The boron oxide vapour reacts with the silicon surface to create elemental boron and silicon oxide. The elemental boron then 10 diffuses into the silicon substrate.

The silicon oxide is typically contaminated with boron oxide, resulting in a borosilicate glass. After the termination of the diffusion treatment, the borosilicate glass is suitably removed. The removal of the borosilicate 15 glass may be effected either with an acid such as HF that will also remove at least part of the diffusion resistance layer 22. Alternatively, use can be made of hot water or any other known etchant which allows selective etching of the borosilicate glass. In the event that a boron-rich layer 20 develops in the selective emitter regions 30, it will be present directly at the substrate surface, in a thickness of typically at most 20 nm. A low temperature oxidation step may then be carried out to oxidize the silicon rich layer and a thin silicon layer below it. The effective selective 25 emitter region 30 is then recessed in the semiconductor substrate 10. The low temperature oxidation step will further create a new oxide on the front side 11 outside the selective emitter regions 30, if the diffusion resistance layer 22 has been removed completely. It has turned that 30 out, when applying conductors with screenprinting techniques, these oxides need not to be removed separately.

Fig. 5 shows the substrate 10 in a fifth stage, after the provision of a trench 35 on the rear side and the 19 application of a passivation layer 32A, 32B on both the front side 11 and the rear side 12. The trench 35 is provided so as to prevent any short-circuit between the double-diffused field region 33 and the conductor to be 5 provided in the through-hole 20. The passivation layer suitably comprises SiN, as known to the skilled person, but alternative materials are by no means excluded. It goes without saying that the passivation layers 32A, 32B could be applied in separate steps and then do not need to have 10 identical composition. The passivation layer 32A, 32B may be applied as well in the through-hole 20, on top of the diffusion resistance layer 22. Suitably, the process is tuned so as to achieve higher growth rates on the front side 11 and/or on the rear side 12 than in the through-hole 20.

15 Instead of growing the passivation layer 32A, 32B into the through-hole, a separate barrier layer could be applied.

Instead of applying a nitride passivation layer, stacks of amorphous silicon layers may be deposited on the front side 11 and optionally on the rear side 12. These amorphous 20 silicon layers are suitably deposited by Plasma enhanced chemical vapour deposition (PECVD), for instance in a parallel plate plasma deposition driven by a 13.5 MHz power source, or in an inductively coupled plasma PECVD set up.

The thickness of amorphous silicon layers is suitably 20 nm 25 or less, more preferably 10 nm or less. The stacks comprise an intrinsic layer and a p-doped layer on the front side 11, and an intrinsic layer and a n-doped layer at the rear side 12. It has turned out that such amorphous silicon layers not only act as passivation layers, but also result in silicon 30 heterojunction solar cells.

Instead of or in addition to creating a trench 35 after completion of the diffusion processes, the field diffusion region could be locally removed prior to the boron 20 diffusion, acting as a further diffusion of the phosphorous as well.

Fig. 6 shows the resulting photovoltaic device 100, after that conductors 40, 41 and terminals 51, 52 have been 5 applied. The conductors include a via 40, i.e. the filled through-silicon through-hole and the conductor 41 on the front side 11. The conductor 41 on the front side 11 suitably comprises silver, the via 40 for instance comprises a silver/aluminum alloy or silver. Such type of conductors 10 are typically applied using a metal paste by screenprinting in a process known in the art, as deemed most beneficial from a cost perspective. The screenprinting paste applied on the front side 11 is typically an acid-containing screenprinted paste that is able, upon heating, to etch away 15 underlying layers, i.e. portions of the passivation layer 32A and the diffusion resistance layer 22. The screenprinting paste applied in the via 40 is suitably free of acid, so as to ensure that the diffusion resistance layer 22 and any optionally applied barrier layer is not removed. 20 The screenprinted pastes are typically fired after their application. However, alternative manufacturing processes as known in the art are not excluded from the scope of the present invention.

The present photovoltaic cell device 100 is provided 25 with first terminals 51 and second terminals 52. It is observed that typically a plurality of both the first terminals 51 and the second terminals 52 are present on the rear side 12 of the substrate 10. The first terminals 51 are electrically connected to the vias 40; the second terminals 30 52 are electrically coupled to the field region 13. It is suitable that the field region 13 is contacted in a distributed pattern, for instance in the form of a star, H-shape or the like. The shape may be optimized to reduce 21 series resistance to the field region 13 and to reduce metal consumption. The second terminals 52 may comprise such distributed contacts. Alternatively, an additional layer may be provided for the definition of such contacts. Suitably, 5 both the first and the second terminals 51, 52 are substantially dot-shaped where contact will be made to a conductor in a panel carrier, which is known per se as a back sheet foil. Suitably, the processing is carried out such that both terminals are applied in a single process 10 step. Therefore, most suitably, the via 40 extends to the same level as the substrate 10.

Fig. 7 shows on a larger scale the device as shown in Fig. 6, with additionally the subdivisions 151, 152 applied as trenches into the semiconductor substrate 10 from the 15 first side 11 and from the second side 12. These trenches 151, 152 clearly indicate the arrangement of the photovoltaic cell device 100 with a plurality of subcells 200. The subcells 200 are mutually mechanically coupled through the intermediate region 35 of the substrate 10. The 20 first doped regions 31 and second doped regions 33 are however mutually insulated through the subdivisions 151, 152 .

Instead or in addition to the application of trenches, the field region 13B may be provided in accordance with a 25 predefined pattern, which defines the subdivisions 152. This patterned application is suitably implemented by application of a mask on the second side 12 prior to phosphorous doping. One way of application such mask is wet-chemically, for instance using a sol-gel material, more particularly a spin-30 on-glass material, as known per se. The spin-on-glass material may herein be provided by printing, for instance inkjetprinting. In addition to defining the subcells, the mask may be used as an alignment feature. Such a mask 22 suitably withstands etching of the phosphosilicate glass (PSG) needed after the doping step. It may then be used as a protection layer against parasitic boron diffusion in the boron diffusion step.

5 In a similar manner, a mask could be applied on the first side 11 prior to the boron diffusion, so as to prevent the diffusion of boron into the subdivisions 151.

In accordance with the invention, the substrate is divided into a plurality of subcells that are located 10 adjacent of each other. The subcells are to be integrated into a circuit or string. As specified in WO2010/037393, such subdivision enables first of all that the resulting output voltage is increased. This increase in output voltage makes the implementation of an efficient and suitable power 15 converter, particularly a DC-DC converter, much simpler. The W02010/037393 teaches the formation of a string of subcells (coupled in series) in particular. However, it is not deemed necessary that all subcells are coupled in series; any other circuit topology may be chosen. This may be done for 20 instance to reduce the impact of shadow effects.

In accordance with the invention, the mutual coupling of individual subcells is arranged in an interconnect level provided externally from the semiconductor substrate. Use can be made of a printed circuit board, a tape material, a 25 flexible printed circuit board material, bonding wires, or the like. Preferably, use is made of a sheet-like carrier with conductors. This simplifies the assembly process, which is typically carried out for a solar panel comprising a plurality of substrates, and hence large plurality of 30 subcells.

However, when each subcell would require separate assembly into the solar panel, assembly costs would go up rapidly. It is thus desired that the substrate remains a 23 single unit that can be assembled as such into the solar panel. The photovoltaic cell device as shown in Fig. 7 provides such functional subdivision without negative impact of electrical interaction between neighbouring subcells and 5 without disintegration of the substrate as a whole.

Fig 8 is a diagrammatical top view of a photovoltaic cell device 100 that in many aspects corresponds to the device shown in Fig. 7. For sake of clarity it is observed that some features are shown several times in this Fig.8, while 10 their reference numeral has been indicated merely once in view of clarity. The subcell 200 is herein delimited by subdivisions 151. Each subcell 200 comprises one or more through silicon vias 40 so as to connect a grid of conductors 41, 50 on the first side to the terminal 51 on 15 the rear side 12 (as shown in Fig. 7). The grid of conductors 41, 50 is coupled to the first doped region 31(not shown). As shown in Fig. 6, the first doped region 31 suitably comprises a selective emitter 30 with higher dopant concentration so as to act as an exposed contact to the 20 conductors 41, 50. The conductors 41 are in the form of straight lines at mutually equal distances. The conductors 41 suitably extend along and over the selective emitter regions. This is deemed beneficial so as to have minimum resistance. It is however not excluded that any other 25 pattern or grid for the conductors is chosen. Object is to ensure that the complete surface of the subcell 200 is adequately provided with a current connection in the form of conductors 41, 50. Furthermore, the number of vias 40 may be defined. A limited number of vias 40 per subcell 200 is 30 preferred so as to loose minimum surface area. However, a via 40 of a certain design (e.g. conductor material, diameter, substrate thickness) typically has a maximum current density. As a consequence, more than one via per 24 subcell may be necessary in certain designs. The subcell 200 of the present embodiment for instance has 4 vias, and the number could alternatively be 2, 3, 5, 6 or even more than 6.

5 Fig. 9 shows an alternative embodiment of the photovoltaic cell device 100 in accordance with the invention. This embodiment comprises subcells 200 arranged in subcell groups 300. The use of subcell groups 300 typically allows the reduction of size per subcell 200, such 10 that one via 40 per subcell 200 is a realistic design option. This embodiment furthermore allows to provide additional isolation 110 between the subgroups 300. In view of the larger scale of the subgroups 300, a number of trenches 110 can be provided into the substrate 10, or 15 isolation may be provided in an alternative manner. If trenches 110 were applied around each subcell 200, the cell device 100 would likely become too fragile to withstand assembly and logistics in sufficiently high yield. It is not necessary for a proper operation that the trenches 110 20 completely isolate the subgroup 300 from neighbouring subgroups .

The trenches 110 serve to isolate certain areas, such that the effective resistance for charge transport from between the groups 300 increases. Therewith the leakage 25 current path between one first doped region 31 (emitter) and a second doped region 33 (field region) in a neighbouring cell group 300 will reduce as compared to the intended current path between said first doped region 31 and the second doped region 33 within the same subcell. The location 30 of the trenches 110 is most suitably coupled to the location of selective emitter regions 30 when present. The effect of increased resistance is may be based on twofold microscopic effect: first an effectively longer path through the 25 intermediate region; secondly, a blocking and deviation of field lines, such that the charge carriers running through the substrate 10 (and particularly the intermediate region 35) are less deviated to the neighbouring subcell group.

5 Additionally, the trenches constitute interfaces that may reflect radiation.

In one embodiment, a first and a second neighbouring subcells 200 in different subcell groups 300 are coupled in parallel to each other, while the intermediate region is not 10 partially blocked by means of a trench or other isolation. Being coupled in parallel and hence to be operated on the same voltage level, there is no risk for deviating currents. The absence of any trench or other isolation then supports mechanical stability.

15 The subcell group 300 constitutes a string of subcells 200, which is preferably a series coupling of the subcells 200. This is considered suitable so as to simplify interconnection. It will however be clear to the skilled person that the string may comprise one or more sections 20 with subcells coupled in parallel within the string. Such parallel connection may be desired if not all subcells have the same size.

Fig. 10-13 are diagrammatical figures for representing the circuit topology used in the photovoltaic cell device 25 in accordance with the invention. For reasons of clarity each individual subcell has been numbered herein as Cl to C16. The arrows depict the order in which the subcells are organized in a string. It will be clear that one string corresponds to one subcell group.

30 Fig. 10 shows diagrammatically a simple order in which a photovoltaic cell device 100 is subdivided into 9 subcells C1-C9 that constitute a string. The string is suitably implemented such that the second terminal of a first cell 26 (Cl) is connected via the backsheet to the first terminal of a second cell (C2). With a voltage gain of approximately 0.6V per subcell, the current is approximately 2A. The voltage difference between neighbouring subcells is at most 5 3V, particularly between subcells Cl and C6 and between subcells C4 and C9. A resulting leakage current between these subcells will be at most 9 mA. The overall leakage current will then be between 10 and 40 mA. This corresponds to 0.5 to 2% of the current, which is a minor loss. For a 10 panel with 35 cells, this leads to the option to design a topology based on 5 parallel strings of 7 cells in series. The overall voltage gain is then 35V, and the resulting current 10A. Without subcells, the voltage difference in one cell would still have been 0.6V, while the current is 18A.

15 The maximum achievable voltage gain, with a single string is then 21V. A single string is however very sensitive to shadow effects and local malfunctioning of a cell or assembly connection.

Fig. 11 and 12 show diagrammatically two embodiments of 20 a photovoltaic cell device 100 subdivided into two subcell groups 300 each with 8 subcells 200, C1-C8 and C9-C16. The Advantage of the configuration of Fig. 12 is that the neighbouring cells C2 and C9 are on the same voltage level. There is thus no need for provision of additional electrical 25 isolation means between them. The same holds for C4 and Cll, for C6 and C13, for C8 and C15, provided that indeed the input voltage for both subcell groups is identical. However, there is a voltage difference between Cl and C2 and between C9 and CIO of 4.2V. Moreover, the input of the string is on 30 the same side as the output of the string. For an arrangement with minimum conductors at assembly level - and thus minimum complexity and minimum losses at the assembly 27 level, it is preferred that the input and output of the string are on opposite sides of the subcell group.

Fig. 11 herein shows an alternatively. The voltage difference between subcells C2 and C9 is still identical to 5 zero, with the assumption of identical input voltages for both subcell groups. The maximum voltage difference between the subcells within a string is now 1.8V, and the input and output of the string are located on opposite sides of the subcell groups.

10 Fig. 13 shows a further embodiment, with three subgroups in a single photovoltaic cell device 100. The first group comprises the subcells C1-C6. The second group comprises the subcells C7-C12. The third group comprises the subcells C13-C18. The photovoltaic cell device 100 is herein 15 shows as a circular wafer. Typically this wafer is cut into a rectangular shape prior or subsequent to processing of the substrate to the photovoltaic cell device. It will be clear the provision of a rectangular shape results in loss of surface area. Such losses are reduced with a round, 20 hexagonal or octagonal shape, which shapes are however less easily to integrate into a panel without empty corners. The present Figure 13 demonstrates that the subcells do not need to have identical shape, even though in a single string surface area of a subcell is suitably constant. The Fig. 13 25 furthermore shows that a single photovoltaic cell device 300 may be subdivided into three groups, with variations in the layout. The advantage of using three subgroups per wafer is that there need not to be any straight line with trenches 110 across the substrate. This reduces the risk of cracking 30 of the substrate along such line.

Fig. 14-17 show consecutive stages of an alternative manufacturing method. While the preceding Figures showed subcell groups mutually isolated with trenches, this 28 alternative manufacturing method leads to trenches filled with oxide.

Fig. 14 shows a semiconductor substrate 10 with a first side 11 and an opposed side 12. A protecting layer 101 is 5 provided both on the first side 11 and on the second side 12. The protecting layer is suitably a nitride, such as silicon nitride as known to the skilled person.

Fig. 15 shows the substrate after a second stage in the manufacturing. Trenches 110 extending from the first side 11 10 to the second side 12 have been created herewith. Typically, use is made of a laser, but reactive ion etching may be used alternatively as known in the art.

Fig. 16 shows the substrate after a thermal oxidation treatment. The presence of the protecting layer 101 prevents 15 growth of a thermal oxide onto the first or the second side 11, 12 of the substrate 10. However, no protection is applied in the trench 110. As a consequence, the thermal oxide 111 will growth within the trench 110. It is observed that the silicon oxide has a lower density than silicon, 20 such that the trench 110 will be automatically filled with silicon oxide. Though not shown in the figure, thermal oxidation is based on silicon consumption and will lead to a thermal oxide 111 which is wider than the original trench 110. Moreover, while trenches are limited laterally so as to 25 maintain substrate integrity, the oxide will further develop in lateral directions. In other words, the thermal oxide may substantially circumfere a subcell or subcell group. Due to diffusion limitation, the oxide growth may be terminate before the silicon oxide on both sides of the original 30 trench has merged into a single body. This is indicated with the dashed line. It appears beneficial to leave a gap at the end of thermal oxidation; stresses could develop due to the difference in thermal expansion between silicon and silicon 29 oxide (smaller in silicon oxide) . If desired such gaps may be filled at a later stage, for instance with a low temperature oxide applied by chemical vapour deposition or in liquid form.

5 Fig. 17 shows the resulting photovoltaic cell device 100. After the provision of the thermal oxide, the protecting layer may be removed and processing is continued with the steps indicated in Fig. 1-6. It is observed that the protecting layer 101 could even be kept on the first 10 side 11 during provision of the second doped region 33 from the second side by means of phosphorous doping. There is then no need to remove the phosphorous doping again from the first side of the substrate 10. As shown in this Figure, the oxide 111 forms a border of an individual subcell 200. It 15 will be understood that the oxide 111 may alternative constitute a border of the subcell group.

Claims

Method for manufacturing a device with a photovoltaic cell, which cell is provided with a plurality of sub cells each provided with a pin diode, which method comprises the steps of: - Providing a semiconductor substrate with a first side and an opposite second side, C - Applying a plurality of first doped regions 10 of the second conductivity type to the first side of the substrate, wherein adjacent first doped regions are mutually separated by at least substantially insulating or semiconductive regions; - Providing a second doped region of the first conductivity type on the second side of the substrate, wherein an intermediate region extends between the first and the second doped regions, and wherein the second doped region is subdivided with at least substantially electrically insulating or semiconductor separations, which separations are arranged in accordance with the at least substantially electrically insulating or semiconductive regions on the first side of the substrate, with which the sub cells are defined

2. Method according to claim 1, wherein the second doped region is applied by applying charge carriers to form the second doped region and applying the separations in the second doped region by removing portions 30 of the semiconductor substrate, which subdivisions extend up to the intermediate area.

The method of claim 1, wherein the second doped region is applied by applying a mask to the second side of the semiconductor substrate, which mask defines the separations, and by applying charge carriers through the mask to form the subdivided second doped areas.

4. Method according to claim 1, wherein the first 10 doped regions are provided by defining selective emitter regions and diffusion regions, which selective emitter regions are provided with a higher doping concentration than the diffusion regions, and are positioned such that a diffusion region is located between one least substantially insulating or semiconductive region and a selective emitter region.

5. A method according to claim 1, wherein the various first doped regions are defined by doping the semiconductor substrate from the first side to form a first doped region and making subdivisions in the first doped region.

6. A photovoltaic cell device comprising a semiconductor substrate with a first side and an opposite second side, which device comprises a plurality of sub cells, each sub cell comprising a first doped region and a second doped region or opposed conductivity type and an intermediate region that extending between the first and the second doped region, which intermediate region is provided with charge carriers of a first conductivity type in a concentration lower than a concentration of charge carriers of the first type in the first or the second area, wherein the intermediate region is mechanically continuous between the sub-cells, and subdivisions are present between the second doped regions of neighboring sub-cells and in which substantially insulating or semiconductive regions are present between the first doped regions of neighboring sub-cells.

7. Device as claimed in claim 6, wherein the first doped regions comprise a selective emitter region and a diffusion region, which selective emitter region has a higher doping concentration than the diffusion region and has an interface with a conductor, and wherein a diffusion region is present between a selective emitter region and an at least substantially substantial insulating or semiconductive region.

8. Device as claimed in claim 6, wherein the sub cells are grouped in sub cell groups, and wherein the sub cells within a group form a string.

9. Device as claimed in claim 8, wherein intermediate regions between sub-cell groups contain electrically insulating regions.

10. Device as claimed in claim 9, wherein the at least substantially electrically insulating regions are formed by grooves (trenches) in the semiconductor substrate, which grooves define mechanical bridges between the subcell groups for mechanical continuity.

11. Device as claimed in claim 6 or 7, wherein each sub-cell comprises a first and a second contact, both located on the second side of the semiconductor substrate, and wherein the first contact is electrically connected to the first doped area on the first side with through silicon vias extending from the first to the second side of the semiconductor substrate and wherein the second contact is electrically connected to the second doped region on the second side. 10

The device of claim 11, wherein the sub-cells are cells of the metal-wrap-through (MWT) type.

13. Device as claimed in claim 6, wherein the surface area of a single subcell is in the range of 4 to 50 cm 2, preferably 6 to 40 cm 2.

14. Solar panel comprising a panel carrier provided with conductors and a plurality of devices with a photovoltaic cell according to one of the preceding Claims 6 to 13 with a first and a second contact on the second side, wherein the sub-cells are arranged in a circuit topology by the first and connecting the second contacts to each other with the conductors of the panel support according to a pattern corresponding to the circuit topology.

15. Solar panel according to claim 14, wherein the circuit topology is determined with an active DC circuit 30 that is controlled with a controller that is inserted into the solar panel.