NL194354B - A method of manufacturing a monolithic integrated circuit having at least one CMOS field effect transistor and one bipolar npn transistor. - Google Patents

A method of manufacturing a monolithic integrated circuit having at least one CMOS field effect transistor and one bipolar npn transistor.

Info

Publication number
NL194354B
NL194354B NL9400337A NL9400337A NL194354B NL 194354 B NL194354 B NL 194354B NL 9400337 A NL9400337 A NL 9400337A NL 9400337 A NL9400337 A NL 9400337A NL 194354 B NL194354 B NL 194354B
Authority
NL
Netherlands
Prior art keywords
manufacturing
integrated circuit
field effect
monolithic integrated
bipolar npn
Prior art date
Application number
NL9400337A
Other languages
Dutch (nl)
Other versions
NL9400337A (en
NL194354C (en
Inventor
Juergen Nagel
Original Assignee
Micronas Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE4319437A external-priority patent/DE4319437C1/en
Application filed by Micronas Gmbh filed Critical Micronas Gmbh
Publication of NL9400337A publication Critical patent/NL9400337A/en
Publication of NL194354B publication Critical patent/NL194354B/en
Application granted granted Critical
Publication of NL194354C publication Critical patent/NL194354C/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
NL9400337A 1993-03-05 1994-03-04 Method for manufacturing a monolithic integrated circuit with at least one CMOS field effect transistor and one bipolar npn transistor. NL194354C (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
DE4306932 1993-03-05
DE4306932 1993-03-05
DE4319437A DE4319437C1 (en) 1993-03-05 1993-06-11 BiCMOS monolithic IC mfr. - avoids need for epitaxial and buried layers
DE4319437 1993-06-11
US37175695 1995-01-12
US08/371,756 US5525825A (en) 1993-03-05 1995-01-12 Monolithic integrated circuit with at least one CMOS field-effect transistor and one npn bipolar transistor

Publications (3)

Publication Number Publication Date
NL9400337A NL9400337A (en) 1994-10-03
NL194354B true NL194354B (en) 2001-09-03
NL194354C NL194354C (en) 2002-01-04

Family

ID=27204834

Family Applications (1)

Application Number Title Priority Date Filing Date
NL9400337A NL194354C (en) 1993-03-05 1994-03-04 Method for manufacturing a monolithic integrated circuit with at least one CMOS field effect transistor and one bipolar npn transistor.

Country Status (3)

Country Link
JP (1) JP3426327B2 (en)
FR (1) FR2702307B1 (en)
NL (1) NL194354C (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0270703B1 (en) * 1986-12-12 1991-12-18 Deutsche ITT Industries GmbH Method of producing a monolithic integrated circuit comprising at least one bipolar planar transistor
DE68921995T2 (en) * 1988-01-19 1995-12-07 Nat Semiconductor Corp Method of manufacturing a polysilicon emitter and a polysilicon gate by simultaneously etching polysilicon on a thin gate oxide.

Also Published As

Publication number Publication date
JPH0758227A (en) 1995-03-03
NL9400337A (en) 1994-10-03
JP3426327B2 (en) 2003-07-14
FR2702307B1 (en) 1995-08-18
FR2702307A1 (en) 1994-09-09
NL194354C (en) 2002-01-04

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Legal Events

Date Code Title Description
BC A request for examination has been filed
DNT Communications of changes of names of applicants whose applications have been laid open to public inspection

Free format text: MICRONAS INTERMETALL GMBH

DNT Communications of changes of names of applicants whose applications have been laid open to public inspection

Free format text: MICRONAS GMBH

V1 Lapsed because of non-payment of the annual fee

Effective date: 20071001