NL166558B - Binaire rekenschakeling voor twee operanden, voorzien van twee trekkerregisters. - Google Patents

Binaire rekenschakeling voor twee operanden, voorzien van twee trekkerregisters.

Info

Publication number
NL166558B
NL166558B NL6516539.A NL6516539A NL166558B NL 166558 B NL166558 B NL 166558B NL 6516539 A NL6516539 A NL 6516539A NL 166558 B NL166558 B NL 166558B
Authority
NL
Netherlands
Prior art keywords
operands
tractor
registers
binary calculation
binary
Prior art date
Application number
NL6516539.A
Other languages
English (en)
Other versions
NL166558C (nl
NL6516539A (nl
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of NL6516539A publication Critical patent/NL6516539A/xx
Publication of NL166558B publication Critical patent/NL166558B/nl
Application granted granted Critical
Publication of NL166558C publication Critical patent/NL166558C/nl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
NL6516539.A 1964-12-23 1965-12-20 Binaire rekenschakeling voor twee operanden, voorzien van twee trekkerregisters. NL166558C (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US420568A US3417236A (en) 1964-12-23 1964-12-23 Parallel binary adder utilizing cyclic control signals

Publications (3)

Publication Number Publication Date
NL6516539A NL6516539A (nl) 1966-06-24
NL166558B true NL166558B (nl) 1981-03-16
NL166558C NL166558C (nl) 1981-08-17

Family

ID=23667003

Family Applications (1)

Application Number Title Priority Date Filing Date
NL6516539.A NL166558C (nl) 1964-12-23 1965-12-20 Binaire rekenschakeling voor twee operanden, voorzien van twee trekkerregisters.

Country Status (8)

Country Link
US (1) US3417236A (nl)
BE (1) BE672601A (nl)
CH (1) CH439809A (nl)
DE (1) DE1499227C3 (nl)
ES (1) ES321002A1 (nl)
FR (1) FR1464946A (nl)
GB (1) GB1097085A (nl)
NL (1) NL166558C (nl)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3582902A (en) * 1968-12-30 1971-06-01 Honeywell Inc Data processing system having auxiliary register storage
NL6908710A (nl) * 1969-06-07 1970-12-09
US3631400A (en) * 1969-06-30 1971-12-28 Ibm Data-processing system having logical storage data register
US3811039A (en) * 1973-02-05 1974-05-14 Honeywell Inf Systems Binary arithmetic, logical and shifter unit
US4254471A (en) * 1978-04-25 1981-03-03 International Computers Limited Binary adder circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2936116A (en) * 1952-11-12 1960-05-10 Hnghes Aircraft Company Electronic digital computer
US3008639A (en) * 1954-04-16 1961-11-14 Ibm Electronic accumulator in which the component trigger circuits are operated relatively continuously
US3028088A (en) * 1956-09-25 1962-04-03 Ibm Multipurpose logical operations
US3056552A (en) * 1959-01-28 1962-10-02 Ibm Asynchronous parallel adder deriving intermediate sums and carries by repeated additions and multiplications
US3235718A (en) * 1962-10-25 1966-02-15 Burroughs Corp Magnetic device for performing complex logic functions
US3249747A (en) * 1963-06-14 1966-05-03 North American Aviation Inc Carry assimilating system
US3320410A (en) * 1964-06-09 1967-05-16 Sperry Rand Corp Register including inter-stage multivibrator temporary storage

Also Published As

Publication number Publication date
DE1499227A1 (de) 1969-10-02
DE1499227C3 (de) 1975-09-18
US3417236A (en) 1968-12-17
BE672601A (nl) 1966-03-16
DE1499227B2 (de) 1975-02-06
FR1464946A (fr) 1967-01-06
GB1097085A (en) 1967-12-29
ES321002A1 (es) 1966-06-01
CH439809A (de) 1967-07-15
NL166558C (nl) 1981-08-17
NL6516539A (nl) 1966-06-24

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Legal Events

Date Code Title Description
V1 Lapsed because of non-payment of the annual fee