NL1026088C2 - Sound signal generating device and method for reducing pop noise. - Google Patents

Description

Brief indication: Sound signal generating device and method for reducing pop noise.

BACKGROUND OF THE INVENTION

1. Field of the invention

The invention is directed to an audio signal generating device and a method for reducing pop noise in a class D amplifier.

2. Explanation of the state of the art

Audio signal amplifiers used for amplifying audio signals are generally classified into classes A, AB, B, C and D, depending on their operational state during the power amplification stage.

Among the different classes of audio signal amplifiers, the class D amplifiers are more popular because their efficiency is higher than that of class AB amplifiers and their linearity is moreover superior due to little cross talk.

Class D amplifiers are also called switch-mode amplifiers because they resemble switch-mode voltage regulators. A class D amplifier uses a pulse width modulation (PWM) method performed on an analog input signal or digital PCM signal. This means that an analog input signal is modulated by a higher frequency modulation or carrier signal, usually a saw-tooth triangle wave, or a digital PCM input signal is converted into a related PHM signal. After pulse width modulation, the analog input signal or the digital PCM signal is discrete or digital, with pulse widths being used to display signal strengths from the original input signal.

The PWM signal presented to the amplifier is a high-frequency digital signal with varying widths. A low band pass filter is used to filter the high frequency component to extract the input signal and reduce switching noise.

FIG. 1 shows a waveform of input signals PWMA and PWMB, which are applied to a conventional class D amplifier, the pulse width modulating signals PWMA, PWMB having substantially the same pulse width but in opposite directions to each other. FIG. 2 shows I a waveform of a loudspeaker voltage VC1 when PWMA, PWMB and I power DET1 are applied (herein, DET1 changes from "Low" to I "High" / when the power is turned on). Fig. 2 shows # 5 that violent overshoot occurs at or near the time at which power is supplied. The overshoot is caused by the same pulse width of the pulse width modulating signals PWMA, PWMB.

This overshoot voltage VCl on the speaker results in "click or I pop" noise. there is therefore a need for a device and method for generating PWM signals that make a class D amplifier work, but without the pop noise after applying power I or when power is supplied from the amplifier deleted.

I SUMMARY OF THE INVENTION

A circuit is provided for manipulating a first pulse width modulation (PWM) signal and a second PWM signal for delivery to an amplifier, the first PWM signal having the same phase as the second PWM signal or with the second PWM signal I has an opposite phase relationship, the circuit comprising: a power detector for detecting switching on of the I power for the amplifier and for outputting a power I on signal; and a pulse generator comprising: a duty cycle generator for generating a first pulse signal corresponding to the first PWM signal and a second pulse signal corresponding to the second PWM signal; and a pulse reduction generator for generating a first pulse with a reduced width or a second pulse with a reduced width for delivery to the amplifier after receiving the power-on signal.

Preferably, the pulse generator further comprises a control for delivering the first pulse with reduced width or the second pulse with reduced width after receiving the power-on signal and for subsequently delivering the first pulse signal and the second pulse signal to the amplifier.

According to this embodiment, the circuit preferably further comprises a selection circuit for generating a selection signal for choosing between the first and second PWM signals during one selection mode and the signals from the pulse generator during a another selection mode, and a counter for determining the time after receiving the power-on signal and for issuing the select signal 1026088 "- 3 - in the other selection mode after reaching a predetermined count for outputting the first and second PWM signals to the amplifier, wherein the pulse width of the first pulse width with reduced pulse width is about half the pulse width of the first pulse signal.

According to an aspect of the invention, the circuit further comprises a delay for delaying the first pulse signal over a predetermined time in order to output a delayed first pulse signal, which pulse signal passes with a delay of the predetermined time around a time gap between the transition of provide the delayed first pulse signal and the transition from the second pulse signal, the amplifier including a series of transistors connected in series for receiving the first pulse signal and the second pulse signal at their gates.

According to another embodiment of the invention, a circuit is provided for manipulating a first pulse-wide temodulation (PWM) signal and a second PWM signal for delivery to an amplifier, the first PWM signal being the same phase as the second PWM signal. has a signal or has an opposite phase relationship with the second PWM signal, the circuit comprising: a power detector for detecting power off for the amplifier and for outputting a power-off signal; and a counter for counting the duration of the pulse width of the first PWM signal, the counter being activated after detection of the power-out signal, and for outputting a selection signal after reaching a predetermined time setting of the reduced width to cause a delivery of a first PWM signal with reduced pulse width or a second PWM signal with reduced pulse width before completing the power-off circuit of the amplifier. Preferably, the circuit further comprises a synchronization circuit for synchronizing the power-out signal using a system clock, the amplifier comprising a pair of transistors for receiving the first PWM signal and the second PWM signal on their ports .

The circuit further includes a mute circuit for outputting the selection signal to cause delivery of a first PWM signal with reduced pulse width or a second PWM signal with reduced pulse width after receiving a mute signal, 1026088-

I - 4 - I

I wherein the mute circuit is an AND gate, and wherein the first I

I PWM signal with reduced pulse width or the second PWM signal with I

I reduced pulse width the last I received by the amplifier

I pulse signal prior to completion of the power-off circuit I

I is 5, and wherein the reduced width is about half the I

I is width of the first PWM signal or the second PWM signal. I

According to yet another embodiment of the invention, an I

I circuit provided for manipulating a first pulse width I

I modulation (PWM) signal and a second PWM signal for delivery to an I

Amplifier, the first PWM signal being the same phase as the I

second PWM signal or with the second PWM signal opposite

I has a phase phase relationship, the circuit comprising: a power I

I detector for detecting power on for I

I the amplifier and for outputting a power-on signal and the I

15 detecting a power off for the amplifier I

I and outputting a power-out signal; a pulse generator with: I

a duty cycle generator for generating one with the first PWM-I

I signal corresponding to the first pulse signal and one to the second PWM-I

signal corresponding to second pulse signal and a reduced-wide I

20 counter generator for generating at least one of a first pulse I

I with a reduced width and a second pulse with a reduced I

I width; a controller for selecting one of the first pulse I

I with reduced width and the second pulse with reduced width I

I for delivery to the amplifier after receiving the power-on signal I

I sew and select the first pulse signal and the second I

pulse signal for subsequent delivery to the amplifier; and a counter I

I for counting the duration of the pulse width of the first PWM signal

Sew, the counter being activated after detection of the power

I gene out signal and a selection circuit for outputting an I

30 off selection signal after reaching a predetermined time set

For the reduced width around a delivery of one of a first

PWM signal with reduced width and a second PWM signal with I

cause reduced width, the selection circuit I

I further comprises a counter for counting the time after receipt of I

I the power-on signal and outputting a selection signal for I

I first delivering one of the first pulse with reduced width I

I and the second pulse with reduced width and then off

I giving the first pulse signal and the second pulse signal to the ver

I stronger. I

I 1026088 - 5 -

The circuit according to this embodiment further comprises a mute circuit for outputting the on-selection signal for outputting one of the first pulse with reduced width and the second pulse with reduced width after receiving a mute signal, wherein the mute circuit is synchronized using a system clock and after mute inactivation, to cause a delivery of one of the first PWM signal with reduced width and the second PWM signal with reduced width, the first pulse signal with reduced width has a pulse width of about half the pulse width of the first pulse signal, and wherein the predetermined time count of the reduced width is about half the duration of the pulse width of the first PWM signal .

The circuit according to this embodiment further comprises a delay for delaying the first pulse signal over a predetermined time in order to provide a delayed first pulse signal, which pulse signal passes with a delay of the predetermined time around a time gap between the transition of the delayed first pulse signal and the transition from the second pulse signal, wherein the amplifier includes a pair of transistors for receiving the delayed first pulse signal and the second pulse signal at its gates, and wherein the amplifier includes a pair of transistors for receiving the gates thereof receive the first pulse signal and the second pulse signal.

According to another aspect of the invention, a method is provided for manipulating a first pulse width modulation (PWM) signal and a second PWM signal for delivery to an amplifier, the first PWM signal being the same phase as the second PWM signal. has a signal or has a reverse phase relationship with the second PWM signal, the method comprising: detecting a power-on switch for the amplifier and outputting a power-on signal; and generating a first pulse signal corresponding to the first PWM signal and a second pulse signal corresponding to the second PWM signal; and generating a first pulse with reduced width or a second pulse with reduced width for delivery to the amplifier after receiving the power-on signal.

Preferably, the method further comprises delivering to the amplifier the first pulse of reduced width or the second pulse 1026088 * 1-6 -

I with reduced width after receiving the power-on signal and I

subsequently outputting the first pulse signal and the second pulse signal

sew on the amplifier, and generate a selection signal for I

selecting between the first and second PWM signals during one I

Selection mode and the selection between the first pulse signal and the I

I second pulse signal during another selection mode for delivery to I

the amplifier, the first pulse with reduced width being an I

I has pulse width of about half the pulse width of the I

first pulse signal. I

According to yet another aspect of this embodiment, I

I the method further delaying I over a predetermined time

I the first pulse signal to output a delayed first pulse signal

indicate which delayed first pulse signal passes with a through the I

I predetermined time-delayed time around a time gap between I

I transition of the delayed first pulse signal and the transition of I

I provide the second pulse signal, and the steps of: the detector

I derive a power off for the amplifier and I

Outputting a power-out signal; counting the duration I

I of the pulse width of the first PWM signal after detection of the I

Power-out signal; and outputting a selection signal after the I

I achieve a predetermined timeline of the reduced I

I width to give a first PWM signal with reduced I

I pulse width or a second PWM signal with reduced pulse width I

prior to completion of the power off for I

25 to cause the amplifier, the first PWM signal having the correct

reduced pulse width or the second PWM signal with reduced pulse I

I width it by the amplifier prior to completion of the output

circuit of the power received last pulse signal, and I

I wherein the reduced width is approximately half the width of I

I is the first PWM signal or the second PWM signal. I

According to yet another embodiment of the invention, I

I provides a circuit for manipulating a first pulse I

I width modulation (PWM) signal and a second PWM signal for delivery I

I to an amplifier, the first PWM signal having the same phase I

35 if the second PWM signal has or with the second PWM signal an I

has a reverse phase relationship, the circuit comprising: mid-I

for detecting power on for I

the amplifier and outputting a power-on signal and the de-I

detect a power off for the amplifier I

1026088-7 and outputting a power-out signal; means for generating a first pulse signal corresponding to the first PWM signal and a second pulse signal corresponding to the second PHM signal, and a reduced-width generator for generating at least one of a first pulse with a reduced width and a second pulse with a reduced width; means for selecting one of the first pulse with reduced width and the second pulse with reduced width for delivery to the amplifier after receiving the power-on signal and for selecting the first pulse signal and the second pulse signal for delivery to the amplifier amplifier; and a counter for counting the duration of the pulse width of the first PWM signal, the counter being activated after detection of the power-off signal, and a selection signal for outputting an out-selection signal after reaching a predetermined 15 reduction of the reduced width to cause a delivery of one of a first PWM signal with reduced width and a second PWM signal with reduced width.

SHORT DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will become more apparent when the detailed description of embodiments is read with reference to the accompanying drawings, in which: Fig. 1A shows a waveform of a PWM switching signal and Fig. 1B shows a class D amplifier; Fig. 2 shows an overspeed response of a loudspeaker voltage when used with the amplifier of Fig. 1; Fig. 3 shows a block diagram of a switching signal generating device according to an embodiment of the invention; FIG. 4 shows a circuit of a half-bridge type class D amplifier having one power source; Fig. 5A shows a circuit of a half-bridge type class D amplifier, which has two power sources; Fig. 5B is a circuit of a full-bridge type class D amplifier that has one power source; Fig. 6 shows a detailed block diagram of a pulse signal generating circuit of Fig. 3; Fig. 7 shows waveforms of a first detection signal DET1 and first and second pulse signals PUL1, PUL2 of the pulse signal generation circuit according to an embodiment of the invention; Fig. 8 shows switching waveforms at the moment of power-on for the switching signal generating device. Fig. 9 shows switching waveforms at the time of power-off for the switching signal generating device; Fig. 10 shows a block diagram of a switching signal generating device according to another embodiment of the invention; Fig. 11 shows switching waveforms at the time of mute switch-on I and mute switch-off for the switch signal generating device; Fig. 12 is a graph showing a response of speaker voltage in an audio sound regeneration device according to an I embodiment of the invention; Fig. 13 is a flowchart, which flowchart shows a method I of generating a switching signal according to an embodiment of the invention.

I 15

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. It should be noted that for the sake of simplicity of illustration I and explanation, the same reference numerals are used for

I designation of the same or equivalent parts or parts. I

FIG. 3 is a switching signal generating device 600 according to an I

I preferred embodiment of the invention. I

Referring to FIG. 3, the switching signal generation includes I

Direction 600 a power detection circuit 610, a pulse signal recording

I wake-up circuit 620, a first selection circuit 630, an audio signal

Signal processor 640, a second selection circuit 650 and a dead-time I

control circuit 660. I

The general operation of the switching signal generating device 600 I

30 is described herein. The power detection circuit 610 detects I

power-on circuit and indicates a first detection signal DET1 to I

the pulse signal generating circuit 620. The power detection circuit I

610 also detects an interruption of the power supply or power

gene-out circuit and outputs a second detection signal DET2, which I

The second detection signal is supplied to the audio signal processor 640

. The power detection circuit 610 receives a timing signal PPS for synchronizing timing signals of the input I

direction with a system clock. The period of the timing signal I

PPS corresponds to the period of time used by the audio signal processor I

1026088 - 9 - 640 generated PWM signals. Furthermore, the power detection circuit 610 generates a control signal SEL and outputs this control signal to the pulse signal generation circuit 620, the first selection circuit and the second selection circuit 650.

The pulse signal generation circuit 620 generates a first pulse signal PUL1 and a second pulse signal PUL2 in response to the first detection signal DET1 and the control signal SEL. A system clock signal can be used to synchronize the pulse signals POL1 and PUL2. According to at least one preferred embodiment of the invention, the pulse signals PUL1 and PUL2 are shaped by the pulse signal generation circuit 620 to be delivered in opposite phase and to initially have smaller pulse widths after applying the first detection signals DET1 to simultaneously switch on the prevent transistors in the audio sound regeneration circuit.

The audio signal processor 640 receives an audio input signal AUDIO and modulates the audio input signal AUDIO with a pulse train to output a pulse width modulated audio signal APWM, wherein the width of the pulses represents the strengths of the audio input signal. The audio signal processor 640 outputs the pulse width modulation period PPS and is preferably deactivated when the second detection signal DET2 is active, which signals off power.

The first selection circuit 630 selects the first pulse signal PUL1 or the pulse width modulated audio signal APWM in response to the control signal SEL and outputs a first selected signal MUXA

off. The second selection circuit 650 selects the second pulse signal PUL2 or the pulse width modulated audio signal APWM in response to the control signal SEL and outputs a second selected signal MUXB. Each output signal of the first and second selection circuits 630, 650 is therefore the pulse signal PUL1, PUL2 or the pulse width modulated audio signal APWM in opposite phase. The first and second selection circuits 630, 650 are preferably multiplexers.

The dead-time control circuit 660 receives the first and second selected signals MUXA, MUXB from the first and second selection circuits 630, 650, respectively. According to an embodiment of the invention, the dead-time control circuit 660 contains delay elements (not shown) for having a predetermined delay time delay of the switching signals.

The delay element is intended for delaying the first pulse signal with a predetermined time in order to produce a delayed first pulse signal, which delayed first pulse signal passes with a delay of the predetermined time to provide a time gap between the transition of the delayed first pulse signal I and the transition of the second pulse signal.

I The delay is preferably applied to the rising I (transition from low to high) edges of the MUXA and MUXB signals.

This dead time delay creates a time gap between the transition I 10 of the delayed first pulse signal and the transition of the second

I pulse signal for simultaneous activation or deactivation of the I

prevent transistors in an audio sound regeneration device. The I

Dead-time control circuit 660 gives first and second switching signals

PWMA, PWMB on the audio sound regeneration device. I

FIG. 4 shows a half-bridge type audio sound regeneration device

I 680, those two series-connected MOS transistors 101, 103, I

I two diodes M1, M2, a band pass filter with an inductance L and I

I comprises a capacitor C, and a loudspeaker 105. One connection from I

I is each of the diodes M1 and M2 with a source electrode of the transistor I

20 is connected and the other terminal of each of the diodes is with an I

drain electrode of the transistor. I

The first generated by the selection signal generating circuit 600

The first and second switching signals PWMA, PWMB are applied to the gate electrodes I

of the MOS transistors 101, 103 and are fed through with the I

25 first and second switching signals PWMA, PWMB corresponding MOS tranna

sistors 101, 103. Since the first and second I

switching signals PWMA and PWMB a sound component and a switching frequency

component, a low frequency band pass filter becomes I

used to filter out the switching frequency component in order to

30 audio signal. I

FIG. 5A shows an alternative audio sound regeneration device

which is of a half-bridge type with two transistors 101, 103, I

two power sources 1/2 Vdc, 1/2 Vdc, a band pass filter with an I

inductance L and a capacitor C, and a loudspeaker 105. FIG. 5B I

35 shows another audio sound regeneration device, that of a front I

bridge type is with one power source Vdc, four transistors 101, 103, I

301, 303 and a band pass filter L1, L2, C. For the person skilled in the art, the I

it will be clear that the audio sound regenerative applicable in the invention

device 680 not to the device shown in FIGS. 4, 5A and 5B

1026088 is limited, but each audio sound regenerator includes at least two transistors with respective gate electrodes for receiving switching signals PWMA, PWMB, and a low frequency band pass filter.

FIG. 6 is an example of a circuit diagram of the pulse signal generation circuit 620 of FIG. 3. This circuit receives as input the power-on detection signal DET1 and the signal SEL, which signals come from the power detection circuit 610, to generate pulse signals PUL1 and PUL2 . After transitioning from "Low" to 10 "High" of the DET signal, half-pulse generators 622 and 623 generate half-width initial pulses (quarter cycle) around the initial pulses of PUL1 and PÜL2 with a pulse width equal to half (½) of the pulse width of the modulated audio signal APWM. Then MUX 626 and MUX 627 are selected to pass the signals output from the 50:50 pulse generator 624, with an operating cycle similar to that of the system clock CLK and with the same period as that of the pulse period signal PPS. According to an alternative embodiment, only one of the two half-pulse generators 622 and 623 is used, depending on whether the transistors 101, 301, 103, 301 are NMOS or PMOS-type, so as to initially have a half pulse on PüL1 or Generate PUL2.

A controller 625 outputs the first pulse with reduced width or the second pulse with reduced width after receiving the power-on signal for subsequently delivering the first pulse signal and the second pulse signal to the amplifier.

FIG. 7 (a) shows waveforms of the first detection signal DET1 and the first and second pulse signals PUL1, PUL2 in the case that the MOS transistors 101, 303, 103, 301 of FIGS. 1 and 3 are NMOS transistors. FIG. 7 (b) shows waveforms of the first and second pulse signals PüL1, PUL2 which are applicable when the MOS transistors 101, 303 of FIGS. 1 and 3 are PMOS transistors and the MOS transistors 103, 301 NMOS transistors to be. It can be seen that the signals PUL1 and PDL2 are opposite in phase in FIG. 7 (a) and in phase in FIG. 7 (b).

FIG. 8 shows switching waveforms at a power-on switching moment for the switching signal generating device 600 and switching signals PWMA, PWMB. With the selection signal SEL initially at a "Low" logic level, the signals P11 and PUL2 are output via first selection circuit 630 and second selection circuit 650 as PWMA and PWMB.

1026088 · I - 12 -

The operation of the switching signal generating device 600 is shifted

I der described with reference to Figs. 3, 6, 7 and 8. When power I

If PW is supplied to the switching signal generating device 600, I

I the power detection circuit 610 the first detection signal DET1 with I

5 transition from logical level "Low" to logical level "High" on the I

I pulse signal generating circuit 620. The power detection circuit 610 I

I also gives a signal SEL, which initially has a logical level "Low" I

I has, at the pulse signal generation circuit 620, the first selection circuit I

Circuit 630 and the second selection circuit 650. I

The pulse signal generation circuit 620 generates the first pulse signal

I sew PUL1 and the second pulse signal PUL2 in response to the first one

Detection signal DET1, as shown in FIGS. 7 (a) and 7 (b). The au-I

I signal signal processor 640 gives the pulse width modulated audio signal

I sew APWM. I

The first selection circuit 630 returns the first selected I

I signal MUXA at the dead time control circuit 660 and the second I

I selected signal MUXB at the dead time control circuit 660 I

I in response to the "low" level of the control signal SEL. I

The dead-time control circuit 660 gives the first and second I

I switching signals PWMA, PWMB on the MOS transistors of the audio signal

I sound regeneration device 680 (FIGS. 4, 5A and 5B). I

7 (a) and 8 show that a width Tonf of a first I

Pulse 701 of the first pulse signal PUL1 is approximately Ton / 2 and I

is smaller than any width (Ton) of other pulses 702, 703, 704, I

705. The first pulse 701 represents a first generated pulse of I

the first pulse signal PÜL1 in the pulse signal generation circuit 620, when I

PW power is supplied. The pulses 703, 705 represent I

second and third pulses of the first pulse signal PUL1, respectively. I

The pulse 702 represents a first pulse of the second pulse signal I

PUL2 and the pulse 704 represent a second pulse of the second pulse I

signal PUL2. The pulse width is preferably Tonf of the first I

pulse 701 of the first pulse signal PUL1 approximately half of the I

width of the other pulses 702, 703, 704, 705. Furthermore, the I

width Tonf of the first pulse 701 of the first pulse signal PUL11

35 about a quarter (k) cycle of the other pulses 702, 703, 704. Each I

cycle (Tsw) of the other pulses 702, 703, 704, 705 is the same as I

a cycle of the pulse width modulated audio signal APWM. An I

The width of an (n) -th pulse is substantially the same as a width I

of an (n + 1) -th pulse. The gain on the transistor of a class D

1026088-1

The original pulse width 701 applied to the receiver (e.g. 101 in FIG. 4) serves to turn on the transistor at reduced energy after power supply, thus the pop noise is minimized since an excess response is minimized. Although the original pulse width of PUL1 or PUL2 is reduced to half a pulse width, as described, other pulse width reductions, such as a quarter to a third pulse width, may also be applicable to reducing pop noise.

After a predetermined time has elapsed, the control signal SEL is changed from logic "Low" to logic "High" and the pulse signal generation circuit 620 is disabled in response to the active (logic "High") control signal SEL. Next, the output signal of the audio signal amplifier 640, the pulse width modulated audio signal APWM, is selected by the first and second selection circuits 630 and 650 for delivery to the dead-time control circuit 660. According to an embodiment of the invention, the predetermined time set by a manufacturer as a default value or by a user as a random value. According to the embodiment shown in Fig. 8, the predetermined time is approximately 2½ cycles.

The dead-time control circuit 660 outputs the first and second switching signals PWMA, PWMB to the MOS transistors of the class D amplifiers 408 (FIGS. 4 and 5). According to an embodiment of the invention, the predetermined dead time (DT) is a time for protecting against simultaneous switching on or switching off of the MOS transistors 101, 103, 301, 303. The dead time control circuit 660 makes the width of at least one of the first and second switching signals PWMA, PWMB with the predetermined dead time (DT) smaller, thus preventing simultaneous switching on or switching off of the MOS transistors 101, 103, 301, 303. The dead-time control circuit 660 contains delay elements for implementing the delay (dead time) to make one or both of the switching signals PWMA and PWMB shorter in pulse width at the logic level "High". According to one embodiment, the delay is applied to the rising ranges of both switching signals PWMA and PWMB.

Referring to FIG. 8, the switching signal generating device 600 outputs the first and second switching signals PWMA, PWMB during the predetermined period "Tp" (or "start mode"). During the "Tp" period, the first and second switching signals PWMA, PWMB are substantially 1026088 "I - 14 -

same as the first and second pulse signals (PUL1, PUL2). After the I

I "Tp" period gives the switching signal generating device 600 the first and second switching signals PWMA, PWMB during a "Ta" period (or "sound

I PWM mode "). During the" Ta "period, the first and second are I

PWMA, PWMB substantially the same as the pulse width value

I modulated APWM audio signal. According to an embodiment of the I

In accordance with this invention, the pulse widths 702, 704 of the second switching signal I are

PWMB smaller than the pulses 703 and 705 of the PWMA signal, preferably I

I test with a quantity of 2 * DT, compared to the switching signal I

I 10 PWMA.

Protective I applicable to the switch-off of the amplifier

Measures are described with reference to Fig. 9, which Figs

I your switching waveforms at a time of switching off before the damage

1 shows a signal-generating device 600. I

According to a preferred embodiment of the invention, the I

I audio signal processor 640 on periods Toni, Ton2 of the APWM I signal

I and the audio signal processor 640 gives an estimated value PPS to the I

I power detection circuit 610. The pulse period is preferably I

I or duration of each cycle of the first and second switching signals PWMA, I

PWMB is substantially constant and the on periods Toni, Ton2 are variable I

I according to an audio signal AUDIO. The cycle duration is preferably 1

I estimate using a counter (not shown). I

The counter preferably counts the time after receipt of the power

I-on signal in order to put the selection signal in another selection mode

I, therefore, to issue for I after reaching a predetermined count

Outputting the first and second PWM signals to the amplifier. I

The counter preferably counts the duration of the pulse width of the I

first PWM signal, the counter being activated after detection I

I of the power-out signal, for outputting a selection signal I

After reaching a predetermined reduced-width time frame

In order to deliver a first PWM signal with reduced I

I pulse width or a second PWM signal with reduced pulse width te I

I cause to switch off the power of the amplifier

I complete. I

This counter value can be stored in a buffer unit (not shown)

I are stored and the buffer is every cycle with the estimated I

I updated PPS value. The estimated PPS value is used for the I

Controlling a pulse width 903 to reduce pop noise when I

The supplied power PW is switched off, that is, the power PW changes from level "High" to level "Low".

During power off, the power detection circuit 610, the pulse signal generation circuit 620, and the audio signal processor 640 may be disabled. The * power detection circuit 610 detects the power off and outputs a second detection signal DET2 to the audio signal processor 640. The audio signal processor 640 stops the operation of pulse width modulation in response to the second detection signal DET2. According to an embodiment of the invention, the second detection signal DET2 is changed to a logic level "Low" (or deactivated) with a reduced pulse width, preferably half of the on period Ton2 or quarter cycle. The width of a pulse 903 is therefore smaller than the width Ton2 of the pulse 902, the pulse 903 being the last pulse before the power cut-out. Preferably, the width of the pulse 903 is substantially half a width of the pulse 902 or a quarter of a period of a normal cycle of the first switching signal PWMA or the second switching signal PWMB. The reduced pulse width is a function of the counter value stored in the buffer. For example, a one-third pulse width in pulse 903 is obtained by transitioning from DET2 from "High" to "Low" at one-third of the time value stored in the buffer.

FIG. 10 is a block diagram of a switching signal generating device 1000 according to another embodiment of the invention. The switch signal generating device 1000 controls an on period of first and second switching signals PWMA, PWMB in response to a mute signal / MUTE.

Referring to FIG. 10, the switch signal generation device 1000 includes a power detection circuit 610, a pulse signal generation circuit 620, a first selection circuit 630, an audio signal processor 641, a second selection circuit 650, a dead-time control circuit 660, and a logic gate 1110.

The power detection circuit 610 detects a supplied power PW and generates a pre-control signal PSEL. The pre-control signal PSEL is input to one of two inputs of the logic gate 1110. The output signal of the logic gate 1110 is a control signal SEL, which functions similarly to the SEL signal in FIG. 3 to switch between POLI and PUL2. or select APWM as output signals from the selectors 630 and 650, respectively.

1026088-1 I - 16 -

The audio signal processor 641 gives a mute control signal CMUTE

I at the logic gate 1110 in response to a mute signal / MUTE. The I audio signal processor 641 controls the time in which CMUTE is active or inactive. The operations and functions of the audio signal processor 641 of the invention are substantially the same as those of the audio signal processor 640 in Fig. 3, with the exception of the possibility of transmitting the control signal (SEL) through the audio signal processor 641 via the I Disable CMUTE signal. According to the present embodiment, the logic gate 1110 is preferably an AND gate I10 or an equivalent gate of the AND gate. The logic gate 1110 receives the MUTE control signal CMUTE and the pre-control signal I PSEL, and generates a control signal SEL.

FIG. 11 shows mute-on and mute-off switching waveforms for the switching signal generating device 1000 in FIG. 10. Reference is now made to FIGS. 10 and 11 wherein, when the switching signal generating device I 1000 as a "sound pulse width modulating (PWM) mode" the I PSEL signal is at a "High" logic level and the mute I signal / MUTE is inactive at the "High" logic level (or "mute-out mode"). During the mute-out mode, the switching signal generating device 1000 outputs first and second switching signals PWMA, PWMB, which are substantially the same as the pulse width modulated audio signal APWM output from the audio signal processor 641.

When the mute signal / MUTE has passed to a logic level "Low" (or "mute-on mode"), the audio signal processor 641, in turn, outputs a mute control signal CMUTE to the logic gate 1110. When the mute control signal CMUTE has passed to a "Low" level, the control signal SEL goes to a "Low" level. During a PWM sound mode, the I pre-control signal is at a "High" level, the control signal passes SEL to the same logic level as the logic level of the mute control signal CMUTE. As in the above-described embodiment for turning off the power with reference to Fig. 9, the audio signal processor 641 estimates the pulse width I of an "on period" (Toni). The audio signal processor 641 can continue

35 generate the mute control signal CMUTE to the "on period" of the I

I last pulse 1103 with a reduced pulse width before the I

I mute control. I

The first selection circuit 630 and the second selection circuit

650 can be switched in response to the control signal SEL. At I

The first selection circuit 630 and the second selection circuit 650 are preferably switched when the pulse width Ton1f (or on period) of the pulse 1103 is smaller than the pulse width Toni (or on period) of the pulse 1101 is, preferably Tonlf is half of Toni.

The audio signal processor 641 outputs the pulse width modulated audio signal APWM. Thus, pop noise generated in the class D amplifier in response to the pulse 1103 is reduced.

When the mute-on mode changes to the mute-off mode, the mute signal / MUTE goes to a "High" logic level. The audio-10 signal processor 641 outputs the mute control signal CMÜTE to the AND-gate 1110 for causing the control signal to switch to a logic level "High" in response to the mute signal / MUTE. The audio signal processor 641 can therefore generate the mute control signal CMUTE to control the "on period" of pulse 1105.

The AND gate 1110 outputs the control signal SEL, which has a logic level "High", in response to the mute control signal CMUTE, which has a logic level "High", and the pre-control signal PSEL, which has a logical level "High".

The first selection circuit 630 and the second selection circuit 650 are switched in response to the control signal SEL, which has a logic level "High". The first selection circuit 630 and the second selection circuit 650 are switched when the pulse width Ton3f (or on period) of the pulse 1105 is smaller than the pulse width Ton3 (or on period) of the pulse 1107. According to a preferred embodiment of the invention, the on period of the pulse 1105 is about half the on period of the pulse 1107. Therefore, any pop noise that can be generated by the pulse 1105 will be less than pop noise that can be generated by pulse 1107.

FIG. 12 is a graph showing a response of the speaker voltage in an audio sound regeneration device according to an embodiment of the invention. The voltage Vel in Fig. 12 is smaller than the voltage Vel in Fig. 2 and the overshoot reaction is considerably reduced in comparison with the conventional overshoot reaction in Fig. 2. Using the switching signal generating device 600 or 1000 therefore makes pop noise for the audio signal generating device (class D amplifier) reduced.

FIG. 13 is a flowchart showing a method for generating a switching signal according to an embodiment of the invention. With reference to Figs. 3, 10 and 13, 1026088 'is first of all

I - 18 - I

I power turned on (Step 1400). The power detection circuit 610 I

detects whether the power is turned on (Step 1401). When the I

I power is on, the power detection circuit 610 gives I

I outputs a first detection signal DET1 (Step 1403). The pulse signal generation

Circuit 620 generates pulse signals POL1, POL2 (Step 1405). An ear I

The original first pulse 701 has half a width in equation I

I with pulses 702, 703, 704. I

The control I generated by the power detection circuit 610

I signal SEL passes from a logic level "Low" to a logic I

I 10 level "High" after the expiration of a predetermined period. The I

The predetermined period is a period for stabilizing the I

Pulse width generated by the audio signal processor 640 or 641

I modulated APWM audio signal. After the initial signals with reduced I

In the same width, regular pulse signals PDL1 and POL2 are output

15 (Step 1407). I

After stabilization of the pulse width modulated audio signal I

APWM become the first selection circuit 630 and the second selection circuit I

circuit 650 selected for PWM signals in the PWM sound mode in I

response to the control signal SEL, which is at the logic level I

I 20 "High" is to be dispensed (Step 1409). I

I When power PW is interrupted or switched off, I

The power detection circuit 610 turns off the power

And gives the power detection circuit 610 the second detection

I signal DET2 to the audio signal processor 640 (Step 1410). Like is I

I shown in FIG. 9, the second detection signal DET2 passes to I

an inactive level, when the last pulse width 903 is approximately the I

I is half the pulse width 902. Next, the PWM sound mode becomes I

stopped when the power is completely off (Step 1411). I

The audio signal processor 640 detects a state of the I

I 30 mute signal / MUTE and determines whether the mute signal / MUTE is in an I

I is in a muting state. If the mute signal / MOTE does not occur I

I is in a muted state, the switching signal generating I

I towards 1000 a PWM sound mode. When the switching signal I

I alarm device 1000 is in a muted state, the I

Audio signal processor 641 a mute control signal CMÜTE on the AND-I

I gate 1110, The first selection circuit 630 and the second selection circuit

The circuit 650 is switched in response to the control signal SEL. I

Although the invention herein with reference to the annexed I

I have described the accompanying drawings, it will be understood that the I

The invention is not limited to these embodiments, and that various other changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the invention. Such changes and modifications are contemplated within within the scope of the invention as defined by the appended claims.

1026088 “

Claims (25)

A circuit for manipulating a first pulse width modulation (PWM) signal and a second PWM signal for delivery to a II amplifier, the first PWM signal having the same phase as the II second PWM signal or with the second PWM signal has an opposite phase relationship, the circuit comprising: II a power detector for detecting power-on II for the amplifier and for outputting a II power-off signal; and II a counter for counting the duration of the pulse width of the first PWM signal, the counter being activated after detection of the power-out signal, and for outputting a II selection signal after reaching of a predetermined reduced width timing II to cause a delivery of a first PWM signal II with reduced pulse width or a second PWM signal with reduced pulse width II before completing the power-off circuit I of the amplifier. I The circuit of claim 1, further comprising a synchronizing circuit for synchronizing the power-out I signal using a system clock. I 20 The circuit of claim 1, wherein the amplifier includes an I pair of transistors for receiving at its gates from the first PWM signal and the second PWM signal. I 4. A circuit according to claim 1, further comprising a muting II circuit for outputting the selection signal about an outputting II of a first PWM signal with reduced pulse width or a second I PWM signal with reduced pulse width after receiving a mute II signal. I The circuit of claim 4, wherein the mute circuit is an AND gate. I 30 The circuit of claim 5, wherein the first PWM I signal with reduced pulse width or the second PWM signal with reduced pulse width is the last pulse I signal received by the amplifier prior to completion of the power-off circuit. I 102608-9 The circuit of claim 3, wherein the reduced width is approximately half the width of the first PWM signal or the second PWM signal. 8. Circuit for manipulating a first pulse width modulation (PWM) signal and a second PWM signal for delivery to an amplifier, the first PWM signal having the same phase as the second PWM signal or with the second PWM signal. signal has a reverse phase relationship, the circuit comprising: a power detector for detecting power on for the amplifier and for outputting a power on signal and detecting a power off for the amplifier and outputting a power-out signal; a pulse generator with: a duty cycle generator for generating a first pulse signal corresponding to the first PWM signal and a second pulse signal corresponding to the second PWM signal and a reduced width generator for generating at least one of a first pulse with a reduced width and a second pulse with a reduced width; a control for selecting one of the first reduced width pulse 20 and the second reduced width pulse for delivery to the amplifier after receiving the power on signal and for selecting the first pulse signal and the second pulse signal for subsequent deliver to the amplifier; and a counter for counting the duration of the pulse width of the first PWM signal, the counter being activated after detection of the power-off signal and a selection circuit for outputting an off-selection signal after reaching a predetermined reduced width timing to cause a delivery of one of a first PWM signal with reduced width and a second PWM signal with reduced width. 9. A circuit as claimed in claim 8, wherein the selection circuit further comprises a counter for counting the time after receiving the power-on signal and outputting a selection signal for first outputting one of the first pulse with reduced output. width and the second pulse with reduced width and subsequently outputting the first pulse signal and the second pulse signal to the amplifier. 1026088 "I 22" 10. A circuit as claimed in claim 8 / further comprising an I mute circuit for outputting the on-select signal for outputting one of the first pulse with reduced width and the second pulse with reduced width to the amplifier after receiving IS from a mute signal. The circuit of claim 10, wherein the mute circuit is synchronized using a system clock and after mute inactivation, to provide one of the first PWM signal with reduced width and the second PWM signal with reduced - cause the width to be specified. The circuit of claim 8, wherein the first reduced-width pulse I signal has a pulse width of about half I of the pulse width of the first pulse signal. I 13 PWM signal with reduced pulse width before completing the power off for the amplifier. The circuit of claim 8, wherein the predetermined I I IS timing of the reduced width is about half the duration I I of the pulse width of the first PWM signal. I 14. A circuit according to claim 8, further comprising a II delay for delaying the first pulse signal over a predetermined time in order to output a delayed first pulse signal, which pulse signal passes with a delay of the predetermined time around a time gap between the transition of the delayed II first pulse signal and the transition of the second pulse signal. I 15. A circuit according to claim 14, wherein the amplifier comprises an I pair of transistors for receiving at its gates the delayed first pulse signal and the second pulse signal. I The circuit of claim 8, wherein the amplifier includes an I pair of transistors for receiving at its gates the first pulse signal and the second pulse signal. I 30 A method of manipulating a first pulse width modulation (PWM) signal and a second PWM signal for delivery to a II amplifier, the first PWM signal having the same phase as the II second PWM signal or with the second PWM signal has an opposite phase relationship, the method comprising: detecting a power on for the I amplifier and outputting a power on signal; and I 1026081 - generating a first pulse signal corresponding to the first PWM signal and a second pulse signal corresponding to the second PWM signal; and generating a first reduced-width pulse or a second reduced-width pulse for delivery to the amplifier after receiving the power-on signal, the method further comprising the steps of: detecting a power-off power for the amplifier and outputting a power-out signal; 10 counting the duration of the pulse width of the first PWM signal after detection of the power-out signal; and outputting a selection signal after reaching a predetermined timing of the reduced width for outputting a first PWM signal with reduced pulse width or a second The method of claim 17, further comprising outputting the first pulse with reduced width or the second pulse with reduced width to the amplifier after receiving the power-on signal and then outputting the first pulse signal and the second pulse signal to the amplifier. The method of claim 17, further comprising generating a selection signal for selecting between the first 25 and second PWM signals during one selection mode and selecting between the first pulse signal and the second pulse signal during another selection mode for delivery to the amplifier. The method of claim 17, wherein the first pulse with reduced width has a pulse width of about half the pulse width of the first pulse signal. 20. AMENDED CONCLUSIONS 21. The method of claim 17, further comprising delaying the first pulse signal over a predetermined time to output a delayed first pulse signal, which delayed first pulse signal passes with a delay determined by the predetermined time about a time gap between the transition of the delayed first pulse signal and the transition of the second pulse signal. 102603 «- I 24 Η The method of claim 17, wherein the first PWM I signal with reduced pulse width or the second PWM signal with reduced pulse width receives the amplifier prior to completing the power shutdown by the amplifier Is the last pulse signal. The method of claim 17, wherein the reduced I width is approximately half the width of the first PWM signal or I the second PWM signal. The method of claim 17, further comprising outputting the selection signal to dispense a first PWM signal with reduced pulse width or a second PWM signal with reduced pulse width after receiving a mute signal causes. 25. Circuit for manipulating a first pulse-wide temodulation (PWM) signal and a second PWM signal for delivery to an amplifier, the first PWM signal having the same phase as the second PWM signal or with the second PWM signal has an opposite phase relationship, the circuit comprising: means for detecting power on for the amplifier and outputting a power-on signal I and detecting a power-on signal switching off the power for the I amplifier and outputting a power-out signal; Means for generating a first pulse signal corresponding to the first PWM signal I and a second pulse signal corresponding to the second PWM signal I, and a reduced-width generator for generating at least one of a first pulse with an I reduced width and a second pulse with a reduced width; I means for selecting one of the first pulse with reduced width and the second pulse with reduced width for delivery to the amplifier after receiving the power-on signal and I for selecting the first pulse signal and the second pulse signal for delivery to the amplifier; and I a counter for counting the duration of the pulse width of the first PWM signal, the counter being activated after detection of the power-out signal, and a selection circuit for I outputting an output selection signal after reaching a predetermined time of the reduced width to cause a delivery of one first PWM signal with reduced width and a second PWM signal with reduced width. 102908 «-