MY203042A - Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache - Google Patents

Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache

Info

Publication number
MY203042A
MY203042A MYPI2020004174A MYPI2020004174A MY203042A MY 203042 A MY203042 A MY 203042A MY PI2020004174 A MYPI2020004174 A MY PI2020004174A MY PI2020004174 A MYPI2020004174 A MY PI2020004174A MY 203042 A MY203042 A MY 203042A
Authority
MY
Malaysia
Prior art keywords
data
layer cache
level cache
computing device
processing unit
Prior art date
Application number
MYPI2020004174A
Other languages
English (en)
Inventor
Mola Jordi
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of MY203042A publication Critical patent/MY203042A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3471—Address tracing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
MYPI2020004174A 2018-02-23 2019-02-13 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache MY203042A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/904,072 US10496537B2 (en) 2018-02-23 2018-02-23 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache
PCT/US2019/017737 WO2019164710A1 (en) 2018-02-23 2019-02-13 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache

Publications (1)

Publication Number Publication Date
MY203042A true MY203042A (en) 2024-06-05

Family

ID=65520481

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2020004174A MY203042A (en) 2018-02-23 2019-02-13 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache

Country Status (16)

Country Link
US (1) US10496537B2 (https=)
EP (1) EP3740871B1 (https=)
JP (1) JP7221979B2 (https=)
KR (1) KR102645481B1 (https=)
CN (1) CN111742302B (https=)
AU (1) AU2019223883B2 (https=)
BR (1) BR112020013505A2 (https=)
CA (1) CA3088563A1 (https=)
ES (1) ES2927911T3 (https=)
IL (1) IL276652B2 (https=)
MX (1) MX2020008664A (https=)
MY (1) MY203042A (https=)
PH (1) PH12020551325A1 (https=)
SG (1) SG11202007582RA (https=)
WO (1) WO2019164710A1 (https=)
ZA (1) ZA202004083B (https=)

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KR102894139B1 (ko) * 2019-12-20 2025-12-03 에스케이하이닉스 주식회사 데이터 저장 장치 및 그 동작 방법
LU101767B1 (en) 2020-05-05 2021-11-05 Microsoft Technology Licensing Llc Recording a memory value trace for use with a separate cache coherency protocol trace
LU101770B1 (en) * 2020-05-05 2021-11-05 Microsoft Technology Licensing Llc Memory page markings as logging cues for processor-based execution tracing
LU101768B1 (en) * 2020-05-05 2021-11-05 Microsoft Technology Licensing Llc Recording a cache coherency protocol trace for use with a separate memory value trace
US12411774B2 (en) 2021-02-22 2025-09-09 Microsoft Technology Licensing, Llc Treating main memory as a collection of tagged cache lines for trace logging
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Also Published As

Publication number Publication date
JP7221979B2 (ja) 2023-02-14
IL276652B2 (en) 2023-09-01
US10496537B2 (en) 2019-12-03
PH12020551325A1 (en) 2021-09-01
AU2019223883A1 (en) 2020-07-23
EP3740871B1 (en) 2022-08-24
RU2020131078A3 (https=) 2022-03-23
AU2019223883B2 (en) 2023-07-13
ZA202004083B (en) 2021-09-29
BR112020013505A2 (pt) 2020-12-01
JP2021515312A (ja) 2021-06-17
CN111742302B (zh) 2025-08-26
EP3740871A1 (en) 2020-11-25
KR102645481B1 (ko) 2024-03-07
SG11202007582RA (en) 2020-09-29
WO2019164710A1 (en) 2019-08-29
US20190266090A1 (en) 2019-08-29
KR20200123187A (ko) 2020-10-28
CA3088563A1 (en) 2019-08-29
IL276652B1 (en) 2023-05-01
ES2927911T3 (es) 2022-11-11
MX2020008664A (es) 2020-09-22
CN111742302A (zh) 2020-10-02
RU2020131078A (ru) 2022-03-23
IL276652A (en) 2020-09-30

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