RU2020131078A3 - - Google Patents

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Publication number
RU2020131078A3
RU2020131078A3 RU2020131078A RU2020131078A RU2020131078A3 RU 2020131078 A3 RU2020131078 A3 RU 2020131078A3 RU 2020131078 A RU2020131078 A RU 2020131078A RU 2020131078 A RU2020131078 A RU 2020131078A RU 2020131078 A3 RU2020131078 A3 RU 2020131078A3
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RU
Russia
Application number
RU2020131078A
Other languages
Russian (ru)
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RU2773437C2 (ru
RU2020131078A (ru
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed filed Critical
Publication of RU2020131078A3 publication Critical patent/RU2020131078A3/ru
Publication of RU2020131078A publication Critical patent/RU2020131078A/ru
Application granted granted Critical
Publication of RU2773437C2 publication Critical patent/RU2773437C2/ru

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/3476Data logging
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Prevention of errors by analysis, debugging or testing of software
    • G06F11/362Debugging of software
    • G06F11/3636Debugging of software by tracing the execution of the program
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • G06F12/0897Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/3471Address tracing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885Monitoring specific for caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
RU2020131078A 2018-02-23 2019-02-13 Запись трассировки посредством регистрации входящих потоков в кэш нижнего уровня на основе элементов в кэше верхнего уровня RU2773437C2 (ru)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/904,072 US10496537B2 (en) 2018-02-23 2018-02-23 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache
US15/904,072 2018-02-23
PCT/US2019/017737 WO2019164710A1 (en) 2018-02-23 2019-02-13 Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache

Publications (3)

Publication Number Publication Date
RU2020131078A3 true RU2020131078A3 (https=) 2022-03-23
RU2020131078A RU2020131078A (ru) 2022-03-23
RU2773437C2 RU2773437C2 (ru) 2022-06-03

Family

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Also Published As

Publication number Publication date
JP7221979B2 (ja) 2023-02-14
IL276652B2 (en) 2023-09-01
US10496537B2 (en) 2019-12-03
PH12020551325A1 (en) 2021-09-01
AU2019223883A1 (en) 2020-07-23
EP3740871B1 (en) 2022-08-24
MY203042A (en) 2024-06-05
AU2019223883B2 (en) 2023-07-13
ZA202004083B (en) 2021-09-29
BR112020013505A2 (pt) 2020-12-01
JP2021515312A (ja) 2021-06-17
CN111742302B (zh) 2025-08-26
EP3740871A1 (en) 2020-11-25
KR102645481B1 (ko) 2024-03-07
SG11202007582RA (en) 2020-09-29
WO2019164710A1 (en) 2019-08-29
US20190266090A1 (en) 2019-08-29
KR20200123187A (ko) 2020-10-28
CA3088563A1 (en) 2019-08-29
IL276652B1 (en) 2023-05-01
ES2927911T3 (es) 2022-11-11
MX2020008664A (es) 2020-09-22
CN111742302A (zh) 2020-10-02
RU2020131078A (ru) 2022-03-23
IL276652A (en) 2020-09-30

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