KR102645481B1 - 상위 계층 캐시의 항목을 기반으로 하위 계층 캐시로의 유입을 로깅함으로써 트레이스 기록 - Google Patents
상위 계층 캐시의 항목을 기반으로 하위 계층 캐시로의 유입을 로깅함으로써 트레이스 기록 Download PDFInfo
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- KR102645481B1 KR102645481B1 KR1020207026919A KR20207026919A KR102645481B1 KR 102645481 B1 KR102645481 B1 KR 102645481B1 KR 1020207026919 A KR1020207026919 A KR 1020207026919A KR 20207026919 A KR20207026919 A KR 20207026919A KR 102645481 B1 KR102645481 B1 KR 102645481B1
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/362—Debugging of software
- G06F11/3636—Debugging of software by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3471—Address tracing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3476—Data logging
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/885—Monitoring specific for caches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/904,072 US10496537B2 (en) | 2018-02-23 | 2018-02-23 | Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache |
| US15/904,072 | 2018-02-23 | ||
| PCT/US2019/017737 WO2019164710A1 (en) | 2018-02-23 | 2019-02-13 | Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20200123187A KR20200123187A (ko) | 2020-10-28 |
| KR102645481B1 true KR102645481B1 (ko) | 2024-03-07 |
Family
ID=65520481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020207026919A Active KR102645481B1 (ko) | 2018-02-23 | 2019-02-13 | 상위 계층 캐시의 항목을 기반으로 하위 계층 캐시로의 유입을 로깅함으로써 트레이스 기록 |
Country Status (16)
| Country | Link |
|---|---|
| US (1) | US10496537B2 (https=) |
| EP (1) | EP3740871B1 (https=) |
| JP (1) | JP7221979B2 (https=) |
| KR (1) | KR102645481B1 (https=) |
| CN (1) | CN111742302B (https=) |
| AU (1) | AU2019223883B2 (https=) |
| BR (1) | BR112020013505A2 (https=) |
| CA (1) | CA3088563A1 (https=) |
| ES (1) | ES2927911T3 (https=) |
| IL (1) | IL276652B2 (https=) |
| MX (1) | MX2020008664A (https=) |
| MY (1) | MY203042A (https=) |
| PH (1) | PH12020551325A1 (https=) |
| SG (1) | SG11202007582RA (https=) |
| WO (1) | WO2019164710A1 (https=) |
| ZA (1) | ZA202004083B (https=) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10031834B2 (en) | 2016-08-31 | 2018-07-24 | Microsoft Technology Licensing, Llc | Cache-based tracing for time travel debugging and analysis |
| US11042469B2 (en) | 2017-08-28 | 2021-06-22 | Microsoft Technology Licensing, Llc | Logging trace data for program code execution at an instruction level |
| US10642737B2 (en) | 2018-02-23 | 2020-05-05 | Microsoft Technology Licensing, Llc | Logging cache influxes by request to a higher-level cache |
| WO2021061220A1 (en) * | 2019-09-24 | 2021-04-01 | Microsoft Technology Licensing, Llc | Logging trace data for program code execution at an instruction level |
| KR102894139B1 (ko) * | 2019-12-20 | 2025-12-03 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 그 동작 방법 |
| LU101767B1 (en) | 2020-05-05 | 2021-11-05 | Microsoft Technology Licensing Llc | Recording a memory value trace for use with a separate cache coherency protocol trace |
| LU101770B1 (en) * | 2020-05-05 | 2021-11-05 | Microsoft Technology Licensing Llc | Memory page markings as logging cues for processor-based execution tracing |
| LU101768B1 (en) * | 2020-05-05 | 2021-11-05 | Microsoft Technology Licensing Llc | Recording a cache coherency protocol trace for use with a separate memory value trace |
| US12411774B2 (en) | 2021-02-22 | 2025-09-09 | Microsoft Technology Licensing, Llc | Treating main memory as a collection of tagged cache lines for trace logging |
| WO2022177697A1 (en) * | 2021-02-22 | 2022-08-25 | Microsoft Technology Licensing, Llc | Cache-based trace logging using tags in an upper-level cache |
| US11561896B2 (en) | 2021-02-22 | 2023-01-24 | Microsoft Technology Licensing, Llc | Cache-based trace logging using tags in an upper-level cache |
| US20220269615A1 (en) * | 2021-02-22 | 2022-08-25 | Microsoft Technology Licensing, Llc | Cache-based trace logging using tags in system memory |
| LU500061B1 (en) * | 2021-04-20 | 2022-10-20 | Microsoft Technology Licensing Llc | Processor support for using cache way- locking to simultaneously record plural execution contexts into independent execution traces |
| US12072803B1 (en) * | 2022-06-30 | 2024-08-27 | Advanced Micro Devices, Inc. | Systems and methods for tracking data cache miss requests with data cache tags |
| US12585469B2 (en) | 2024-04-04 | 2026-03-24 | Apple Inc. | Trace cache access prediction and read enable |
| US12547409B2 (en) | 2024-04-04 | 2026-02-10 | Apple Inc. | Trace cache that supports multiple different trace lengths |
| CN121029641B (zh) * | 2025-10-31 | 2026-03-17 | 砺算科技(上海)有限公司 | 处理器及其数据缓存方法、电子设备、存储介质 |
Citations (1)
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| US20170052876A1 (en) | 2015-08-18 | 2017-02-23 | Telefonaktiebolaget L M Ericsson (Publ) | Method for observing software execution, debug host and debug target |
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| US10642737B2 (en) | 2018-02-23 | 2020-05-05 | Microsoft Technology Licensing, Llc | Logging cache influxes by request to a higher-level cache |
-
2018
- 2018-02-23 US US15/904,072 patent/US10496537B2/en active Active
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2019
- 2019-02-13 MX MX2020008664A patent/MX2020008664A/es unknown
- 2019-02-13 AU AU2019223883A patent/AU2019223883B2/en active Active
- 2019-02-13 WO PCT/US2019/017737 patent/WO2019164710A1/en not_active Ceased
- 2019-02-13 SG SG11202007582RA patent/SG11202007582RA/en unknown
- 2019-02-13 ES ES19707256T patent/ES2927911T3/es active Active
- 2019-02-13 CN CN201980014858.4A patent/CN111742302B/zh active Active
- 2019-02-13 BR BR112020013505-4A patent/BR112020013505A2/pt not_active IP Right Cessation
- 2019-02-13 EP EP19707256.4A patent/EP3740871B1/en active Active
- 2019-02-13 CA CA3088563A patent/CA3088563A1/en active Pending
- 2019-02-13 MY MYPI2020004174A patent/MY203042A/en unknown
- 2019-02-13 JP JP2020544520A patent/JP7221979B2/ja active Active
- 2019-02-13 KR KR1020207026919A patent/KR102645481B1/ko active Active
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2020
- 2020-07-03 ZA ZA2020/04083A patent/ZA202004083B/en unknown
- 2020-08-11 IL IL276652A patent/IL276652B2/en unknown
- 2020-08-20 PH PH12020551325A patent/PH12020551325A1/en unknown
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170052876A1 (en) | 2015-08-18 | 2017-02-23 | Telefonaktiebolaget L M Ericsson (Publ) | Method for observing software execution, debug host and debug target |
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| Title |
|---|
| DONGYOON LEE et al, "Offline symbolic analysis for multi-processor execution replay", MICROARCHITECTURE, 2009, 42nd ANNUALIEEE/ACM International Symposium on. IEEE, (2009.12.12.) |
| Watson Robert N M 외, "CHERI : A Hybrid capability-system architecture for scalable software compartmentalization", 2015 IEEE SYMPOSIUM on Security AND Privacy, IEEE, (2015.5.17.) |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7221979B2 (ja) | 2023-02-14 |
| IL276652B2 (en) | 2023-09-01 |
| US10496537B2 (en) | 2019-12-03 |
| PH12020551325A1 (en) | 2021-09-01 |
| AU2019223883A1 (en) | 2020-07-23 |
| EP3740871B1 (en) | 2022-08-24 |
| RU2020131078A3 (https=) | 2022-03-23 |
| MY203042A (en) | 2024-06-05 |
| AU2019223883B2 (en) | 2023-07-13 |
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