MY174573A - Controlling an order for processing data elements during vector processing - Google Patents

Controlling an order for processing data elements during vector processing

Info

Publication number
MY174573A
MY174573A MYPI2015700010A MYPI2015700010A MY174573A MY 174573 A MY174573 A MY 174573A MY PI2015700010 A MYPI2015700010 A MY PI2015700010A MY PI2015700010 A MYPI2015700010 A MY PI2015700010A MY 174573 A MY174573 A MY 174573A
Authority
MY
Malaysia
Prior art keywords
order
register
processing
stream
vector instructions
Prior art date
Application number
MYPI2015700010A
Other languages
English (en)
Inventor
Alastair David Reid
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of MY174573A publication Critical patent/MY174573A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G06F8/4451—Avoiding pipeline stalls
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G06F9/4451—User profiles; Roaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
MYPI2015700010A 2012-07-11 2013-06-11 Controlling an order for processing data elements during vector processing MY174573A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/546,227 US9098265B2 (en) 2012-07-11 2012-07-11 Controlling an order for processing data elements during vector processing

Publications (1)

Publication Number Publication Date
MY174573A true MY174573A (en) 2020-04-27

Family

ID=48670609

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2015700010A MY174573A (en) 2012-07-11 2013-06-11 Controlling an order for processing data elements during vector processing

Country Status (9)

Country Link
US (1) US9098265B2 (enExample)
EP (1) EP2872988B1 (enExample)
JP (1) JP6236443B2 (enExample)
KR (1) KR102071272B1 (enExample)
CN (1) CN104487941B (enExample)
GB (1) GB2517877B (enExample)
IL (1) IL236572A (enExample)
MY (1) MY174573A (enExample)
WO (1) WO2014009689A2 (enExample)

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GB2543554B (en) * 2015-10-22 2019-01-23 Advanced Risc Mach Ltd Handling exceptional conditions for vector arithmetic instruction
CN111580863B (zh) * 2016-01-20 2024-05-03 中科寒武纪科技股份有限公司 一种向量运算装置及运算方法
US10762164B2 (en) 2016-01-20 2020-09-01 Cambricon Technologies Corporation Limited Vector and matrix computing device
GB2548601B (en) * 2016-03-23 2019-02-13 Advanced Risc Mach Ltd Processing vector instructions
GB2549737B (en) * 2016-04-26 2019-05-08 Advanced Risc Mach Ltd An apparatus and method for managing address collisions when performing vector operations
GB2552154B (en) * 2016-07-08 2019-03-06 Advanced Risc Mach Ltd Vector register access
GB2552153B (en) * 2016-07-08 2019-07-24 Advanced Risc Mach Ltd An apparatus and method for performing a rearrangement operation
EP3336691B1 (en) 2016-12-13 2022-04-06 ARM Limited Replicate elements instruction
EP3336692B1 (en) * 2016-12-13 2020-04-29 Arm Ltd Replicate partition instruction
KR102343652B1 (ko) 2017-05-25 2021-12-24 삼성전자주식회사 벡터 프로세서의 서열 정렬 방법
CN107291425B (zh) * 2017-06-23 2020-11-24 上海兆芯集成电路有限公司 合并解决重命名尺寸问题的部分写入结果的系统和方法
JP7078380B2 (ja) * 2017-11-01 2022-05-31 Ｎｅｃプラットフォームズ株式会社 命令制御装置、命令制御方法およびプログラム
CN108710505A (zh) * 2018-05-18 2018-10-26 南京大学 一种基于fpga的可扩展稀疏矩阵向量乘处理器
US11663014B2 (en) * 2019-08-26 2023-05-30 Arm Limited Speculatively executing instructions that follow a status updating instruction
CN110971401B (zh) * 2019-11-19 2021-10-22 武汉大学 一种基于交叉互锁机制的认证密钥协商方法及其实施装置
US12190117B2 (en) 2019-11-26 2025-01-07 Advanced Micro Devices, Inc. Suppressing allocation of registers for register renaming
US11301252B2 (en) * 2020-01-15 2022-04-12 Arm Limited Executing mutually exclusive vector instructions according to a vector predicate instruction
US20240311939A1 (en) * 2022-11-23 2024-09-19 Brian Richard Fast Asset management system simulation
US12261755B1 (en) 2023-09-22 2025-03-25 Bank Of America Corporation Streaming architecture for improved fault tolerance
US12455780B2 (en) 2023-10-09 2025-10-28 Bank Of America Corporation Data reconciliation architecture for improved fault tolerance

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JPH0721154A (ja) * 1993-06-21 1995-01-24 Hitachi Ltd ベクトル処理装置
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
JP4800582B2 (ja) * 2004-02-20 2011-10-26 セイコーエプソン株式会社 演算処理装置
JP3988144B2 (ja) * 2004-02-23 2007-10-10 日本電気株式会社 ベクトル処理装置、及び、追い越し制御回路
US7644255B2 (en) * 2005-01-13 2010-01-05 Sony Computer Entertainment Inc. Method and apparatus for enable/disable control of SIMD processor slices
WO2007039837A2 (en) * 2005-09-15 2007-04-12 Dharmasena Suminda Sirinath Sa Implied instruction set computing (iisc) / dual instruction set computing (disc) / single instruction set computing (sisc) / recurring multiple instruction set computing (rmisc) based computing machine / apparatus / processor
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Also Published As

Publication number Publication date
US20140019728A1 (en) 2014-01-16
EP2872988B1 (en) 2016-12-14
WO2014009689A3 (en) 2014-03-27
IL236572A0 (en) 2015-02-26
KR102071272B1 (ko) 2020-01-30
CN104487941B (zh) 2017-09-29
JP6236443B2 (ja) 2017-11-22
CN104487941A (zh) 2015-04-01
GB2517877A (en) 2015-03-04
WO2014009689A2 (en) 2014-01-16
EP2872988A2 (en) 2015-05-20
GB2517877B (en) 2020-08-26
US9098265B2 (en) 2015-08-04
JP2015522196A (ja) 2015-08-03
IL236572A (en) 2017-12-31
KR20150037951A (ko) 2015-04-08

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