MY139709A - Hdtv trellis decoder architecture - Google Patents

Abstract

A TRELLIS DECODING SYSTEM (1) FOR USE IN PROCESSING A HIGH DEFINITION TELEVISION SIGNAL. THE TRELLIS DECODING SYSTEM PROCESSES VIDEO DATA IN THE FORM OF GROUPS OF INTERLEAVED TRELLIS ENCODED DATA PACKETS AND INCLUDES A TRACEBACK UNIT (33) THAT IDENTIFIES A SEQUENCE OF ANTECEDENT TRELLIS STATES IN ACCORDANCE WITH A STATE TRANSITION TRELLIS. THE DELAY, RE-ENCODER AND TRELLIS DEMAPPER ELEMENTS OF PREVIOUS TRELLIS DECODERS ARE ELIMINATED. A BRANCH METRIC COMPUTER (2) INCLUDES EIGHT DISCRETE SUBUNITS (3), ONE FOR EACH POSSIBLE TRELLIS STATE. EACH SUBUNITS (3) GENERATES TWO OUTPUT BITS (14,15) INDICATIVE OF THE TWO TRELLIS BRANCHES EXITING THE TRELLIS STATE REPRESENTED BY THAT PARTICULAR SUBUNITS (3). AN ADD-COMPARE-SELECT UNIT (8) INCLUDES EIGHT DISCRETE SUBUNITS (23), EACH ASSOCIATED WITH A PARTICULAR TRELLIS STATE. EACH SUBUNIT (23) INCLUDES AS AN INPUT TWO BITS (28, 29) RECEIVED FROM THE BRANCH METRIC COMPUTER (2) AND AS AN OUTPUT TWO BITS (6, 31). BIT 31 IS CHOSEN FROM 28 AND 29. BIT 6 IS CHOSEN FROM THE BRANCH METRIC INFORMATION (26, 27) INPUT TO EACH SUBUNIT (23). A TRACEBACK CONTROL AND MEMORY UNIT (33) INCLUDES AN N TO 1 MULTIPLEXER (49) WHICH RECEIVES AS AN INPUT THE OUTPUT BITS (6, 31) FROM THE ADD-COMPARE-SELECT UNIT (8). THE PRESENT SYSTEM OFFERS A HARDWARE REDUCTION FROM PRIOR ART.