MXPA98007295A - Method and apparatus for generating a cam - Google Patents

Abstract

The present invention relates to a method for generating a converter for a series of data in which the converter defines an address in an associative memory, the method comprises the steps of: a) receiving a first converter associated with a first series of data that defines an address in the associative memory for the first data series. b) receiving a second converter associated with a second series of data defining an address in the associative memory for the second data series. c) determining a first combined second converter from the second converter and the first converter where the first second converter combined in a converter for a series of first second data and defining an address in the associative memory for the first second data series, and d ) query the address in the associative memory for the series of first seconds data to determine if the series of first seconds data are stored in the associative memory

Description

METHOD AND APPARATUS TO GENERATE A CHANGE BACKGROUND OF THE INVENTION Field of the Invention The present invention relates, in general, to the field of the generation of converters (changes), such as cyclic redundancy codes, polynomial codes and key calculation codes, and more specifically, to a method and apparatus for generating a converter (change).

Description of the State of the Art In FIGURE 1 an example of a converter of converters (changes) 10 of previous inventions is shown. The converter (change) generator 10 of the previous invention has a data record (shift register) 12 and an intermediate retentive register 14. The specific generator of FIGURE 1 is designed to calculate a cyclic redundancy code (CRC-16). The various registers 16 of the intermediate retentive register 14 are strategically coupled by a variety of exclusive OR's 18. The data bits are shifted out of the data register 12 and sent to the intermediate register 14. When the data bits have been completely moved to the intermediate register 14, the intermediate register 14 contains the CRC related to the data bits. The converter generators (changes) have also been encoded in software. Emulating hardware has proven to be an inefficient method to generate converters (changes) in software, so software schemes generally use look-up tables to calculate the converter (change) of one byte or a quartet (4 bits) at a time. The table can be adjusted for any size of data bits (for example, 1 bit, 10 bits, etc.).

The packetizers use converter generators (changes) to calculate the CRCs for newly formed data packets. A packetiser receives packets (data) from different sources. Then, the received packets are grouped according to their final destination. If two small packages have the same destination, they are combined in a single package and then transmitted to their destination. In previous invention applications, the packetizer removes the CRCs from both packets and then recalculates the CRC based on the combined data of both packets. In other situations, the packetizer may receive a large packet that needs to be divided into two smaller packets. In the applications of previous inventions, the CRC of the large package is discarded and a new CRC is calculated from the working memory for the two smaller packages. This process is not efficient because the CRCs of the received packets contain useful information to calculate the CRCs of the output packets.

Generators of converters (changes) are also used in associative memories. The converter generator (changes) calculates the key calculation code or the polynomial code (see USPN 4,527,239 Brandin) to determine the address of a data packet. When the data packet consists of a combination of the two previous packets, the associative memories of the previous inventions calculate a new converter (address) for the new data packet from the working memory. You can achieve processing advantages with a converter generator (changes) that the old converters (changes) can use to calculate a new converter.

Consequently, there is a need to have a converter (change) generator that can generate a new converter from the existing converters (changes) without having to use the underlying data.

Summary of the Invention A method that overcomes these problems generates a converter (change) upon receiving a first converter associated with a first data series. A second converter associated with a second data series is also received. The second converter is added to the first converter in order to form a combined converter composed of the first and the second converter for a series of data composed of the first and the second series.

An apparatus for implementing this method that includes an input / output port coupled to a controller. The controller is also coupled to a query memory, to a shift module and to a combiner.

Brief Description of the Drawings FIGURE 1 is a schematic diagram of a converter of converters (changes) of the State of the Art; FIGURE 2 is a block diagram of a converter generator (changes) according to the invention; FIGURE 3 is a schematic representation of a displacement module employed in the converter (change) generator of FIGURE 2; FIGURE 4 is a schematic representation of a combiner employed in the converter (change) generator of FIGURE 2; FIGURE 5 is a block diagram of an alternative embodiment of the converter (change) generator according to the invention; FIGURE 6 is an operation diagram of a displacement module; FIGURE 7 is a diagram of operations of a module without displacement; FIGURE 8 is an operations diagram of a converter module (changes); FIGURE 9 is a diagram of operations of a module without converters (changes); FIGURE 10 is a block diagram of an associative memory; FIGURE 11 is a block diagram of a packetizer; FIGURE 12 is a schematic diagram of a general-purpose computer and a computer-readable storage medium containing readable computer instructions; FIGURE 13 is a look-up table for a CRC-32 polynomial code; and FIGURE 14 is a reverse look-up table for the CRC-32 polynomial code.

Detailed Description of the Drawings FIGURE 2 shows a block diagram of a converter (change) generator 20 according to the invention. Unlike the converter generators (changes) of the previous inventions, the converter (change) generator 20 can calculate a new converter based on the previous converters (changes) without having to refer to the underlying data. To understand how the converter (change) generator works, 20 we must understand some of the underlying mathematical operations. The underlying mathematics is based on polynomial codes, including, but not limited to, cyclic redundancy codes. These codes can be expressed by means of the following equation: X "- M (X) = Q (X) G (X) + R (X) Where X "" k is a displacement term M (X) is the polynomial of the message G (X) is the generator polynomial Q (X) is the quotient resulting from the message being divided by the generator polynomial; and R (X) is the remnant of the division process.

The remainder is the CRC or message converter. From the above equation it can be shown that the converter of two messages that have been combined exclusively (OR) is equivalent to the combined converters associated with the two messages. If the first message is "A" and the second message is "B", the combined message will be "AB". The polynomial of the message is: Where Z is equal to the number of bits that message B has.

RAB (X) = R (XZA (X)) + RB (X) In this way, to generate the message converter "AB", we only need to combine the "B" converter with the "AO" converter, where 0 represents Z zero. When the converters (changes) of "A" and "B" are known, all that is needed is to calculate the value of the converter moved from "A" and combine it with the "B" converter. Fortunately, there is a simple process to calculate the displaced converter.

The converter (change) generator 20 uses the mathematics described above to calculate new converters using existing converters. An input / output port 22 is used to receive the existing converters (changes) and generate the new converters. The input / output port 22 is coupled to a controller 24 that coordinates the functions of a memory 26, of a displacement module 28 and of a combiner 30. The memory contains a look-up table for the converter. An example of such a look-up table is shown in FIGURE 13. The table in FIGURE 13 is based on a CRC-32 converter that calculates the byte-by-byte converter. Other tables can be generated for other polynomials. The invention is not limited to CRC polynomials, but can accommodate a wide variety of different polynomials. The specific polynomial will depend on the application of the converter generator (changes). The displacement module 28 has the function of determining the displaced converter. For example, the combiner is used to combine (XOR) a first shifted converter and a second converter to form a first-second converter. The first-second converter is defined as the converter associated with a first-second data series (ie, in an example of communications, the second data series is transmitted immediately after the first data series: first-second data series). The process of moving the first converter and combining it with the second converter is called addition. The converter (change) generator can be implemented in software, or in hardware consisting of a memory, a microprocessor and a few displacement registers and excluding OR circuits.

FIGURE 3 shows a schematic diagram of a displacement module 28 used by the converter (change) generator 20. The converter to be moved is stored in a register of converters (changes) 40 having an input 42, a control of displacement 44 and an output 46. The output 46 is connected to an exclusive OR circuit 48. A query register 50 contains an element that is selected using an indicator derived from the converter to be shifted. The query register 50 has an input 52, a shift control 54 and an output 56. The output 56 is coupled to a second input of the exclusive OR circuit 48. The output 58 of the exclusive OR circuit is stored in an output register 60. After proper processing, the output register 60 contains the shifted converter, which is transmitted to the controller 24 through an output 62.

FIGURE 4 shows a schematic diagram of the combiner 30 used by the converter (change) generator 20. A first register 70 and a second register 72 have three outputs connected to an exclusive OR circuit 74. In one example, the first record 70 contains the first converter shifted, and the second register 72 contains the second converter. The output of the exclusive OR circuit 74 is connected to an output register 76. Once the first shifted converter is combined with the second converter, the output register 76 will contain the first-second converter.

FIGURE 5 is a block diagram of an alternative embodiment of a converter (change) generator 100 according to the invention. The converter (change) generator 100 has an input / output port 22 coupled to the controller 24. The controller 24 communicates by means of a bus (main path) 102 with a memory 26, a module 28, a non-displacement module 104, a converter module 106, a non-converter module 108 and a combiner 30. The memory 26 contains the look-up table (e.g., the table of FIGURE 13) plus a reverse look-up table, the example of which is illustrated in FIGURE. 14. The reverse lookup table in FIGURE 14 is based on the same approach, byte by byte, CRC-32. The converter (change) generator 100 of FIGURE 5 can combine converters (changes) such as the converter (change) generator 20 of FIGURE 2. In addition, the converter generator 100 can determine a first-second converter if the converter is provided. first converter and a second data series or a first data series and a second converter. The converter (change) generator 100 can eliminate the second converter from the first-second combined converter to determine the first converter. Basically, the converter (change) generator 100 allows the complete manipulation of converters when there are sufficient inputs and converters (changes) or data. It will be explained in more detail how to achieve it after explaining each of the modules in more detail with respect to FIGURES 6-9.

FIGURE 6 is an operation diagram of the displacement module. The displacement module determines the converter of a displaced message (ie, "AO" -XZA (X)). The process begins, step 120, upon receiving the converter 122 to be moved in step 124. Then, in step 128, the indicator 126 is extracted. Then, the converter 122 is moved to the right by the number of bits which is in the indicator 126, in step 130. This forms a moved indicator 132. It should be noted that the words right and left are used only for convenience and are based on the conventionalism that the most important bits are placed at the left. When a different conventionalism is used, it is necessary to change the words right and left so that they conform to conventionalism. Then, the moved converter 132 is combined (i.e., XOR is made) with an element 134 associated with the indicator 126, in step 136. With this the shifted translator 138 is formed in step 140, with which the process is completed in step 142. It must be pointed out that if the reason the first converter is moving is to generate a first-second converter, then the first converter must be moved by the number of bits that there are in a second series of data. This is done by executing X times the displacement module, where X is equal to the number of data bits of the second data series divided by the number of bits in the indicator. It should be noted that another way of implementing the displacement module is by employing a polynomial generator like that of FIGURE 1. The first converter 122 is placed in the intermediate retentive register 14. A number of logical zeros (null) is then processed. ) equal to the number of data bits in the second data series.

FIGURE 7 is an operation diagram of the undisplaced module. An example of when this module is used is when the data series converter "AB" is combined with the converter of the data series "B". This makes the data series converter "AO" or XZA (X). It is necessary "not to move" the converter to find the converter of the data series "A". The process is started, step 150, receiving the shifted converter 152, in step 154. In step 156, a reverse indicator 158 is extracted. The reverse indicator 158 is equal to the most important portion 160 of the shifted converter 152. The indicator Inverse 158 is associated with an indicator 162 in the reverse look-up table (e.g., see FIGURE 14) in step 164. Next, the element 166 associated with the indicator 162 is combined with the translator shifted in step 168. This produces an intermediate product 170, in step 172. In step 174, the intermediate product 170 is moved to the left to thereby form a moved intermediate product 176. Then, the moved intermediate product 176 is combined with the indicator 162, in the step 178, to form the converter 180, which ends the process, step 182. It should be noted that the number of bits in the series (z) of data "B" is not equal to the number of bits in the indicator when the module is executed X times displaced, where X = z / (number of bits in the indicator).

FIGURE 8 is an operation diagram of a converter module. The converter module can determine the first-second converter of a first-second data series by providing the first converter and the second data series, without first having to convert the second data series to a second converter. The process begins, step 190, extracting at least a significant portion 192 from the first converter 194 in step 194. This is combined with the second data series 196 to form an indicator 198, in step 200. Next, a first moved converter 202 is combined with an element 204 associated with the indicator in the look-up table (e.g., FIGURE 12), in step 206, creating a combined converter 208 in step 210, which completes the process, step 212. It should be noted that if the indicator has a length of one byte, then the converter module can only process one byte of data at a time. When the second data series is greater than one byte, then the converter module is executed by one byte of data at a time, until the entire second data series has been executed. In another example it is assumed that the first converter is equal to all zeros (null), then the combined converter will only be the converter of the second data series. In another embodiment, the first converter could be a precondition and the resulting converter would be a pre-converter to the second condition. Let us assume, in another example, that a fourth converter is desired for a fourth series of data. A first piece of data (eg, one byte) is extracted from the fourth data series. This indicates an element in the lookup table. When the fourth data series contains more than the first data portion, the next portion of data is extracted. The next portion of data is combined with the least important portion of the element to form an indicator. Then, the element is moved to the right by the number of bits in the next data portion to form a moved element. The moved element is combined with a second element associated with the indicator. This process is repeated until the fourth data series is fully processed.

FIGURE 9 is an operation diagram of a non-converter module. The non-converter module can determine the first converter for a first data series by providing the first-second converter and the second data series. The process begins, step 220, by extracting the most important portion 222 from the first-second converter 224 in step 226. The most important portion 222 is a reverse indicator that is associated with an indicator 228 in the inverse look-up table. In step 230 the indicator is accessed. Then, the first-second converter 224 is combined with an element 232 related to the indicator so as to form an intermediate product 234 in step 236. The intermediate product is moved to the left by the number of bits in indicator 228, in step 238. This forms a moving intermediate 240. Then, the indicator 228 is combined with the second data series 242 so as to conform the result 244 in step 246. The result 234 is combined with the intermediate product moved 240 to thus forming the first converter 248 in step 250, which completes the process in step 252. Again, this module is repeated several times if the second data series is longer than the indicator.

Some examples of what converter module 100 can do, include determining a second-third converter from a first-second converter and a first converter. The first converter is shifted by the number of data bits of the second-third data series. The first displaced converter is combined with the first-second-third converter to form the second-third converter. In another example, the converter (change) generator 100 can determine a first-second-third-fourth converter after receiving a fourth data series. In an example, the converter module would first calculate the fourth converter (using the converter module). Using the displaced module, the first-second-third converter would be displaced by the number of data bits in the fourth data series. Then, the first-second-third displaced converter is combined, using the combiner, with the fourth converter.

FIGURE 10 is a block diagram of an associative memory 300. The associative memory 300 uses a converter (change) generator 302 to associate a data series with an address and a confirmer. In general, the address is half the converter and the confirmer is equal to the other half of the converter. A catalog 304 stores the list of addresses and their associated confirmators, plus a linked list if necessary. The linked list is necessary to resolve any conflict. Conflicts occur when two different data series are converted to the same address. The linked list points to another address when a conflicting series of data is stored. The confirmer is used to verify that the correct address associated with the data series has been accessed. The catalog shows the address where the data series is stored in a memory 306. The process is controlled by a controller 308 that communicates with the outside world through an input / output port 310. If all the data series they have a fixed length, it is possible to eliminate the use of the catalog 304. By using the converter (change) generator 302, it is easy to see if the first-second data series is stored if the first converter and the second converter are known. It is also possible to carry out a quick search of a reverse order (that is, second-first series of data). For those who have knowledge of the technique, a wide variety of quick search routines will be obvious. It should be noted that the requirements of the underlying polynomial of an associative memory are not the same as those of a CRC. As a result, other polynomial generators can be used in this application.

FIGURE 11 is a block diagram of a packetizer 320. The packetizer 320 is another example of a device that uses a converter (change) generator 322 as described herein. In one example, a packetizer is part of a router. A controller 326 receives the incoming packets 324. The controller 326 forms the outgoing packets 328 from the incoming packets 324. Commonly, the outgoing packets 328 have a fixed length, and the incoming packets 324 have an undefined length or are of different length . Frequently incoming data is not formed before in packets. An output packet 334 can be formed from two small packets 330, 332, which go to the same destination. The data packets contain a portion of data ("A" or "B") and a CRC or converter [R (AB) or R (B)]. Using the converter (change) generator 322, the CRC [R (AB)] of the combined packet ("AB") 334 can be quickly determined by providing the CRCs of the individual packets 330, 332. In another example, the incoming packet 336 It is too large and should be divided into two packages 338, 340. The two new CRCs can be easily calculated by first calculating the converter (for example [r (C)]) of the shorter of the two data series and eliminating this converter from the combined converter to form the other CRC [R (D)]. Other examples can be devised where more complex manipulations of CRCs are needed. The converter (change) generator described in this report can perform these calculations without having to recalculate the CRCs from the working memory using the underlying data.

FIGURE 12 is a schematic diagram of a general-purpose computer 350 and a computer-readable storage medium 352 that contains readable computer instructions. The computer-readable storage means 352 contains instructions that when executed by the computer 350 performs the function of the converter (change) generator 100. These instructions may be independent or may be part of a set of instructions performing the functions of the associated memory 300 or performing the functions of the packer 320.

In this way, a converter (change) generator has been described which can determine a combined converter from a plurality of separate converters (changes) without having to access the underlying data. In addition, the converter (change) generator can perform many other converter manipulations (changes) that arise in packetizers and associative memories. The utility of the converter (change) generator is not limited to the two examples described in this specification (ie, associative memories and packetizers). For those who have knowledge of the technique, many other applications will be obvious.

Although the invention has been described in conjunction with the specific embodiments thereof, it is obvious that the various alterations, modifications and variants for those who have knowledge of the technique will be obvious, based on the above description. Accordingly, it is intended that the claims set forth below cover all such alterations, modifications and variants.

Claims (20)

CLAIMS Having sufficiently described my invention I consider as a novelty and therefore claim as my exclusive property, what is contained in the following clauses:

1. A method to generate a converter (change), comprising the following steps: (a) receiving a first converter associated with a first data series; (b) receiving a second converter associated with a second data series; and (c) adding the second converter to the first converter, so as to generate a first-second combined converter for a first-second data series.

2. The method of claim 1, further including the following steps: (d) removing the second converter from the first combined second converter to thereby form a first shifted converter; (e) not move the first displaced converter to form the first converter.

3. The method of claim 2, wherein the non-offset step includes the following steps: (i) extracting a reverse indicator from the first shifted translator; (ii) read an indicator in a reverse look-up table; (iii) combining an element of a look-up table associated with the indicator, with the first displaced translator, in order to form an intermediate product; (iv) move the intermediate product to the left by a number of bits in the indicator, in order to form a moving intermediate product; and (v) combining the intermediate product moved with the indicator.

4. The method of claim 3, wherein steps (i) to (v) are repeated X times, where X is equal to the number of bits in the second data series divided by a number of bits in the indicator.

5. The method of claim 1, wherein the step of the addition includes the following steps: (i) shifting the first converter to the right by the number of bits in the second data series, in order to form a first shifted translator; and (ii) combining the first displaced converter with the second converter.

6. The method of claim 1, wherein the converter is the result of a polynomial code applied to a series of data.

7. The method of claim 6, wherein the polynomial code is a cyclic redundancy code.

8. The method of claim 1, further including the following steps: (d) receiving a first-second-third converter associated with a first-second-third data series; (e) moving the first converter by a number of bits in a second-third data series, in order to form a first shifted converter; and (f) combining the first-second-third converter with the first shifted converter, in order to form a second-third converter.

9. The method of claim 8, further including the following steps: (g) receiving a fourth series of data; (h) calculate a fourth converter; (i) shifting the first-second-third converter by a number of bits in the fourth data series, in order to form a first-second-third shifted converter; and (j) combining the first-second-third converter shifted with the fourth converter, so as to form a first-second-third-fourth converter.

10. The method of claim 9, wherein the step of calculating the fourth converter includes the following steps: (i) extracting a first data portion of a fourth data series; (ii) accessing an element associated with the first data portion in a query memory table; (iii) when the fourth data series contains more than the first data portion, extract a next portion of data; (iv) combining the next portion of data with a significant portion of the element, at least, to form an indicator; (v) moving the element to the right by a number of bits of the next data portion, to form a moved element; (vi) combining the moved element with a second element associated with the indicator; and (vii) repeat steps from (iv) to (vi) until the entire fourth series of data has been processed.

11. The method of claim 8, wherein the displacement step includes the following steps: (i) extracting an indicator from the first converter; (ii) move the first converter to the right, by a number of bits of the indicator, in order to form a first converter moved; (iii) combining the first translator moved with an element of a look-up table associated with the indicator.

12. The method of claim 1, wherein steps (i) to (iii) are repeated X times, where X is equal to the number of bits in the indicator divided by the number of bits in the second- third series of data.

13. The method of claim 8, wherein the displacement step includes the following steps: (i) placing the first converter in an intermediate register of a polynomial generator; (ii) process a number of logical zeros equal to the number of bits in the second-third data series.

14. A computer-readable storage medium that contains computer-readable instructions that, when inserted into a computer, performs the following steps: (a) receiving a first converter associated with a first series of data; (b) receiving a second converter associated with a second data series; and (c) adding the second converter to the first converter to thereby generate a first-second combined converter for a first-second data series.

15. The computer readable storage medium of claim 14, further including the following steps: (d) removing the second converter from the first combined second converter, so as to form a first shifted converter; (e) not move the first displaced converter to form the first converter.

16. The computer readable storage medium of claim 14, wherein the addition step includes the following steps: (i) shifting the first converter to the right by a number of bits of the second data series, so as to form a first displaced converter; and (ii) combining the first displaced converter with the second converter.

17. A converter generator (changes) comprising: an input / output port; a controller coupled to the input / output port; a query memory coupled to the controller; a displacement module coupled to the controller; and a combiner coupled to the controller.

18. The converter generator (changes) of claim 17, further including a non-offset module coupled to the controller.

19. The converter generator (changes) of claim 17, further including a converter module coupled to the controller.

20. The converter generator (changes) of claim 17, further including a non-converter module coupled to the controller.