MXPA98003160A - Disintercal - Google Patents

Abstract

The present invention relates to a deinterleaver including a first storage unit for storing data, an order of which is rearranged from a correct order to a random order, a data retention circuit unit for temporarily holding the data out of the first storage unit, a second storage unit for storing the output data of the data retention circuit unit, and an addressing unit for generating a routing signal for reading which is output to the first storage unit, and a routing signal which is output to the second storage unit. The addressing unit includes a counting unit for counting a clock signal to generate the addressing signal for reading, and an arithmetic unit for generating the addressing signal for writing, for rearrangement in the correct order using the addressing signal for reading, output of the cont unit

Description

UNINTERCUTOR Field of the Invention The present invention relates to a deinterleaver for deinterleaving an interleaved data sequence, and in particular to a deinterleaver required for a code division multiple access terminal (CDMA) unit operating in accordance with the U.S. Standard. IS-95.

Description of Related Art In communication systems, consecutive errors may occur in the communication data depending on the environments of the data transmission routes and the like in order to invalidate the advantageous effect of the coding that corrects the errors at random. In such a situation, the following operations are commonly accomplished.

Especially, to convert the errors of the data occurring or presented successively during the transmission in the errors of the random data, the order of the data of the transmission to be transmitted is rearranged or redistributed to a random order Ref.27301 default and then the transmission data is sent from a transmitter. In a receiver, the order of the reception data is rearranged or redistributed in the correct order or in the original order. An apparatus for rearranging or redistributing the order of transmission data to the predetermined random order is called an interleaver, and an apparatus for rearranging or redistributing the order of reception data to the correct order is called a deinterleaver. A deinterleaver includes, as shown in FIG. 1, a first storage unit 110, a data retention circuit unit 120, a second storage unit 130, and an addressing unit 140 that includes a binary counting unit 141. and a third storage unit 142. The reception data is stored sequentially in the first storage unit 110 starting at address "O". The binary counting unit 141 of the addressing unit 140 counts from the initial count value "0" to the number of the reception data stored in the first storage unit 110, and produces an output signal corresponding to the value of the count. The output signal is output to the first and third storage units 140 and 142 as a routing signal for reading. Therefore, the data of The reception stored in the first storage unit 110 is read sequentially from it in response to the addressing signal for reading from the binary counting unit 141 starting at address "0". The reception data read from the first storage unit 110 is temporarily retained in the data retention circuit unit 120. In the third storage unit 142 of the addressing unit 140, the numbers representing the correct order of the data of reception are stored starting at address "0". The numbers are read sequentially from the third storage unit 142 in response to the addressing signal for reading from the binary counting unit 141 starting at the number stored at address "0". The number read from the third storage unit 142 is output to the second storage unit 130 as an address signal for writing. In the second storage unit 130, the reception data temporarily held in the data retention circuit unit 120 is stored in an address specified by the addressing signal for writing from the third storage unit 142. Accordingly , the data of reception are sequentially stored in the second storage unit 130 in the correct order starting at address "0". That is, in the deinterleaver shown in Fig. 1, the reception data is read sequentially from the first storage unit 110 in the order of reception. When the reception data read from the first storage unit 110 is written to the second storage unit 130, the write address of the second storage unit 130 is modified. Therefore, the order of the reception data is rearranged to establish an order before the interleaving operation. However, since the conventional deinterleaver requires a memory having a relatively large storage capacity as the third storage unit 142 which is used to store the numbers representing the correct order of the reception data as the information of the address for writing the second storage unit 130, the area of the physical elements and the consumption of the energy with increased disadvantageously. Accordingly, such deinterleaver can not be properly installed in a receiving apparatus such as a communication terminal equipment. mobile which is required to minimize the size and energy consumption.

Brief Description of the Invention It is therefore an object of the present invention to provide a deinterleaver whose size and power consumption can be reduced. To solve the above problem according to the present invention, a first deinterleaver is provided comprising: first storage means for storing the data there, the order of which is rearranged from a correct order to a random order; data retention circuit means for temporarily retaining therein the output data of the first storage means; second storage means for storing therein the output data of the data retention circuit means; and addressing means for generating a read address signal which is output to the first storage means, and a write address signal which is output to the second storage means, wherein the addressing means include counting means for counting a clock signal to generate the signal of address for reading; and arithmetic means for generating the address signal for writing for the rearrangement of the order of the data from the random order to the correct order using the address signal for reading that has been output from the counting means. Furthermore, according to the present invention, a second deinterleaver is provided comprising: first storage means for storing the data therein, whose order is rearranged from a correct order to a random order; data retaining circuit means for temporarily retaining therein the output data of the first storage means; second storage means for storing therein the output data of the data retention circuit means; and addressing means for generating a routing signal for reading, which is output to the first storage means, and a write addressing signal which is output to the second storage means, wherein the addressing means include counting means for counting a clock signal to generate the addressing signal for writing; and arithmetic means to generate the address signal for reading to rearrange the order of the data from the order to randomly to the correct order using the address signal for writing that was output from the counting means.

Brief Description of the Drawings The objects and features of the present invention will become apparent from the consideration of the following detailed description taken in conjunction with the appended drawings, in which: Figure 1 is a block diagram showing a configuration of a conventional deinterleaver; Figure 2 is a block diagram showing the structure of a deinterleaver according to a first embodiment of the present invention; Figure 3 is a block diagram showing the constitution of a deinterleaver according to a second embodiment of the present invention; Figure 4 is a block diagram showing an example configuration of a communication system including a receiving apparatus which has a deinterleaver of the present invention; and Figure 5 is a schematic diagram showing a portion of a data sequence after which it is interleaved from a paging channel of a downlink of the IS-95 Standard or from a forward traffic channel thereof.

Description of the Preferred Modalities Referring now to Figures 2 to 5, a description of one embodiment of the present invention will be given using as an example a deinterleaver for use with a paging channel for a downlink of a CDMA terminal facility conforming to the IS Standard. -95 US and / or a forward traffic channel thereof.

(First mode of the invention) A de-interleaver according to a first embodiment of the present invention includes, as shown in FIG. 2, a first storage unit 10, a data retaining circuit unit 20, a second storage unit 30, and a unit 40. In the structure, the addressing unit 40 includes a binary counting unit 41 of 9 bits, a binary counting unit 42 of 6 bits, an inversion unit 43 of the order of the bits, a selection unit of addends 44, and an aggregator 45. The reception data is stored sequentially in the first storage unit 10 that starts at address "0 (decimal)". The binary counting unit 41 of 9 bits of the addressing unit 40 counts from "0 (decimal)" to "383 (decimal)", so that the counting value is sequentially output to the first storage unit 10. as a routing signal for reading. Accordingly, the reception data stored in the first storage unit 10 are read sequentially from it starting at the "0 (decimal)" address in response to the addressing signal for reading from the binary counting unit 41 of 9 bits. The reception data read from the first storage unit 10 is temporarily withheld in the data retention circuit unit 20. The 6-bit binary counting unit 42 of the addressing unit 40 is activated by a clock signal CLK2 . The frequency of the clock signal CLK2 is one sixth that of a clock signal CLK1 which is used to activate the binary counting unit 41 of 9 bits. The 6-bit binary counting unit 42 counts from "o (decimal)" to "63 (decimal)", and the count value obtained is output sequentially up to the inversion unit 43 of the order of the bits. The inversion unit 43 of the order of the bits rearranges an order of the bits of the count value from the binary counting unit 42 of 6 bits to an inverted bit order. For example, when the count value from the 6-bit binary counting unit 42 is "101000", the inversion unit 43 of the order of the bits produces a data output of "000101". The adder selection unit 44 is activated with a clock signal CLK3 having a frequency equal to that of the clock signal CLK1 used to activate the binary counting unit 41 of 9 bits. The addend selection unit 44 selects sequentially six addends (ie 0, 64, 128, 192, 256 and 320) in synchronization with the clock signal CLK3. For example, the addend selection unit 44 includes a sextant or 3-bit sextant counter, so that when the counting values are "0 (decimal)", "1 (decimal)", "2 (decimal)" , "3 (decimal)", "4 (decimal)" and "5 (decimal)", the addends "0 (decimal)", "64 (decimal)", "128 (decimal)", "192 (decimal) "," 256 (decimal) "and" 320 (decimal) "are selected, respectively. The operation is executed repeatedly after this, in a similar way. With In relation to this, the selecting unit of the addends 44 can also be implemented with a counter and a selector. The aggregator 45 adds an output signal of the inversion unit 43 of the order of the bits and an output signal of the selecting unit of the addends 44, and the resulting signal is output to the second storage unit 30 as a signal Address for writing. The reception data temporarily retained in the data retention circuit unit 20 is stored in the second storage unit 30 in a direction designated by the addressing signal for writing from the aggregator 45. A description will be given below. of the deinterleaver operation according to this embodiment in an example in which the reception data interleaved as shown in Figure 5, they are introduced. In Figure 5, an address for reading indicates an address for reading the first storage unit 10, and each of the reception data denotes a portion of a data sequence after it is sandwiched over a paging channel for a downlink of the IS-95 US Standard or on a traffic channel forward of it. In this respect, for example, the reception data DO stored in the first storage unit 10 in the reading direction "0 (decimal)" designates the data whose position is the first before the interleaving operation, and the data of the reception D64 stored in the first storage unit 10 in the address for reading "1 (decimal)" designates the data whose position is 64a. before the collation operation. When an initial counting value "000000000" (decimal "0") of the 9-bit counting unit 41 is output from the 9-bit counting unit 41 to the first storage unit 10 as the addressing signal for reading, the data of the reception DO stored in the address for reading "0 (decimal)" of the first storage unit 10 are read from it to be temporarily retained in the data retention circuit unit 20 In addition, an initial count value "000000" (decimal "0") of the 6-bit counting unit 42 is output to the inversion unit 43 of the order of the bits, and then the order of the bits of the it is inverted. As a result, "000000" (decimal "0") is output from the inversion unit 43 of the order of the bits to the aggregator 45. In this situation, since the unit of selection of the addends 44 selects the summand "0 (decimal)" ("000000000"), the result of the addition "000000000" (decimal "0") is output from the aggregator 45 to the second storage unit 30 as the address signal for writing. Accordingly, the reception data DO temporarily retained in the data retention circuit unit 20 are stored in the second storage unit 30 in the "0 (decimal)" direction which corresponds to the position of the data, the DO reception data before the interleaving operation. When the count value "000000001" (decimal "1") is output from the 9-bit binary counting unit 41 to the first storage unit 10 as the address signal for reading, the reception data D64 stored in the address for reading "1 (decimal)" are read from the first storage unit 10 to be temporarily held in the retention circuit unit. data 20. On this occasion, since the binary counting unit 42 of 6 bits, continuously outputs "000000000" (decimal "0") to the inversion unit 43 of the order of the bits, "000000000" (decimal "0" ") is output from the inversion unit 43 of the order of the birios to the aggregator 45. In addition, the unit of selection of the addends 44 selects the summand" 64 (decimal ("001000000") to output the summing to the aggregator 45. Accordingly, the result of the addition "001000000" (decimal "64") is output from the aggregator 45 to the second storage unit 30 as the address signal for writing. In response thereto, the reception data D64 temporarily retained in the data retention circuit unit 20 is stored in the second storage unit 30 in the "64 (decimal)" direction which corresponds to the position of the data, of the reception data D64 before the interleaving operation. After this point, the operation is carried out repeatedly in a similar manner, so that the reception data is stored in the second storage unit 30 in the directions corresponding to the positions of the reception data before the reception. intercalation operation, as shown in Table 1. "_do not Table 1 N > O Table 1 (Cont.) ON For example, the reception data D32, D144 and D368 stored in the addresses for reading "6 (decimal)", "14 (decimal)" and "23 (decimal)" in the first storage unit 10 are stored in the second storage unit 30 and the addresses which correspond to the data positions of the reception data D32, D144 and D368 before the interleaving operation, as follows (reference will be made to rows 1, 15, and last of Table 1). When the counting value "000000110" (decimal "6") is output from the 9-bit binary counting unit 41 to the first storage unit 10 as the address signal for reading, the reception data D32 stored in the address for reading "6 (decimal)" are read from the first storage unit 10 which are to be held temporarily in the data hold circuit unit 20. Since the count value of the binary counting unit 42 of 6 bits is "000001" (decimal "1") in this case, "100000" (decimal "32") is output from the inversion unit 43 of the order of the bits up to the aggregator 45. On the other hand, the summing "0 decimal") ("000000000") is selected to be output from the addend selection unit 44 to the aggregator 45. Consequently, the result of the addition "000100000" (decimal "32") is output from the aggregator 45 to the second storage unit 30. Accordingly, the reception data D32 temporarily held in the data retention circuit unit 20 is stored in the second storage unit. storage 30 in the address "32 (decimal)" which corresponds to the position of the data, of the reception data D32 before the interleaving operation. When the value of the count "000001110" (decimal "14") is output from the binary counting unit 41 of 9 bits to the first storage unit 10 as the address signal for reading, the data of the reception D144 stored in the address for reading "14 (decimal)" are read from the first storage unit 10 that are to be temporarily held in the unit of the data hold circuit 20. On this occasion, since the counting value of the unit Binary count 42 of 6 bits is "00001" (decimal "2"), "010000" (decimal "16") is output from the inversion unit 43 of the data order to the aggregator 45. On the other hand, the summing "128 (decimal)" ("010000000") is selected to be output from the selection unit of the addends 44 to the aggregator 45. Accordingly, the result of the addition "0100010000" (decimal "144" ) is output from the aggregator 45 to the second unit of storage 30. The reception data D144 temporarily retained in the unit of the data retention circuit 20 are stored accordingly in the second storage unit 30 in the address "144 (decimal)" which corresponds to the position of the data, of the reception data D144 before the interleaving operation. For the reception data D368, when the count value "00010111" (decimal "23") are output from the 9-bit binary counting unit 41 to the first storage unit 10 as the address signal for reading, the reception data D368 stored in the address for reading "23 (decimal) "are read from the first storage unit 10 so that they are temporarily retained in the data retention circuit unit 20. Since the count value of the 6-bit binary counting unit 42 is" 000011" (decimal "3") in this situation, "110000" (decimal "48") is output from the inversion unit 43 from the order of the bits to the aggregator 45. On the other hand, the sum "320 (decimal)" ( "101000000") is selected to be output from the selection unit of the addends 44 to the aggregator 45. Accordingly, the result of the addition "101000011" (decimal "368") is output from the aggregator 45 to the second storage unit . Accordingly, the reception data D368 temporarily retained in the data retention circuit unit 20 is stored in the second storage unit 30 in the "368 (decimal)" direction which corresponds to the position of the data of the data retention circuit unit 20 before the interleaving operation. As described above, in the deinterleaver of this mode, since the addressing unit 40 can be configured with a counter and an arithmetic circuit, the memory for the address modification table for the deinterleaving operation can be distributed with, and the circuit system can be advantageously configured in a small-sized structure for minimized energy consumption.

(Second embodiment of the invention) A de-interleaver according to a second embodiment of the present invention includes a first storage unit 50, a data retention circuit unit 60, a second storage unit 70, and an addressing unit 80. In connection therewith, the addressing unit 80 includes a binary counting unit 81 of 9 bits, a inversion unit 82 of the order of the bits, a multiplier 83, a divisor 84, and an aggregator 85. The reception data is stored sequentially in the first storage unit 50 starting at the address "0 (decimal)". The binary counting unit 81 of 9 bits of the addressing unit 80 counts from "0 (decimal)" to "383 (decimal)". The inversion unit 82 of the order of the bits rearranges an order of the six-bit bits of lower order of a count value of the binary counting unit 81 of 9 bits to an inverted order. For example, the counting value of the binary counting unit 81 of 9 bits is "100101000" (decimal "296"), "000101" (decimal "5") is output from the inversion unit 82 of the order of bits. The multiplier 83 multiplies an output signal of the inversion unit 82 of the order by a multiplication factor "6 (decimal)". Additionally, the divider 84 divides the count value of the binary counting unit 81 from 9 bits between a fixed value "64 (decimal)". Incidentally, it is also possible to extract only three high order bits from the counting value of the binary counting unit 81 of 9 bits. The aggregator 85 adds the output signal of the multiplier 83 to the output signal of the divider 84, and then the result of the addition is output to the first storage unit 50 as a Address signal for reading. As a result, the reception data stored in the first storage unit 50 is read sequentially therefrom in response to the addressing signal for reading from the aggregator 85. The reception data read from the first storage unit 50 are temporarily held in the data retention circuit unit 60. The count value of the 9 bit binary counting unit 81 of the addressing unit 80 is consecutively output from it to the second storage unit. 70 as an address signal for writing. As a result, the reception data temporarily retained in the data retention circuit unit 60 is stored sequentially in the second storage unit 70 in response to the addressing signal for writing the binary counting unit 81 of 9 bits. Next, the operation of the deinterleaver according to the second embodiment will be described in relation to an example in which the interleaved reception data shown in FIG. 5 is entered. In the addressing unit 80, the initial counting value "00000000" (decimal "0") of the unit binary counting 81 of 9 bits is output from the binary counting unit 81 of 9 bits to the inversion unit 82 of the order of the bits. In the inversion unit 82 of the order of the bits, only six bits of lower order are extracted from the value of the count, and then the order of the bits thereof is inverted. As a result, "000000" (decimal "0") is output from the inversion unit 82 of the order of the bits to the multiplier 83. In the multiplier 83, "000000" (decimal "0") is multiplied by the factor of multiplication "6 (decimal)" to output the result of the multiplication "000000000" (decimal "0") to the aggregator 85. On the other hand, in the divisor 81, the initial count value "000000000" (decimal "0" ) of the binary counting unit 81 of 9 bits is divided by the fixed value "64 (decimal)" to output the result of the division "000" (decimal "0") to the aggregator 85. In the aggregator 85, the result of the multiplication "000000000" (decimal "0") is added to the result of division "000" (decimal "0"), so that the result of the addition "000000000" (decimal "0") is output to the first storage unit 50 as the address signal for reading. Accordingly, the data of the reception DO stored in the first storage unit 50 in the reading direction "0 (decimal)" are read from it (see ) that are to be temporarily retained in the data retention circuit unit 60. In this situation, since the initial count value "000000000" (decimal "0") of the binary counting unit 81 of 9 bits are input to the second storage unit 70 as the routing signal for reading, the reception data DO temporarily retained in the data retention circuit unit 70 are stored in the second storage unit 70 in the address " 0 (decimal) "which corresponds to the position of the DO data before the collation operation. Subsequently, the count value "000000001" (decimal "1") is output from the binary counting unit 81 of 9 bits to the inversion unit 82 of the order of the bits. In the inversion unit 82 of the data order, only six lower order bits are extracted from the count value, and then the order of the bits is inverted. As a result, "100000" (decimal "32") is output from the inversion unit 82 of the order of the bits to the multiplier 83. In the multiplier 83, "100000" (decimal "32") is multiplied by the multiplication factor "6 (decimal)", and then the result of the multiplication "110000000" (decimal "192") is output to the aggregator 85. On the other hand, in the splitter 81, the count value "000000001" (decimal "1") of the binary counting unit 81 of 9 bits is divided by the fixed value "64 (decimal)", and then the result of the division "000" (decimal "0") ") is fed to the aggregator 85. In the aggregator 85, the result of the multiplication" 110000000"(decimal" 192") is added to the result of the division" 000"(decimal" 0"), so that the result of the addition "110000000" (decimal "192") is output to the first storage unit 50 as the address signal for reading. In response to this, the data of the reception DI (not shown in figure 5) stored in the first storage unit 50 in the address for reading "192 (decimal)" are read from it so that they are temporarily withheld in the data retention circuit unit 60. On the other hand, since the count value "000000001" (decimal "1") of the binary counting unit 81 of 9 bits is output to the second storage unit 70 as the address signal for writing, the reception data DI temporarily held in the data retention circuit unit 70 are stored in the second storage unit 70 in the "1 (decimal)" direction which corresponds to the position of the data, of the reception data DI before the interleaving operation.

The above operation is carried out repeatedly thereafter in a similar manner, so that the reception data is stored in the second storage unit 70 in the directions corresponding to the data positions of the reception data. before the collation operation.

OR Table 2 N > o Table 2 (Cont.) KJ 00 For example, the reception data D16 and D8 stored in the read addresses "12 (decimal)" and "24 (decimal)" in the first storage unit 50 are stored in the second storage unit 30 in the directions which correspond to the positions of the data on the reception data DI6 and D8 before the interleaving operation, as follows (see rows 17 / a and ninth of Table 2). For the reception data D16, the counting value of "000010000" (decimal "16") is output from the binary counting unit 81 of 9 bits to the inversion unit 82 of the order of the bits. In the inversion unit 82 of the order of the bits, only six bits of lower order are extracted from the counting value, and then the order of the bits thereof is inverted. As a result, "000010" (decimal "2") is output from the inversion unit 82 of the order of the bits to the multiplier 83. In the multiplier 83, "000010" (decimal "2") is multiplied by the multiplication factor "6 (decimal)", and then the result of the multiplication "000001100" (decimal "12") is output to the aggregator 85. For another part, in divider 81, the count value "000010000" (decimal "16") of the binary counting unit 81 of 9 bits is divided by the fixed value "64 (decimal)", and then the result from the division "000" (decimal "0") is output to the aggregator 85. In the aggregator 85, the result of the multiplication "000001100" (decimal "12") is added to the result of the division "000" ( decimal "0"), so that the result of the addition "000001100" (decimal "12") is output to the first storage unit 50 as the address signal for reading. As a result, the reception data D16 (see FIG. 5) stored in the first storage unit 50 in the read address "12 (decimal)" are read from it so that they are temporarily retained in the unit. data retention circuit 60.

On the other hand, since the count value "000010000" (decimal "16") from the binary counting unit 81 of 9 bits is inputted to the second storage unit 70 as the address signal for writing, the reception data D16 temporarily held in the data retaining circuit unit 70 are stored in the second storage unit 70 in the address "16 (decimal)" corresponding to the position of the data, of the reception data D16 before the interleaving operation. For the data of the reception D8, the counting value "000001000" (decimal "8") is output from the binary counting unit 81 of 9 bits to the inversion unit 82 of the order of the data. In the unit inversion 82 of the order of the data, only six bits of lower order are extracted from the count value, and then the order of the bits thereof is inverted. Accordingly, "000100" (decimal "4") is output from the inversion unit 82 of the data order to the multiplier 83. In the multiplier 83, "000100" (decimal "4") is multiplied by the factor of multiplication "6 (decimal)", and then the result of the multiplication "000011000" (decimal "24") is output to the aggregator 85. On the other hand, in the divisor 81, the count value "000001000" ( decimal "8") of the binary counting unit 81 of 9 bits is divided by the fixed value "64 (decimal)", and then the result of the division "000" (decimal "0") is output to the aggregator 85 In the aggregator 85, the result of the multiplication "000011000" (decimal "24") is added to the result of the division "000" (decimal "0"), so that the result of the addition "000011000" (decimal "24") is output to the first storage unit 50 as the address signal for reading. In response to this, the reception data D8 (see FIG. 5) stored in the first storage unit 50 at the "24 (decimal)" read address are read therefrom so that they are temporarily retained in the data retention circuit unit 60. On the other hand, since the counting value "000001000" (decimal "8") of the binary counting unit 81 of 9 bits is input to the second storage unit 70 as the address signal for writing, the data of the reception D8 temporarily held in the unit data retention circuit 70 are stored in the second storage unit 70 in the "8 (decimal)" direction which corresponds to the position of the data, of the data of the reception D8 before the interleaving operation. To explain the functions of the divider 84, the description of the operation of the deinterleaver will now be given with respect to the reception data D320 and D352 (not shown in Table 2) stored in the first storage unit 50 in the directions for reading "5 (decimal)" and "11 (decimal)". The count value "101100000" (decimal "352") is supplied from the binary counting unit 81 of 9 bits to the inversion unit 82 of the order of the bits. In the inversion unit 82 of the order of the bits, only six bits of lower order are extracted from the counting value, and then the order of the bits thereof is inverted. As a result, "000001" (decimal "1") is output from the inversion unit 82 of the order of the bits to the multiplier 83. In the multiplier 83, "000001" (decimal "1") is multiplied by the multiplication factor "6 (decimal)" to output the result of the multiplication "000000110" (decimal "6") to the aggregator 85. On the other hand, in the divisor 81, the count value "101100000" (decimal "352") of the binary counting unit 81 of 9 bits is divided by the fixed value "64", and then the result of the division "101" (decimal "5") is it outputs to the aggregator 85. In the aggregator 85, the result of the multiplication "000000110" (decimal "6") is added to the result of the division "101" (decimal "5"), so that the result of the addition "000001011" (decimal "11") is output to the first storage unit 50 as the address signal for reading. Accordingly, the reception data D352 stored in the first storage unit 50 at the read address "11 (decimal)" are read from it (see Figure 5) so that they are temporarily retained in the storage unit. data retention circuit 60. In this situation, since the count value "101100000" (decimal "352") of the binary counting unit 81 of 9 bits is input to the second storage unit 70 as the signal of address for writing, the reception data D352 temporarily retained in the retention circuit unit for the data 70 are stored in the second storage unit 70 in the address "352 (decimal)" which corresponds to the position of the data, of the reception data D352 before the interleaving operation. As above, in the deinterleaver according to the second embodiment of the present invention, since the addressing unit 80 can be configured with a counter and an arithmetic circuit, the memory for the address modification table for the deintercation operation It can be distributed with it. This makes it possible to build the deinterleaver in a small-sized structure for minimized energy consumption.

(Modality of a receiving apparatus of the invention] As can be seen from Figure 4, a receiving apparatus 400 having a deinterleaver according to the present invention is provided which includes a demodulator unit 410, a deinterleaver unit 420 configured substantially in the same manner as for the deinterleaver shown in FIG. 2 or 3, and a decoding unit 430 for error correction. The receiver 400 is connected by means of a transmission path 300 to a transmission unit 200 which includes a coding unit 210 for error correction, for driving or carrying out an error correction coding for the transmission data, an interleaving unit 220 to achieve an interleaving operation for the output signal of the error correction coding unit 210, and a unit of modulation 230 for modulating the output signal of the interleaver unit 220 to transmit the modulated output signal. In the receiving unit 400, the transmission signal transmitted by the transmission path 300 from the transmitter 200 is demodulated by the demodulator unit 410 to produce the reception data. The reception data is de-interleaved as described above by the de-interleaving unit 420. As a result, the reception data is rearranged to the correct order, and then output from the de-interleaving unit 420 to the decoding unit 430 of correction of the errors, so that they are codified in the same one. In response to this, the decoded data is output from the receiving apparatus 400. In the de-interleaving unit 420 of the receiver 400, since the addressing unit can be configured with a counter and an arithmetic circuit (FIGS. 2 and 3) , it is possible to build the deinterleaving unit 420 of a small size to achieve a minimized energy consumption.

(Other modalities) The deinterleaver shown in Figure 2 can possibly be used as an interleaver in a transmission apparatus as follows. Especially, the read addressing signal sent from the addressing unit 40 to the first storage unit 10 is also used as the write addressing signal for the first storage unit 10 and the addressing signal for reading for the second unit. storage 30 is also adopted as the write addressing signal for the second storage unit 30, so that the transmission data is output from the second storage unit 30 to the first storage unit 10 by means of the data retention circuit unit 20 to be written to the first storage unit 10. Similarly, the deinterleaver of Figure 3 can also be used as a deinterleaver in a transmission apparatus. Although the present invention has been described with reference to the illustrative modalities particular, will not be restricted by these modalities but only by the appended claims. It will be appreciated that those skilled in the art can change or modify the modalities without departing from the scope and spirit of the present invention.

It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates.

Having described the invention as above, property is claimed as contained in the following

Claims (8)

1. A deinterleaver, characterized in that it comprises: a first storage means for storing the data, an order of which is rearranged from a correct order to a random order; a data retaining circuit means for temporarily retaining the output data of the first storage means; a second storage means for storing the output data of the data retention circuit means; and a routing means for generating a routing signal for reading, which is output to the first storage means, and a write addressing signal which is output to the second storage means, wherein the Addressing includes: a counting means for counting a clock signal to generate the addressing signal for reading; and an arithmetic means for generating in response to the address signal for writing a rearrangement of the order of the data from the random order to the correct order using the addressing signal for reading output from the counting medium.

2. A de-interleaver according to claim 1, characterized in that: the counting means includes a binary bit counting means (m is an integer) for counting the clock signal to generate the addressing signal for reading; and the arithmetic means includes: a n bit binary counting means (n is an integer less than m) to count another clock signal, which has a frequency lower than that of the clock signal, to output a value of counting; a means of reversing the order of the data, for reversing an order of the bits of the count value output from the binary bit counting means; a means of selecting addends to sequentially select a plurality of addends in synchronization with the clock signal; and an aggregator means for adding an output signal of the inversion medium of the order of the bits to an output signal of the selection means of the addends.

3. A de-interleaver according to claim 2, characterized in that: the binary binary counting means includes a binary 9-bit counter; the half-bit binary counter includes a 6-bit binary counter; the other clock signal has a frequency which is one sixth of that of the clock signal; and the summation selection means sequentially selects the addends of 0, 64, 128, 192, 256 and 320 in synchronization with the clock.

4. A receiving apparatus, characterized in that it comprises a de-interleaver according to claims 1, 2 or 3 for receiving the data, which are transmitted from a transmission apparatus and an order of which is rearranged from a correct order to an order to randomly, to rearrange the random order to the correct order.

5. A deinterleaver, characterized in that it comprises: a first storage means for storing the data, an order of which is rearranged from a correct order to a random order; a data retaining circuit means for temporarily retaining the output data of the first storage means; a second storage means for storing the output data of the data retention circuit means; and a routing means for generating a read address signal which is output to the first storage means, and a write address signal which is output to the second storage means, wherein the addressing means includes: a counting means for counting a clock signal to generate the addressing signal for writing; and an arithmetic means for generating the address signal for reading, for rearranging the order of the data from the random order to the correct order using the address signal for writing.

6. A deinterleaver according to claim 5, characterized in that: the counting means includes a binary bit counting means (m is an integer) for counting the clock signal to generate the addressing signal for reading, and the arithmetic means includes: a means of inverting the order of the bits to reverse an order of the bits, of the lower order n bits (n is an integer less than m) of the count value output from the binary bit count medium; a multiplication means for multiplying an output signal of the inversion means of the order of the bits by a predetermined multiplication factor; a dividing means for dividing the count value output from the binary bit counting means by a predetermined fixed value; and an aggregator means for adding an output signal of the multiplier means to an output signal of the divider means.

7. A de-interleaver according to claim 6, characterized in that: the binary bit counting means includes a binary 9-bit counter; the bit order reversal means inverts an order of the six bit bits of lower order of the count value output from the binary bit count means; the multiplying means multiplies an output signal of the inversion medium of the order of the bits by six; and the dividing means divides the count value from the binary counting medium of 9 bits by 64.

8. A receiving apparatus, characterized in that it comprises a de-interleaver according to claims 5, 6 or 7 for receiving the data, which are transmitted from a transmission apparatus and an order of which is rearranged from a correct order to a random order , to rearrange the random order to the correct order.