MXPA97007576A - Circuit line interface for an band - Google Patents

Abstract

Line interface circuit for broadband, consisting of a transmission module and receiving module, the transmission module being formed by a converter block of parallel to serial format (11), which receives data from a multiplexer block (14). ), a scrambling block (15) and a transmission clock generation block (12), the parity generating blocks (13), the scrambling block (15) and the multiplier block (14) being interconnected, while the receiver module is constituted from a serial to parallel converter block (33), which receives data from a container clock generation block (34) and sends data to a demultiplexer block (36) and to a parity check block (32), as well as to a descrambler block (37) that is connected to the demultiplexer block (3)

Description

CIRCUIT LINE INTERFACE FOR BROADBAND D E S C R I P C I O N OBJECT OF THE INVENTION The present specification refers to a patent application of invention relating to a broadband line interface circuit, whose obvious purpose is to be used in broadband integrated services digital network equipment (B-ISDN) or for e-teams of the synchronous digital hierarchy (JDS), performing the conversion of serial-parallel format and vice versa, for regimes of up to 622 Mbs and the termination function of regeneration section and synchronous multiplexing of up to four tributaries, including the detection of the frame alignment, the generation and verification of the regeneration section parity and the line randomization and descrambling.

FIELD OF THE INVENTION This invention has its application in the field of telecommunications and more specifically in the transport and switching systems of the synchronous digital hierarchy (JDS) and the broadband integrated services digital network (B-ISDN) BACKGROUND OF THE INVENTION It is known the existence in the market of commercial products that perform the function of conversion from serial to parallel format and vice versa, as well as the possibility, by means of discrete components, of performing the functions of termination of section of regeneration and synchronous ultiplexing for interfaces of regimes high-speed binaries.

The realization, thus, of the previous functions requires a complex, voluminous circuitry with high power consumption.

The integrated circuit line interface, object of this invention, comes to solve these problems by presenting a new architecture, performing these functions with a reduced complexity in its circuitry, pejueño volume and reduced power consumption, which has a very positive effect on the cost of the transport and switching equipment of the broadband integrated services digital network (B-ISDN), and the synchronous digital hierarchy (SDH).

DESCRIPTION OF THE INVENTION The broadband line interface circuit that the invention proposes, is in itself an obvious novelty within its field of application, since according to its characteristics, it is possible to have a new solution for the line interface circuits of broadband, which are used in the equipment of the terminal section (center where the signal is multiplexed / demulti-plex and the signal is regenerated) of the broadband integrated services network (B-ISDN), or of the synchronous digital hierarchy ( JDS).

More specifically, the broadband line interface circuit object of the invention converts from parallel to serial format and vice versa, multiplexing and demultiplexing several flows of synchronous frames in a single serial flow, suitable for transport in fiber optic links .

The invention consists of two modules, one of transmission and the other of reception, the transmission module carrying out the synchronous mul iplexing, the generation of the regeneration section parity, the line and terminal randomization and the conversion from parallel to serial format.

The transmission module basically consists of the following blocks. Namely: - Parity generator block.

- Randomizer block.

- Generation block of the transmission clock.

- Multiplexer block.

- Converter block and serial parallel format.

The parity generator block calculates the regeneration section parity over all octets of each synchronous frame transmitted after synchronous multiplexing and line randomization.

The calculated value of the parity in each frame is inserted in the field corresponding to the parity of the regeneration section of the next frame, prior to the randomization of the line.

The position that this field must occupy will be determined by a signal, "which is a primary input of the device.

The scrambling block performs the terminal and line randomization and the terminal scrambling is performed independently on each of the tributaries that are multiplexed synchronously, while the line randomization is performed on the global octet flow, after which the tributaries have been multiplexed.

The object of the terminal randomization is to facilitate the interconnection of the invention with other devices of lower speed that can use signals with PECL (Positive Emiter Coupled Logic) levels, which in turn have continuous levels displaced with respect to the ECL (Emiter Coupled Logic) levels that are used in this invention for the entry of data from tributaries.

The sequence generated by both scrambling steps is reset in each synchronous frame with the transmission frame start signal.

A signal will indicate to the scrambler the octets belonging to the first row of the regeneration section overhead of each synchronous frame, which must not undergo any randomization process.

The terminal and line randomization can be disabled by a signal that is a primary input of the device.

The generation block of the transmission clock generates and distributes the clocks derived from the transmission line frequency, which is a primary input of the device that uses the ECL logic levels (Emiter Coupled Logic) for the rest of the blocks of the transmission module. ) differential.

The derived clocks are the transmission octet clock, which is used internally in the circuit and the tributary clock which is a primary output of the device.

The multiplexer block is responsible for transforming the set of octet flows, from the selected tributaries, into a single multiplexed flow for transmission.

The number of tributaries is selected by a combination of signals which are primary inputs of the device.

The octet flows of the selected tributaries are entered into the device through the corresponding primary inputs.

The synchronous multiplexing is carried out by successively intercalating an octet of the higher-order tributary with one byte of the next-order tributary and so on.

The purpose of the serial format converter block is to transform the multiplexed octet stream into a serial bitstream.

The parallel format converter block generates the primary outputs of the transmission data transmission output and output clock circuit, suitably aligned for use by the external circuitry and both signals use the ECL (Emiter Coupled Logic) differential levels, so The corresponding negated signals are also present.

The serial parallel format converter block also performs the remote loop function, which is governed by a control signal which is a primary input of the device.

When the remote loop is activated, the data and the high-speed reception clock are connected directly to the data and transmission clock threads.

The establishment of ties is especially useful for network tests on the corresponding interfaces.

The reception module performs synchronous demultiplexing, verifies regeneration section parity, performs terminal and line descrambling, and converts serial to parallel format.

The reception module is basically composed of the following blocks. Namely: - Parity verification block.

- Descrambler block.

- Generation block of the reception clock.

- Demultiplexer block.

- Serial to parallel conversion block.

The parity check block calculates the parity of the regeneration section over the received synchronous frames and compares it with the parity field of the regeneration section received.

The result of the comparison made replaces the regeneration section parity field itself and if both parities are equal, the result of the comparison will be 00 'H.

The position of the regeneration section parity field is identified by a signal that is a primary input of the device.

The descrambler block is responsible for carrying out descrambling both terminal and line.

Terminal desalination is done independently on each of the tributaries that are demultiplexed synchronously, while line desalination is performed on the global flow of octets before they are demultiplexed and the purpose of terminal descrambling is to facilitate the interconnection of the invention with other devices of lower speed.

The sequence that generates both descrambling steps is reset in each synchronous frame with the receive frame start signal, which is a primary input of the device.

This same reception frame start signal identifies the octets that belong to the first row of the synchronous traffic regeneration section overhead, which must not undergo any descrambling process and both descrambling steps can be disabled by a signal that is a primary input of the device.

The reception clock generation block generates and distributes the clocks derived from the receiving line frequency, which is a primary input of the device that uses the ECL (Emiter Coupled Logic) differential logic levels, for the rest of reception blocks. reason why it also appears as input the corresponding, negated signal and the derived clocks are the one of reception octet and the receiver tributary clock, the latter being a primary output of the device.

The demultiplexer block is responsible for transforming the flow of octets received in a number of flows directed to the corresponding tributaries and the number of tributaries is selected by means of signals that are primary inputs of the device.

The octet flows of the selected tributaries leave the device through the corresponding primary outputs and the synchronous demultiplexing is done by successively extracting from the flow of octets received an octet directed to the higher order tributary, followed by another octet of the next order and thus successively .

The serial-to-parallel conversion block transforms the serial stream of bits, received at the primary input of high-speed data, into an octet stream.

The signal of the primary high-speed data input uses the ECL (Emiter Coupled Logic) differential logic levels, which is why the negated signal also appears as the primary input.

To transform the serial stream of bits into a flow of octets, there is a machine with two states, which are the status of hooked and status of NOT HITCHED, which are governed by several signals of primary inputs.

In the NO HITCH state, the serial to parallel format conversion block searches for the appearance of the synchronous frame ament sequence.

Once said synchronous frame ament sequence has been found, the format converter block as the octets it generates so that the ament sequence is transformed into a pair of octets, and the machine enters the ENGAGED state.

From that moment, the machine maintains the. octet phase captured with the ament sequence and remains in this state while not being indicated, through a control signal, that it must perform a new ament process.

If this were to happen, the machine would go to the NO HITCH state and the process would be restarted again.

The ament process can be disabled by a control signal that is a primary input of the device.

When this occurs, the format converter block generates the octets from the serial stream of bits, completely independent of the detection of the ament sequence of the synchro-na frame.

The conversion block of serial format to parallel, performs the function of lasal loop, and the primary output of high speed is derived from the data wire of high transmission speed, according to the value of a control signal that is an input primary of the device. The establishment of ties is useful to perform network tests on the corresponding interfaces.

DESCRIPTION OF THE DRAWINGS To complement the description that. is being carried out and in order to help a better understanding of the characteristics of the invention, this descriptive report is accompanied, as an integral part thereof, two sheets of drawings in which illustrative and non-limiting, has been represented the next: Figure number 1 shows a block diagram of the transmission module of the broadband line interface circuit object of the invention.

Figure number 2.- Corresponds to the block diagram of the reception module incorporating the invention.

PREFERRED EMBODIMENT OF THE INVENTION In view of these figures, it can be seen how the broadband line interface circuit proposed is divided into two modules, one for transmission and one for reception, represented respectively in figures 1 and 2.

The transmission module represented in a diagram in figure number 1 performs synchronous multiplexing, generation of regeneration section parity, line and terminal randomization and conversion from parallel to serial format, in accordance with recommendations G .707, G.708 and G.709 of the ITU-T.

The reception module represented in a block diagram in figure 2, performs synchronous demultiplexing, verifies regeneration section parity (Bl), performs descrambling of terminal and line, and converts serial to parallel format, in accordance with the recommendations cited above G.707, G.708 and G.709 of the ITU-T.

Following the figure number 1 it is observed that the transmission module of the broadband line interface circuit object of this invention, is constituted basically by the following blocks. Namely: Parity generator block (13).

Randomizer block (15).

Generation block of the transmission clock (12) Multiplexer block (14) - Series parallel format converter block (eleven) .

The parity generator block (13) calculates the regeneration section parity Bl on all octets of each synchronous frame transmitted after synchronous multiplexing and line randomization.

The calculated value of the parity in each frame is inserted in the field corresponding to the parity of the regeneration section of the next frame, prior to the line randomization.

The position that said field must occupy is indicated by an active pulse at high level of the signal (16), which is a primary input of the device.

The scrambling block (15) performs the randomization of both terminal and line and both steps generate respective pseudo-random sequences according to the primitive polynomial g (x) = x7 + x6 + l.

Terminal scrambling * is performed independently on each of the tributaries that are multiplexed synchronously, while line randomization is performed on the global flow of octets, after the tributaries have been multiplexed.

The purpose of terminal randomization is to facilitate the interconnection of the invention with other devices of lower speed that can use signals with PECL (Positive Emiter Coupled Logic) levels with levels of continuous displaced with respect to ECL (Emiter Coupled Logic) levels. they use the entries (18), (19), (20) and (21).

Terminal scrambling allows the adaptation of the DC levels by means of a simple step capacitor, thanks to the fact that the randomized terminal data stream does not contain information at low frequencies.

The sequence generated by both scrambling steps is reset in each synchronous frame with the transmission frame start signal (17), which is a primary input of the device.

The signal itself (17) configured as the transmission frame start signal identifies, by means of an active pulse at high level, the octets belonging to the first row of the overhead of the regeneration section of each synchronous frame which, according to with Recommendation G.708 of the ITU-T, they should not undergo any randomization process and both the line and terminal scrambling process can be disabled by the signal (23), which is a primary input of the device .

The generation block of the transmission clock (12) generates and distributes the clocks derived from the transmission line frequency (8), which is a primary input of the device that uses the logic levels, for the rest of the blocks of the transmission module. ECL (Emiter Coupled Logic) differential, which is why the negated signal (9) also appears as input.

The derived clocks are the transmission byte clock (48), which is used internally in the circuit and the transmitting tributary clock (22), which is a primary output of the device.

The multiplexer block (14) is responsible for transforming the set of octet flows from the selected tributaries into a single multiplexed flow for transmission.

The number of tributaries is selected by a combination of two signals (10) which are primary inputs of the device and the combination of signals indicates the following. Namely: - Combination 00 «that there is a single tributary.

- Combination 01 there are two tributaries.

- Combination 10 that there are three tributaries.

- Combination 11 there are four tributaries.

The octet flows of the selected tributaries are introduced into the device through the primary inputs (21), (20), (19) and (18), with the primary input (21) being the highest order.

Synchronous multiplexing is done by intercalating an octet of the highest order tributary with one octet of the next order tributary and so on.

The purpose of the serial parallel format converter block (11) is to transform the multiplexed octet stream into a serial bit stream.

The series parallel format converter block (11) generates the primary outputs of the output transmission clock circuit (3) and the data transmission circuit (1), suitably aligned for use by the - external circuitry and both signals use the ECL (Emiter Coupled Logic) differential levels, so that their corresponding negated signals (4) and (2) are also present respectively.

The serial parallel format converter block (11) also performs the remote loop function, which is governed by the control signal (5) which is a primary input of the device.

When the remote loop is activated, the data (6) and high-speed clock (7) wires are connected directly to the transmission data wires (1) and transmission clock (3).

The establishment of ties is especially useful for network tests on the corresponding interfaces.

In view of Figure 2, it can be observed «that the reception module consists basically of the following blocks. Namely: - Parity check block (32).

- Descrambler block (37).

- Generation block of the reception clock (34).

- Demultiplexer block (36).

Conversion block from serial to parallel format (33).

The parity check block (32) calculates the regeneration section parity (Bl) on the received synchronous frames and compares it with the received regeneration section parity field.

The result of the comparison replaces the regeneration section parity field itself and if both parities are equal, the result of the comparison will be 00'H.

The position of the regeneration section parity field is identified by a high-level active pulse of the signal (39), which is a primary input of the device.

The descrambler block (37) is in charge of desalting both the terminal and the line and desalination of terminals is performed independently on each one of the affluents that are demultiplexed synchronously, while the desalination of lines is done on the global flow of octets before these are demultiplexed.

Both descrambling steps generate respective pseudorandom sequences according to the primitive polynomial cited in the description of the invention corresponding to g (x) = x7 + x6 + l.

The object of terminal descrambling is to facilitate the interconnection of the invention with other devices of lower speed, as well as the scrambling block (15) of the transmission module.

The sequence generated by both desa-randomization steps is reinitiated in each synchronous frame with the reception frame start signal (38), which is a primary input of the device.

This same signal identifies the octets that belong to the first row of the regeneration section overhead of each synchronous frame, which, according to ITU recommendation G.708, must not undergo any descrambling process, and both desaleate steps -risation can be disabled by means of a signal (46), «which is a primary input of the device.

The reception clock generation block (34) generates and distributes. for the rest of reception blocks the clocks derived from the reception line frequency (7), which is a primary input of the device that uses the ECL (Emiter Coupled Logic) differential levels, which is why the input also appears as the corresponding denied signal (29).

The derived clocks are the reception byte clock (47) and the reception tributary clock (45), this latter receiving tributary clock (45) being a primary output of the device.

The demultiplexer block (36) is responsible for transforming the flow of received bytes in a number of flows directed to the corresponding tributaries.

The number of tributaries that is selected by the combination of two signals (35) which are primary inputs of the device, the combination of signals indicating the following. Namely: - Combination 00 there is a single tributary.

- Combination 01 -there are two tributaries.

- Combination 10 that there are three tributaries.

- Combination 11 there are four tributaries.

Then, a maximum of four tributaries can be selected and the octet flows of the selected tributaries leave the device through the corresponding primary outputs (43), (42), (41) and (40), synchronous demultiplexing taking place successively from the octet stream received, one octet directed to the higher order tributary (43), followed by another directed to the next order (42), and so on.

The serial to parallel format conversion block (33) transforms the bitstream stream, received with the primary input of high speed data (6), into an octet stream.

The signal of the high-speed data input (6) uses the ECL (Emiter Coupled Logic) differential levels, which is why the negated signal (27) also appears as the primary input.

To transform the serial stream of bits into a flow of octets, there is a machine with two states, which are HITCHED and NON-HITCHED, which are governed by two signals (30) and (31) which are primary inputs of the circuit.

In the NO HITCH state, the serial to parallel format conversion block (33) searches for the appearance of the synchronous frame alignment sequence.

Said synchronous frame is? IIIOIIOOOIOIOOO'B.

Once this sequence is found, the format converter block aligns the octets it generates so that the previous bit sequence is transformed into the pair of octets F6'H and 28'H, passing the machine to the status of HITCHED.

From said instant the machine maintains the octet phase captured with the first alignment sequence, and remains in this state as long as it is not indicated, through an active pulse at low level in the control signal (30), that You must perform a new alignment process.

Subsequent alignment sequences detected in the reception flow produce a high-level active pulse at the primary output (44), such that said pulse coincides with the interval of the clock signal (45), immediately after the value byte. 28'H, which presents the second octet of the alignment sequence.

After the pulse in the signal (30), the machine goes to the state of NOT ENGAGED and the process is restarted., Again.

The alignment process can be disabled by the control signal (31), which is a primary input of the device and when this occurs, control signal (31) at low level, the format converter block (33) generates the octets from of the bitstream stream completely independently of the detection of the synchronous frame alignment sequences.

Additionally, the conversion block of serial to parallel format (33) performs the function of the lasal loop, and the primary high-speed output (26) is derived, through the multiplexer (25), of the high-speed data wire of transmission (1) or of the reception line (28), according to the value of the control signal (24), which is a primary input of the device, being useful the establishment of ties to perform network tests on the corresponding ones interfaces It is not considered necessary to extend this description so that any expert in the field understands the scope of the invention and the advantages "that derive from it.

The materials, shape, size and arrangement of the elements will be subject to variation, provided that this does not entail an alteration to the essence of the invention. , j The terms in which this report has been described should always be taken in a broad and non-limiting manner.

Claims (8)

R E I V I N D I C A C I O N S

1. - Line interface circuit for the ansha band, of the integrated type and those constituted by a transmission module and a reception module, which is sarasterized because the transmission module is made up of a series-parallel serial converter block (11), which stores data of a multiplexer block (14), a scrambling block (15) and a transmission clock generation block (12), the parity generation blocks (13), the scrambling block (15) and the multiplexer block being interconnected ( 14), and of a receiver module formed from a serial to parallel converter block (33) that receives data from a reception clock generation block (34) and sends data to a demultiplexer block (36) and to a parity check block (32), and a descrambler block (37), which is connected to the demultiplexer block (36).

2. - Line interface circuit for broadband, according to the first claim, characterized by the parity generator block (13), calculates the parity of regeneration section on the frames of transmitted fabric after the synchronization multiplexing and the line randomization.

3. - Cirsuito line interface for band ansha, according to the first claim, sarasterized because the scrambling block (15) performs the randomization of independent terminal on sada tributary that is multiplexed, while the line randomization is performed on the global flow of ostetos, after the tributaries have been multiplexed, both randomization steps can be disabled by means of a signal (23) which is a primary input of the device.

4. - Cirsuite line interface for broadband, according to the first claim, characterized in that the transmission clock generation block (12) generates and distributes to the rest of the blocks of the transmission module, as derivative clocks, the transmission octet clock (48) (internal signal) and the transmitting tributary clock (22) (primary output of the device).

5. - Line interface circuit for broadband, according to the first claim, characterized by the converter block from parallel to serial format (11), also performs the function of remote loop, directly connecting the data wires (6) and the high clock. reception speed (7), with transmission data wires (1) and transmission clock (3).

6. - Line interface circuit for broadband, according to the first claim, sarasterized by the blocker that descrambler (37), effects the desleatorization of independent terminals on each of the tributaries that are demultiplexed synchronously, while the desalination of line is performed on the global flow of octets before these are demultiplexed, both descrambling steps can be disabled by means of a signal (46) which is a primary input of the device.

7. - Line interface circuit for band ansha, according to the first claim, characterized in that the generation block of the reception clock (34) generates and distributes to the rest of blocks of the reception module, as derived clocks, the reception byte clock (47) (internal signal) and the afferent resection clock (45) (primary device output).

8. - Cirsuito line interface for band ansha, according to the first claim, characterized in that the block of serial to parallel format (33), uses a two-state machine for operation operation, governed by several primary input signals, searching in one of the states the appearance of the synchronous frame alignment sequence, and in the other the maintenance of the captured octet phase, remaining in this state until the corresponding control signal indicates a new alignment search, this can be disabled process through a primary signal of the device. SUMMARY Line interface circuit for broadband, consisting of a transmission module and a reception module, the transmission module being formed by a peace-allele to serial converter (11) format block, which receives data from a multiplexer block (14), a scrambling block (15) and a trans-ion clock generation block (12), the parity generation blocks (13), the scrambling block (15) and the multiplexer block (14) being interconnected. , while the receiver module is constituted from a serial to parallel converter block (33), which receives data from a reception clock generation block (34) and sends data to a demultiplexer block (36) and to a parity check block (32), as well as a "torch" block (37) that connects to the demultiplexer block (36).