KR100270311B1 - Scrambling circuit for pattern induced jitter suppression in sdh repeater chain - Google Patents

Abstract

PURPOSE: A scrambling circuit for reducing pattern-induced jitter in SDH(synchronous digital hierarchy) is provided to increase reliability of long haul transmission by preventing repetition of identical patterns. CONSTITUTION: An initiation timing generator(210) generates an initiation timing signal responding to a frame synchronization signal(FS). An inital value generator(240) generates random initial values for each regeneration repeater to prevent accumulation of pattern-induced jitters. A PRBS(pseudo random binary signal) generator(220) a PRBS corresponding to each random initial value. An initial value inserter(250) inserts the random initial values on a synchronous transfer mode frame by receiving the random initial values.

Description

SCRAMBLING CIRCUIT FOR PATTERN INDUCED JITTER SUPPRESSION IN SDH REPEATER CHAIN}

TECHNICAL FIELD The present invention relates to the field of data communications, and more particularly to a synchronous digital hierarchy (SDH) transmission system, and more particularly to a scrambling technique in a synchronous optical transmission device according to ITU-T Recommendation G.707.

In general, a regeneration repeater is used to compensate for a loss of a signal generated in a long distance transmission of a signal in a synchronous digital transmitter. The clock extractor inside the regenerative repeater extracts and provides a clock from an input signal, and a pattern induced jitter is generated in the extracted clock.

In a network in which regenerative repeaters are continuously connected, the signal input to the clock extractor of each regenerative repeater repeats the same pattern, thereby increasing the accumulation of pattern induction jitter. This pattern-induced jitter is entirely dependent on the pattern of the signal, and the cumulative increase by the number of each successive passing through the repeater repeats a serious performance degradation in the transmission network.

1 is a block diagram illustrating a scrambling method used in a conventional synchronous optical transmission device. As illustrated in FIG. 1, the initialization timing generator 110 may refer to an input frame syncronization signal (FS). An initialization timing signal is generated and output to the pseudo random binary sequence (PRBS) generator 120.

Here, the PRBS generator 120 uses a generating polynomial of 1 + x ⁶ + x ⁷ and the last byte of the first row of the Synchronous Transport Module (STM) -N section overhead (SOH: Section Overhead). byte) In the next byte, after the initialization timing signal input from the initialization timing generator 110 is initialized to "1111111", the output of the PRBS generator 120 and the STM-N signal at the x ⁷ position are modular 2 summer 130. ) And the scrambled STM-N signal is output. At this time, the first row of the STM-N section overhead is not scrambled. Therefore, since the PRBS generator 120 is initialized to "1111111" every frame in the same manner in all repeaters, the scrambled signals of all repeaters are output as STM-N signals of the same pattern.

Therefore, as mentioned above, there is a problem in that the influence of the pattern induction jitter is increased. For reference, the output period of the seven-stage PRBS generator 120 is 127 bits.

The present invention devised to solve the problems described above, pattern induction jitter by preventing the repeating of the same pattern in each repeater by different scrambling initialization for each repeater in a network connected to the repeater repeater It is an object of the present invention to provide a scrambling circuit for suppressing the occurrence of a.

That is, the present invention increases the accumulation of the pattern induction jitter by repeating the same pattern of the input signal of the clock extractor in all the repeaters in a network in which the repeaters are connected continuously. In each repeater, the scrambling is initialized differently. By preventing the same pattern from being repeated, it is intended to reduce the pattern induced jitter and to minimize the accumulation of the jitter to enable reliable long haul transmission.

1 is a diagram of a scrambling circuit in a synchronous digital transmission system according to the prior art.

2 is a scrambling circuit diagram in a synchronous digital transmission system according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210: initialization timing generator 220: PRBS generator

230: modular 2 summer 240: initial value generator

250: initial value inserter

According to an aspect of the present invention, there is provided a scrambling circuit of a synchronous digital transmission system having a connected repeater network, comprising: initialization timing generating means for generating an initialization timing signal in response to a frame synchronization signal (FS); Initial value generating means for generating an arbitrary initial value for each of the reproduction repeaters in response to the frame synchronizing signal (FS) in order to prevent the same pattern from being repeated in each reproduction repeater to prevent accumulation of pattern induction jitter; Pseudorandom binary signal generating means for generating a pseudorandom binary signal (FRBS) according to the initialization timing signal and the arbitrary initial value different for each of the reproduction repeaters; And an initial value inserting means for receiving the arbitrary initial value and inserting the random initial value on a predetermined synchronous transmission mode frame to enable correct descrambling at the receiving end of another reproduction repeater. It is done.

In addition, the present invention further comprises a modular 2 summer for outputting a scrambled synchronous transmission mode signal by summing a predetermined position value of the pseudo random binary signal (FRBS) and the output signal of the initial value inserting means that are different for each of the regenerative repeaters. Characterized in that the made up.

The accumulation of pattern induction jitter is increased by repeating the same pattern of input signals of clock extractors in all repeaters in a network in which repeaters are continuously connected among SDH transmission devices. This is a decisive factor in limiting the maximum number of repeaters. Accordingly, the present invention provides a method of fundamentally preventing the accumulation of pattern induction jitter by preventing the repeating of the same pattern in every repeater by changing the initialization of scrambling in the SDH repeater.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In general, since the output order of the PRBS generator is determined by the initial value and the generation polynomial, by changing the initial value, an output having a time delay with respect to the output order of the original PRBS generator can be obtained.

FIG. 2 illustrates a scrambling circuit in a synchronous regenerative repeater network according to an embodiment of the present invention. As illustrated, an initialization timing generator 210, a PRBS generator 220, a modular 2 summer 230, and an initial stage are shown. The value generator 240 and the initial value inserter 250 are configured.

As shown in FIG. 2, the scrambling circuit in the synchronous relay network according to an embodiment of the present invention includes an initialization timing generator 210 for generating an initialization timing signal in response to the frame synchronization signal FS, and regeneration. In order to prevent the repeating of the same pattern by repeating the same pattern in the repeater, an initial value generator 240 for generating an arbitrary initial value for each repeater in response to the frame synchronizing signal FS, an initialization timing signal and In accordance with the random initial value different for each repeater, the FRBS generator 220 for generating a pseudorandom binary signal (FRBS) and the predetermined initial value are inputted with a predetermined initial value so that the receiver can correctly descramble. An initial value inserter 250 for inserting any initial value on the transmission mode frame. In addition, a modular 2 summer 230 for adding a predetermined position value of the different pseudorandom binary signal FRBS and the output signal of the initial value inserter 250 to output the scrambled synchronous transmission mode signal for each repeater is further included. Include.

Here, the configuration of the initialization timing generator 210, the PRBS generator 220 and the modular two summer 230 is the same as in the prior art.

The initial value generator 240 generates a different initial value for each repeater, and its output is applied to the PRBS generator 220 to initialize the PRBS generator 220 and to the initial value inserter 250 to be applied to the STM-N. By loading the initial value information on the frame, the correct descrambling is possible at the receiving end.

The initial value generator 240 initializes the PRBS generator 220 to an arbitrary value without initializing the PRBS generator 220 to "1111111" every frame so that the output value of the PRBS generator 220 is differently output for each repeater. In this case, the receiver may also be able to descramble the correctly received data only when the receiver knows the initial value information. Therefore, the initial value information should be loaded on the STM-N frame.

The frame structure used for SDH (Synchronous Digital Hierarchy) synchronous multiplexing is clearly defined in International Standard ITU-T G.707.

For reference, look at the SDH frame structure defined in ITU-T G.707, where N is STM-N (N = 1, 4, 16, 64), which is 1, 4, and 16 times 155.520 Mb / s, respectively. It refers to SDH signals corresponding to 155Mb / s, 622Mb / s, 2.5Gb / s, and 10Gb / s transmission speeds, which are twice the speed of 64 times. In the frame, a payload corresponding to a pure information signal and a section overhead necessary for transmission are separately configured.

Looking specifically at the section overhead of the STM-N, A1 and A2 bytes are each 3 bytes in the case of STM-1, and 3 * N are present in the STM-N signal frame. Its purpose is to inform frame synchronization, that is, the starting point of a frame. In the actual algorithm, it is realized by finding the boundary of A1 and A2, where A1 bytes are contiguous and changed to A2 bytes.

As described above, there are 3 * N A1 and A2 bytes in the STM-N signal frame, so that the larger the N, the more A1 and A2 bytes exist than to satisfy the required frame synchronization performance. Therefore, A1 and A2 bytes of the part where A1 and A2 are replaced are mainly used, and both ends, that is, A1 bytes at the front and A2 bytes at the back, are unnecessary.

In addition, after the J0 byte and the Z0 byte of the SDH section overhead, there are X marked bytes, which are defined as "reserved bytes for domestic use" and are not defined for SDH multi-device interoperability. It can be used arbitrarily by the operator. By the way, the Z0 byte is not defined in the STM-1 signal.

The purpose of the J0 byte is to check the connection status of the repeater section in the SDH transmission network, but a detailed description of the use thereof will be omitted.

Scrambling is performed on the part except the overhead of the first row of the frame. Therefore, the unused portion of the overhead of the first row may be utilized to transmit the initial value information of scrambling to the relay period, and as described above, some of the A1 and A2 bytes and the X display portion of the first row overhead are used. Becomes

Therefore, the first row of the overhead in the STM-N frame is not scrambled, and the overhead of the first row contains the frame sync bytes A1 and A2 used for synchronization and the J0 byte defined for relay section tracking, J0 After the byte, there are a number of reserved bytes whose definitions are reserved for domestic use.

In the STM-N signal, there are 3 * N A1 and A2 bytes, and only some bytes of the boundary between A1 and A2 bytes are used for frame synchronization.

Since the initial value information should not be scrambling, it is inserted and transmitted after the unused J0 byte without being scrambled on the STM-N signal frame, or it is inserted into the unused A1 or A2 byte among the frame sync bytes. . Therefore, the receiving end can correctly descramble using the initial value information of the corresponding position. The initial value can be any value except "0000000".

The scrambling circuit of the present invention as shown in the above embodiment initializes the PRBS generator 220 to an arbitrary value without initializing the PRBS generator 220 to "1111111" every frame so that the output value of the PRBS generator 220 is different for each repeater. Minimize pattern induction jitter.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, the present invention provides a pattern induction jitter by preventing the repetition of the same pattern in each repeater by changing the initialization of the scrambling for each repeater in a network in which the repeaters are continuously connected among the SDH digital transmitters. By reducing and minimizing the accumulation of this jitter, a long-range transmission of reliable signals is possible.

Claims (6)

A scrambling circuit of a synchronous digital transmission system having a serially connected regenerative repeater network, Initialization timing generating means for generating an initialization timing signal in response to the frame synchronizing signal FS; Initial value generating means for generating an arbitrary initial value for each of the reproduction repeaters in response to the frame synchronizing signal (FS) in order to prevent the same pattern from being repeated in each reproduction repeater to prevent accumulation of pattern induction jitter; Pseudorandom binary signal generating means for generating a pseudorandom binary signal (FRBS) according to the initialization timing signal and the arbitrary initial value different for each of the reproduction repeaters; And Initial value insertion means for receiving the arbitrary initial value and inserting the arbitrary initial value on a predetermined synchronous transmission mode frame to enable correct descrambling at another receiving repeater's receiving side. Scrambling circuit for suppressing the pattern induction jitter in a synchronous digital repeater network comprising a. The method of claim 1, A modular 2 summer for outputting a scrambled synchronous transmission mode signal by summing a predetermined position value of the pseudorandom binary signal FRBS different from each other and the output signal of the initial value inserting means for each of the regenerative repeaters. Scrambling circuit for suppressing the pattern induction jitter in a synchronous digital repeater network further comprising. The method according to claim 1 or 2, The arbitrary initial value is A synchronous digital repeater network, characterized in that it is inserted into a next byte (preferably a JO byte) defined for an unused relay section tracking of the first relay section overhead of the synchronous transmission mode frame and transmitted to the receiving side. Circuit for suppressing pattern-induced jitter in the circuit. The method according to claim 1 or 2, The arbitrary initial value is In a synchronous digital repeater network, characterized in that the first and second frame sync bytes (preferably A1 byte and A2 byte) of the synchronous transmission mode frame are inserted into a byte not used for frame synchronization and transmitted to the receiver. Scrambling circuit for suppressing pattern induced jitter. The method according to claim 1 or 2, The initial value inserting means, Inserting different initial value information for each reproduction repeater on the synchronous transmission mode frame to enable correct descrambling on the receiving side, but since the initial value information at one reproduction repeater transmitting side should not be scrambling, the synchronous transmission mode frame Insert into the position after the byte (preferably JO byte) defined for the relay section which is not used without scrambling on the frame, or use it for frame synchronization among the first and second frame sync bytes (A1 and A2 bytes). A scrambling circuit for suppressing pattern induction jitter in a synchronous digital repeater network, characterized in that it is inserted into a non-byte. The method of claim 5, The transmitting side, A scrambling circuit for suppressing pattern induction jitter in a synchronous digital regenerative repeater network, wherein the same pattern is prevented from occurring by varying an initial value of scrambling in a successive repeater in a synchronous digital transmitter.

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