MXPA97006400A - Entry and exit configure - Google Patents

Abstract

A configurable input and output array (100) for a controller that has a number of internal and external input and output terminals, each of which is selected in the field as well as an input or output terminal. The logic functions (106) of the controller are configured for a specific number of outputs that use up to (32) internal logic states and the states of (32) external physical input and output points. The time update for each logic circuit is selected to be synchronized in different ways, synchronized with an internal event within the controller, synchronized with an event external to the controller, and asynchronous. The input and output arrangement includes a combination of synchronous clamped input condition arrangements (102) useful for the configuration means (112) for the logical combination of the output signals of the read circuits, and the mechanisms for driving the signals. external devices as a function of the logical combinations of the output signals of the reading circuits

Description

CONFIGURABLE INPUT AND OUTPUT TECHNICAL FIELD The present invention relates generally to configurable useful logic configurations, and more particularly, to controllers useful as decoders and bar code verifiers. BACKGROUND OF THE INVENTION A controller is an electronic device that provides control functions for an external device in response to the input signals. The controller provides one or more command signals or output controls to the external device in response to one or more input signals. The controllers are used, for example, in industrial packaging applications in the pharmaceutical, cosmetic, beverage and other industries. Programmed logic controllers (PLCs) use programmed logic devices to implement a controller function. The logic functions of the PLCs are executed in a fixed scan average, which is asynchronous to any input signal. The logic functions implemented in the internal PLC program cause a waiting time equal to the scan period. This decreases the response time and the results in PLC output endings that are not synchronized with external events. The PLC operates asynchronously so that the output signals are not synchronized with external or internal events.

Alternatively, control functions are implemented with logical hardware. The logic hardware is programmed, for example, by means of a physical wire device, blow-melt, or programmable non-volatile memory devices. The logical hardware was not reconfigured to the programs quickly or easily. Accordingly, there is a need for a controller that is easily reprogrammed and that also provides synchronized output signals. SUMMARY OF THE INVENTION It is then an object of the present invention to provide a controller having a configurable input and output arrangement and providing flexibility for the use of a number of external physical input / output points, or terminals. Each individual input and output point, or output terminal of the controller, may be actuated either as an input terminal or as an output terminal. In one embodiment of the invention, the logic functions of the controller are configured for each output terminal using up to 32 internal logical conditions and the conditions of 32 external physical input and output points. The time accuracy for each logic circuit in a controller with a configurable input and output arrangement according to the invention is selected to synchronize in different ways. One of these ways is to synchronize with the internal event which provides an input condition array inside the controller. Another way to synchronize it with an event that is external to the controller. Alternatively, an asynchronous time authorization may be provided, if desired. The invention includes a combination of reading circuits, configurable means useful for logically combining the output signals of the reading circuit, the signal conditioning mechanisms for combining the outputs of the read signals and the intermediate signals resulting from other means of communication. signal conditioning, the updating of the activation mechanisms to provide an updated activation signal to the configurable mechanisms and the signal conditioning mechanisms, and the mechanisms to activate the external devices as a function of logical combinations of the output signals of the reading circuits. A presence detector, which detects, for example, the presence of a bar code can be used to operate the system. A controller having a configurable input and output system according to the invention includes the mechanisms for initializing the system, the mechanisms for detecting an input event; the mechanisms for placing an input event in a row of circular events; and the mechanisms to execute a predetermined merge in response to an incoming event. Functional dispatch mechanisms include the mechanisms for mapping the events using a table with a combinatorial logic calculation routine and includes the mechanisms to initiate the execution of a logical combination routine. The inputs to the condition array are provided at the end of the gate period provided by an action event. The mechanisms for executing a predetermined function in response to events include: mechanisms for providing variable states representing input values; the mechanisms to operate in variable states to produce output conditions, the default function is a software simulator of a programmable array. The programmable array is an AND / OR gate array through which the output can be specified as logical functions of the inputs. The variable state of outputs consists of external signals, under internally generated conditions, counting conditions, conditions of change record and shipping conditions. In a specific embodiment of the invention, the external signals include a signal that is generated in an "object" presence sensor, which detects, for example, the presence of a bar code. The presence sensor provides an "event gate" time during which one of the main functions of the controller can be started. The signal generated from the presence sensor includes, for example, a signal generated when an object is in front of the infrared light. According to another aspect of the invention, the configurable input and output system includes an input condition array; drive function; logical functions and an output signal conditioner. The drive function is the mechanism for synchronizing the logic functions with other external events or internal events within the control system. In contrast, the PLC does not provide synchronization are external or internal events. According to another aspect of the invention, a configurable input and output system includes an input condition rule to receive a plurality of input signals and has a plurality of elements corresponding respectively to one of the input signals. The detention arrangement has events to receive and store the conditions of the elements of the entry conditions. Mechanisms are provided to select a clock signal provided in the succession array. A logical sequence AND includes an inverter array Y that has elements to receive and selectively invert the elements of the succession mechanisms; an array of multiple entries; and an input selection array Y to direct a corresponding bit from the succession array in one of the multi-input Y arrays; and an output inverter Y. A logic sequence 0 includes an inverter array 0 having elements to receive and selectively invert the elements of the succession mechanisms; an array 0 of multiple entries; an input selection array 0 to direct a corresponding bit from the succession array in one of the arrays 0 to multiple inputs; and an output inverter O. A gate O combines the output of the output inverter Y and the output inverter O. According to another aspect of the invention, the logic sequence AND configurable for a configurable input and output system includes a first Exclusive OR arrangement to logically combine each of the respective elements of the condition array with the respective element of the inverter array Y. A first array Y is provided to logically combine each of the elements of the first exclusive OR array with each of the elements of the enabling arrangement Y. A first array OR logically combines in the respective elements of the array Y into a single element. A first inverter of the exclusive inverted OR arrangement combines a single element of the OR array with an inverter command signal to provide an inverted or non-inverted Y output signal. The logical or configurable sequence for a configurable input and output system includes a second unique 0 array that logically combines the respective elements of the condition array - and the inversion array 0. A second array Y logically combines the respective elements of the second array 0 excessive with the respective elements of the enabling array 0. U second array 0 logically combines with the respective elements of the second array Y into a single element. A second exclusive inverter array 0 combines the simple elements of array 0 with an inversion command signal to provide an inverted or non-inverted output signal 0. The 0 array of the output logically combines the inverted and non-inverted Y output signal with an inverted or non-inverted output signal 0. The configurable input and output system also includes an output signal conditioner that alternately provides the direct channels of the output terminals, the change logger, a pulse circuit, a succession circuit, and an internal controller. In a specific organization form of the configurable input and output system, the logical sequence Y and the logical sequence 0 are the same. The differences between the sequences Y and the sequence 0 are only in the direction of the control INV / INV with the gate X 0 inverted and in the direction of the control bits in the inverted arrays 0 is Y. The method for providing a configurable input and output system comprises the steps of: initializing the system; detect an entry condition; place the entry condition in a circular row of conditions; remove the input transmission from the row of circular conditions using the functional dispatch mechanisms; and execute a predetermined function in response to the input condition. The method includes the step of mapping the event by a table or table for a combinatorial logic calculation routine and includes the step of initial execution of a logical combination routine. The step of executing a predetermined function in response to an event includes the steps of providing variable conditions representing input values and operating in the conditions variables to produce output conditions. The step of executing a default response function or an input condition includes the step of simulating a software simulator of a programmable array. The step of using a software simulator of a programmable array includes using a programmable array in which an array of AND / OR gates by which the outputs can be specified as logic functions of the inputs. The variable input conditions consist of internally generated signals, count states, change register states, and clamping states. BRIEF DESCRIPTION OF THE DRAWINGS The appended drawings that are incorporated in and as part of these specifications, illustrate the embodiments of the invention and together with the description, serve to explain the principles of the invention: The figure in a block diagram of a generalized configurable input and output system that includes a generalized configurable input and output condition arrangement that includes an input condition array, a logic function, an actuator function, and an output signal conditioner. Figure 2A is a functional block diagram illustrating the initialization of a configurable input and output system according to the invention. Fig. 2B is a functional block diagram illustrating a technique for providing a drive function for a configurable input and output system according to the invention. Figure 3A is a flow chart illustrating the detection of an actuator event and adding the actuator event to a row of circular events. Figure 3B is a flow chart illustrating the taking of an actuator event from the circular event row and the executed logical functions. Figure 4 is a block diagram of an input state array and a logical function. Figure 5 is a diagram illustrating the combinatorial functions Y / O of a configurable input and output system according to the invention. Figure 6 is a block diagram of an output conditioning circuit for a configurable input and output according to the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that no attempt is made to limit the invention to these embodiments, on the contrary, it is intended that the investment cover alternatives, modifications and equivalents, which may be included within. of the scope and spirit of the invention as defined by the appended claims. Figure 1 shows a block diagram indicating the main elements of the configurable input and output system 100, according to the invention. The configurable input and output system 100 includes an input state array 102 for receiving n input state variables.

A multiplexer with actuator function 104 provides release and clock signals to the output hold arrangement, which is part of an input condition array 102. The multiplexer with drive function 104 provides a number of preselected signals to drive the holding arrangement of the input condition array 102. The multiplexer with drive function 104 receives the input signals from a number of sources including radiable m of input condition, presence signals indicating the presence of an object, and other signals such as periodic clock pulses and disabling signals. In this way the variables of the input state are retained and provided at the precise moment to the configurable logic function 106 for the execution of the logic function 106 in synchronization with the selected input of the multiplexer with drive function 104. The output of the function logic is then provided to a signal conditioner 112. The initialization of the logic function, the signal conditioner 112 and the actuator multiplexer 104 provides via the initialization function block 110. The initialization function 110 allows users to select, for example, which of the n variables of the input state will be operative with the logical function 106.

The initialization function 110 also allows the user to select the configuration of the logic function 106, for example, as a simulated combinatorial AND / OR logic function. The initialization function allows the inversion and the enabling of the pre-selected input status variables as well as the different final and intermediate state variables for the logical function. The initialization function 110 further allows the user to select the signal conditioning functions for the output of the logic function 106. In addition the signal conditioning may alternatively include, for example, the output signals connected to the counter, to the output terminal , the change recorders, the pulse circuit, the holding circuit, or any other internal counter. Figure 2A shows the initialization module 200 which starts the system. The initialization module 200 includes a static memory. The initialization module 200 provides the output for the static logical arrays and provides the control signals or the states for the logical elements. The initialization module 200 is activated by the initialization module to load the appropriate array and start the operation of the system. The initialization module is a block of programs that stable the conditions between the different modules of the system. The connections are maintained in a functional block list directed to call the actuator events. Figure 2B is a functional block diagram illustrating the steps of the program that provides an activation for the initial execution of a function for a configurable input and output system according to the invention. An event detector module 202 detects an interrupted event that is accused by a change in the input signal. This event detector module 202 detects these events that are used as actuators and also detects interruptions in the timer. After detecting an event, this event is placed in a row of circular event 204. Event row 204 isolates interrupts in the event detection of the slowest event processing operations. This provides a system with a high average in the degree of increase of events. The functional distributor module 206 initiates the execution of a functional logical block by having a module 208 that takes an event from the event row 204 at an appropriate time, determined by the duration of the delay provided by the 204 event row. executed function 210 simulates a configurable logic function for the configurable input and output system. The system is optimized to operate in real time and to satisfy two important constraints of real time: namely to maximize the average acquisition of changes in inputs and maximize the average processing of the elements of the configurable system, which includes the conditioners of signal and the logical combinations, for example, recorders of change retainers and accountants. The function distribution modules 206 remove the events from the event row 204 and execute an appropriate functional block in the module 210. For example, it may be desirable for a certain output variable to change to drive a combinatorial logic calculation of configurable input and output that it is required to produce a certain bit of output control. When the input variable changes, an event identifier is placed in the row of events 204. The function distribution module 206 removes the identified event, mapped the event by a box to perform the combinatorial logic calculation routine, and then start execution of a combinatorial logic routine in the execution module 210. The function distributor 206 continues taking events from the event row 204 and executes the functional blocks until the event row 204 is emptied. After being called by the functional distributor, the function is triggered by an event of input and output is executed. The execution functions provided by the execution module 210 take all the variables of input states, operating them later and producing output states. An example of a particular execution function is a logical function and / or which is shown here below in relation to figure 5. Figure 3A is a flow chart illustrating the steps for detecting an actuator event and for adding the actuator event to a row of circular events 204. An element 302 detects an appropriate trigger source and an element 304 adds an event to the row of events 204. Figure 3B is a flow chart illustrating the steps for taking a trigger event from the row of circular events and the execution functions. The element 310 drives the event loaded in the row 204. The element 312 determines whether the additional functions are appended to the actuator event in row 204 and if they are executed as indicated by element 314. Elements 312 and 314 continue their function until all the functions attached to the received actuator event are completed. Fig. 4 is a functional block diagram illustrating an input state array as an actuator function, and a logic function for a configurable input and output system module 400, according to the invention. A complete configurable input and output system contains, for example, 32 of these modules. The input and output system module 400 combines the input state module 210, the drive module 104, and the logic function module 106 of FIG. 1. Among the invention is that in terms of the different arrangements and the logic elements , one of the preferred forms of the invention is simply by using various software arrangements, logical functions, and interconnected patterns as provided in a conventionally programmed personal computer, a workstation, or similar systems. Each module of the input and output system includes 64-bit 404 input state arrays that have 64 input signals (0-634). The 64-bit input state array 404 receives signals from various sources such as bar code decoders. The 64 outputs of the 64-bit input state array are connected to an input terminal of a 64-bit input retention array 406. The input retention array 406 receives the clock signals on a signal line 408 of a output terminal of a multiplexer 410. The 64-bit input array receives no interrupts or other transitions as such. The 64-bit input array also always contains the latest and most up-to-date status of all entries. The MUX 410 detects transitions and en-route to the appropriate retention arrangements. The transition of the state array is subsequently processed by a logical combination. The input retention output 406 is provided in 2 combinatorial logical patterns for subsequent stops: one path provides some Y functions and the other path provides a 0. For the Y path, the output of the retention array 406 is provided as the inputs to the 64-bit inverter array Y 414. The inverted Y configuration control states are resident by the 64-bit inverter array Y on a 64-bit bus 415. The outputs in the inverted array Y 414 are connected to the respective outputs of the enabling arrangement Y 418. The configuration control signals Y in are received by the inverter array Y of 64 bits 418 on the 64-bit bus 419. The outputs of the enabling arrangement Y 418 are connected to the respective inputs of the gate array Y of 64 inputs 422. The output of the gate arrangement Y of 64 inputs is connected to the input terminal of an exclusive gateway 424 that functions as the master gateway for the Y functions. INV / INV signal is provided on a line 425 to the other input terminal of exclusive gateway 424. The exclusive gateway 0 output terminal 424 is connected to an input terminal of a gateway O 428. The terminal of gate output OR provides a CMBx signal, 430 where x corresponds to one of the 32 output terminals for the 32-bit system. For the path O, the output terminals of the input holding array 406 are also connected to the respective inputs of the 64-bit reverse arrangement of 434.

The configuration control signals of the inverted signals OR are received by the inverter array or 64 bits on a 64-bit bus 435. The output terminals of the inverted array 0 are connected to the respective inputs of the enabler array 0 438. The Signal control signals of signals EN 0 are received by inverter array 0 of 64 bits on a 64-bit bus 439. The output of enabled array 0 438 is connected to the respective inputs of gate 64 of 64 inputs 442. The output of the 64-gate OR gate arrangement 442 is connected to an exclusive OR gate input terminal 444 that functions as a master inverter gate. An INV / * INV signal is provided with a signal line 445 for the other input terminal of the exclusive OR gate 444. The exclusive OR gate output terminal 444 is connected by a signal line to the other input terminal of the exclusive gateway 444. gateway O 428 where gateway O 428 combines the outputs of channels Y and O to provide the CMBx 430 signals where x corresponds to one of the 32 output terminals of system 32. The 64-bit input status array 404 of the input and output system module 400 has terminals from 0 to 31 which are always only input terminals. The arrangement of the input state 404 includes a number of input and output terminals (humidity from 32 to 63). All these input and output terminals are input terminals unless otherwise programmed. Until the configuration codes are loaded into the input and output system module 400, no output signal is provided at the output terminal for the control of any external action. Without the configuration codes, the operations of the internal controller such as the decoding of the bar code and the coincidence of the bar code are carried out but no output signal is provided at the output terminal. The results of the matching operations are only placed in the internal 64-bit input state array 404. The 64-bit 404 input conditions array contains all the input states that subsequently become available for both the logic circuits combinatory O and Y. For all modules of the input and output system. Therefore, the input and output system modules 32 provide 32 outputs. Of the 64 input bits provided for the input terminals (0-63) for the 64-bit input state array, the 32 bits provided in terminal 0-31 are bits that indicate the internal logic state of, for example , a barcode reader system such as that provided in connection with the PMC80 series of print drivers provided by DataLogic, Inc. of Scotts Valley, California. The other 32 input bits provided in terminal 32-63 are associated with the external input and output points or terminals. The 32 internal logical states provided with the terminal 0-31 include all the internal states of, for example, the bar code reader system. The internal states provided by the bar code reader system are the results of the operations carried out by the bar code readers. These basic results include: a status of the matching and barcode reading functions for each barcode scanner, a consecutive error status for each scanner, a reject-verified status, failure for up to 8 entry points and exit, and a scanner-head-disabled status. The 32 external input and output terminals 32.63 of the state array provide the inputs to the subsequent combinatorial logic circuits as well as the forward and backward connections of other outputs. The forward feeding characteristics provide the ability to carry out more complex logical functions by cascading logic functions. Each logical internal status terminal 0-31 and each external input / output terminal 32-63 is assigned a position bit in the 64-bit input status array 104 that contains a total of 64 bits, or possible tickets. These 64 possible inputs are arranged in a combinatorial logic AND or OR subsequent. In order to appropriately control the output time generated by the combinatorial logic an input retainer is provided with a clock-free signal provided on the signal line 408 of the multiplexer 410. This arrangement allows a programmer to synchronize the output of the system module Input and output configurable with the inspection of events. Whenever the clock signal selected on the signal line goes from false to true, the last value of the array of the input state is present at the input terminals of the combinatorial logic circuits Y and O. The clock signal for the array Inbound retention 406 is enabled through multiplexer 410, which is provided for the selection of any of the 4 bar code presence signals in either the "true to false" or "false to true" transition modes. . The external input and output points from 28 to 31 are also available as clocks in the output hold in the transition from "true to false" and from "false to true". The four bar code presence signals and the 4 external input and output points are available as clock sources. A periodic internal clock signal is available which provides the update of outputs similar to the PLC analysis cycle. This retention clock is used as long as it is desired to have constant and continuous updating of the selected output according to the last state of the bits in the input state array. This is the type of update that typically occurs with logical relay solutions functions of programmable logic controllers. The input retainer passes the last state of the input state array to the combinatorial logic of the selected clock transition. The output of the retainer is released as or placed "in fake", on the set edge of the selected clock. This guarantees that there will be a transition from the subsequent combinatorial logics from one inspection to the next. Note that the release functions do not occur when the periodic clock source is being used. Each enabled output must have an updated enabled control for it. This updated control selects that of a number of events that causes an update of the output. These events will come from the source of the periodic clock or the external inputs. The clock inputs or the presence tickets. The time meters will be 2 milliseconds and 10 milliseconds. This will be selected by a numeric value in an array that defines the update of the event for each output. This will be: 0 - disabled 1 - Presence # 1 false to true 2 - Presence # 2 false to true 3 - Presence # 3 false to true 4 - Presence # 4 false to true 5 - Presence # 1 true to false 6 - Presence # 2 true to false 7 - Presence # 3 true to false 8 - Presence # 4 true to false 9 - Input 29 false to true A - Input 29 false to true B - Input 30 false to true C - Input 31 false to true D - Input 28 false to true E - Input 29 false to true F - Input 30 false to true 10 - Input 31 true to false 11 - 2 milliseconds the source of the periodic clock 12 - 10 milliseconds of the source of the periodic clock Each output terminal of the Intake retention arrangement 406 is connected to the corresponding inputs of the inverter array Y 414 and the inverter array O 434. These arrays each contain 64 bits, each of which corresponds to a position in the input state array . Any particular bit position that is set for 1 corresponding inverter array causes the logical value of the array of the state that is reversed before going to the associated combinatorial logic gate. The output terminals of the inverter array Y 414 are connected to the corresponding inputs of the enabled array Y 418. The output terminals of the inverted array 0 434 are connected to the corresponding input terminals of the enabled array 0 438. Each array enabled contains 64 bits, each of which corresponds to the bit in arrangement of the input state. Setting a particular bit in one of the enabled arrays directs the corresponding bit position from the corresponding input state array in the corresponding combinatorial logic gate. The enabling of an input is analogous to the closing of a switch in the circuit that connects a bit of the arrangement of the input state with the input terminal of the corresponding combinatorial logic gate. Each of the outputs of the enabled array Y 418 is powered to the corresponding one in the input terminal 64 of the gate array Y of 64 inputs 422. Each of the outputs of the enabled array OR 438 were fed corresponding to the 64 array inputs of the gate OR the 64 entries 444. All gate inputs Y that are not enabled are forced to true (raised). All gateway array inputs that are not enabled are forced to false (lowered). The output of gate array Y 422 has a selectable output reversal function provided by an exclusive gateway 424. The output of gate array 444 has a selectable output reversal function provided by an exclusive gate 444. Exclusive 0 gates 424, 444 are used to implement the NO and YNOO functions. The logical states Y and 0 are combined using the final O gate 428. At this point the combinatorial logic stage is completed. The CMBx 430 signal (where x = 0 to 31) appears in the output terminal of the input and output system module. Each GMBx signal 430 can also be piped to the shift register of the pulse circuit, to the direction channel of the physical output or to the latch circuit, as described in relation to FIG. 6 below. The CMBx output can also be directed to drive an internal counter. The output signal at terminal 430 can be fed to counter 450 which then drives a screen. If no input is enabled for the AND array then the master inverter Y (424) is set or placed for the inverter. If no entry has been enabled for the OR array, then the master inverter (444) is disabled. The failure definitions for the external input and output points require that all points including the SHF CLK and the RJ VERs can also be used as general purpose inputs if they have not been used for their failure purpose. Your status or characteristic is available in entry status arrangement whether or not they are programmed to make an entry or exit. For the implementation of the software of the invention, each of the above events has an event handling routine which is then called when the event occurs. This event handler will look in its own list, which is done at the time of initialization and that contains the vectors for each output to be updated. The list is done at the time of initialization or when carried out to the configuration in order to save time during execution. Additionally, with the exception of clocks of 2 milliseconds and 10 milliseconds, the external clock signals for the retention of the input release the retention at the edge of the phase or at the unspecified edge. Figure 5 illustrates the combinatorial functions Y and O simulated for a configurable input and output system according to the invention. The logic and / or 500 is provided, for example, as a software simulation of a programmable multilevel array of the AND / OR gates so that the outputs are specified as a logical function of the inputs. The variables in the input state that are triggered by the functional logic block include the externally generated signals, the signals generated by the program, the states of the counter, the states of the record of changes and retention states. For each of the states of the output there can be a separate logic equation based on the variables of the input state. Figure 5 shows 64 elements of the arrangement of the input state that are combined with the respective 64 elements of the inverter of the inverted array Y in an exclusive OR array 502. The 64 elements of the exclusive array 502 is combined with the respective 64 elements of the array enabled and AP in an array Y 504. The 64 individual elements of the array Y 504 are combined together with the function O 506 to provide a single output element that is combined with another exclusive function 508 with the control signal INV / * INV. The value "0" for the control signal INV / * INV inverts the function Y to a non-Y function. The output of the exclusive OR function 508 is an input to an output gate O that provides an output signal GMBx. In a similar way, Figure 5 also shows the 64 elements of the input state array that is combined with the 64 respective elements in the inverter of the inverted OR array, in an exclusive 0 array 522. The 64 elements of the exclusive array 512 are combined with the respective 64 elements of array 0 enabled in an array Y 514. The 64 individual elements of the array Y 514 are combined together with a function 0 516 to provide a simple output element, which is combined with another exclusive function 0 518 with the control signal INV / * INV. A value "1" for the control signal INV / * INV reverses the function 0 to a function no 0. In the output of the exclusive 0 function 518 is the other input to the output 0 gate 510 that provides the output signal GMBx. Note that the inverted Y array inverts if a 0 is present, while the inverted array 0 is reversed if a 1 is present. An example of the externally generated input signals is the presence of a sensor is a logical 1 as long as it is present. the package is in front of an infrared beam of light. An example of the general state variable internally results from the consecutive error of the counter which increases the presence of the sensor once at a time in part of the packet without the tag in the packet being coded. When the counter reaches the programmed limit value, this retains the state variable up to 1. This state variable can then be used by combinatorial logic to establish or release the output signals on the machine, such as a stop signal machine. Referring to Figure 4, the combinatorial logic contains 2 gate arrays, the array Y and the array 0. The state variables are each entered into the logical array. For each entry there are also 2 programmable variables, the ENABLED and the INVERTED. The complete equation for the output GMBx (x = i) in terminal 430 of Figure 4 is: output (i) 430 = Inverted (Y_result [i] 422? Y_total_inverted [i] 424) + (O_result [i] 422? 0_total_inverted [i] 444), where: Y_result [i] 422 = (entry (j) 06? Y_inverted (i, j) 414 • Y_allowed (i, j) 418 and O_result (i) 422 = (entry (j) 406 F O_inverted (i, j) 434 • O_enabled (i, j) 438 The following symbols are provided as follows: F means exclusive O operation; F means exclusive non-OR operation; • means Y function; + means function O, and is a sum for the number of terms. There are M input state variables, designated as input (j) 406. There are multiple output signals designated as outputs (i) 430. For each input in each output equation there is an inverter for the input, and both arrays Y are designated as Y_inverted (i, j) 424. For each input in each output equation there is an inversion variable, designated as O_inverted (i, j), for input in both arrays OR. For each input in each output equation there is a variable enabled, designated as Y_activated (i, j), for the outputs in both Y arrangements. For each exit occasion there is one enabled, designated as 0_activated (i, j), for the output in both O arrangements. For each output there is an inversion variable, designated as Y_total_inverted ( i), to change the equation Y to a non-Y equation. For each output there is an investment variable, designated as Or total_inverted (i), to change the equation O to a non-O equation. An event will trigger the calculation of the output states for one or more outputs. For example, if an event triggers the calculation of the output (5) then the previous equation will execute i = 5. Figure 6 shows a functional block diagram of an output conditioning module 600 that receives the input terminal 602 of the output signal GBMx, where GMBx is provided for the terminal 430 of the combinatorial logic phase of the input system module and output of Figure 4. The signal at the input terminal 602 is routed using mutually exclusive switches 603a, 603b either directly through the signal line 604 to the output conditioning module 606 or, alternatively to the input terminal of a change register module 608. 4 register module are available in such a way that up to 8 change registers are available in simple form or in pairs like IA to IB, 2A to 2B, etc. Each module can be assigned with any of the GMBx output. Both 1 or 2 changers can be placed in any of the output streams. If the value of the change register is not 0 this will cause a change operation, otherwise the signal goes directly to the next module.

The clock input to the shift register goes through multiplexer 610, 611 allowing a separate selection of the clock input, in the same way as the clock inputs towards combinatorial retention. This provides internal clock pulses or external inputs that include the presence of inputs. The rejection / verification test block is related to any of the entry and exit points.

Therefore, when the GMBx output signal propagates through the input and output points, the reject / verified test block is started, if its timer is not 0. The rejected timer is started when the output is started. If the rejected timer ends before a transition detects in the verified input, the rejected / verified status (x) bit in the input status register will be successful. If the bit is released during the next slow periodic update cycle, ensuring that an entry and exit point will be captured at the state change. Additionally, output of the combinatorial phase CMB00 -CMB31 are available through a multiplexer to a clock in any of the 6 configurable event counters. The remainder of the conditioning module from the output includes an output conditioning sub-module containing a pulse output timer 612 and a retainer 614. The input to the timer 612 or the retainer 614 is obtained using exclusive mutually exclusive switches 615a, 615b. The operations of the pulse output timer and the retainer are mutually exclusive so that when the output pulse is selected, the retainer is reselected and vice versa. The timing module of the pulse output 612 or pulsor, provides a pulse output with a programmable duration. The pulse output is able to be activated again. If the new actuator fills before the pulse is complete, the pulse time restarts and the pulse continues. If the pulsor is not set to 0, then the pulser module acts similar to a cutter and passes the state of the signal to the output circuit. Likewise, the pulse always starts in a transition from 0 to 1. The pulse timer is programmed from 2 milliseconds to 2 seconds. The retainer 614 is always driven from an input that goes from the state of 0 to 1. When the output of the retainer occurs, the output level remains until the retainer is released. The signal that releases the retainer is selected with a multiplexer similar to the clock selector for an input retainer. The signals that are released from the retainer are: the keyboard signal, serial command, and the selected external input. The retainer also has a bit enabled that can cause the name of an output that is written on the screen and also to a series of ports. The screen is locked until it is released by the keyboard. This allows an alarm message to be displayed. After a signal comes out the retainer or the pulsor, it is fed into a gate 0 of 2 inputs 616. The output of the gate 0 is fed to an inlet of a gate 0 Exclusive 618. The other input terminal of the gate 618 receives an NC / NO signal that determines whether the final input and output signal (00-31) at the TERMINAL IS NORMALLY OPEN OR NORMALLY CLOSED, (which refers to the final output output). The output terminal then directly connects a physical output device. The output at terminal 430 is also available for an entry retainer. This allows logical circuits to be chained as well as creating circuits, for example oscillators. The PMC80 series of the master investment controllers includes 4 sets of counters 452 for each of the 4 barcode scanners. 2 additional sets of 4 counters are available, of which 6 can be arranged on a map for the combinatorial outputs of the modules. The first of three counters in each group of 4 performs specific counting tasks while the fourth buyer is used for totals and is increased each time one of the 3 counters is increased. If these additional sets of counters are enabled, a screen program shows 3 counters and a printing routine prints these counters. A letter 10 that modifies the names is available for the counters which are identified as G, N, W, A, B, C, D, E, F, and T. Table 1 shows the values of different control signals that they are established during system initialization to obtain a specific input and output configuration.

TABLE 1; Application = Sample; output bit anode = Hold, WC_Hl, Shft Reg 3A (6), output bit # = 01 01; Clock source 00-17 (00 = dis) 0; Counter 0-6 (0 = dis) 6; Changer 0-8 (0 = dis) L = Link 00; Rejection and verification timer 0- (0 = none) 0; Investor AND teacher 0; Inverter O master 0; AND INV O INVES AND ENABLED OR ENABLED 0 or 0 0 0 or good reading head 1 0 0 0 or good reading head 2 0 0 good reading head 3 0 or 0 0 good reading head 4 0 0 0 0 or head without reading 1 0 0 0 or head without reading 2 0 0 head without reading 3 0 or 0 0 head without reading 4 uo 1 0 or reading head erroneous 1 or 0 0 or reading head erroneous 2 or 0 0 misreading head 3 oo 0 0 misreading head 4 oo 0 0 head cer 1 oo 0 0 head cer 2 oo 0 0 head cer 3 oo 0 0 head cer 4 oo 0 0 o / rjvfla o 0 0 rjvflb oo 0 0 rjvf2a oo 0 0 rjvOb oo 0 0 rjvf3a oo 0 0 rjvf3b oo 0 0 rjvf4a oo 0 0 or rjvf4b .- 'or 0 0 or head 1"ciisabled or 0 0 or head 2 disabled or 0 0 oo head 3 disabled 0 0 oo head 4 disabled 0 0 no ps hl oo 0 0 no ps h2 0 or 0 0 no ps h3 0 or 0 0 no ps h.4 oo 0 0 e / s 00 oo 0 0 e / s 01 e / s 02 oo 0 0 oe / s 03 or 0 0 oo 0 0 e / s26 oo 0 0 e / s 27 oo 0 0 e / s28 e / s2g oo 0 0 ei s o o 0 0 e / s 30 o o 0 0 e / s 31 WCH1 Output name (maximum duration 10) NO; NO or NC Retention; Retention Enabled; Hold that presents the flag enabled / disabled Enabled; Retention released by the keyboard for Enabled / Disabled 00; Retention releasing the selection 00-16 (00 not released) The foregoing descriptions of the specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended that it be exhaustive or that the limit of the invention in the precise form presented, and obviously many modifications and variations are possible in view of the fact that it is not taught above. The embodiments have been selected with the aim of better explaining the principles of the invention and their practical application, thus enabling those skilled in the art to better utilize the invention and the different embodiments with various modifications as appropriate. has suited for the particular use contemplated. It is intended that the scope of the invention be defined in the claims appended hereto and their equivalents.

Claims (17)

1. CLAIMS 1. A configurable input and output system, comprising: an input state array having a plurality of state variables represent 2 input variables; a logic function mechanism for operating on the plurality of state variables and for providing a logical output signal; the actuator mechanisms for the synchronized operation of the mechanisms of the logic function with an actuator event.
2. 2. A configurable input and output system according to claim 1, which includes the mechanisms of the multiplexer for selecting an actuator event from a plurality of functions of the actuator.
3. 3. A configurable input and output system according to claim 1 including an output signal conditioner for conditioning the logic output signal.
4. 4. A configurable input and output system according to claim 1 including the mechanisms for initially configuring the logic function mechanisms.
5. 5. A configurable input and output system according to claim 1 wherein the mechanisms of the actuator include the mechanisms for detecting a preselected input event.
6. 6. A configurable input and output system according to claim 5 wherein the actuator mechanisms include the functional distribution mechanisms for placing a preselected input event detected in a row of circular events and for removing the detected pre-selected input event from the row of circular events; and wherein the logic function mechanisms for operating on a plurality of state variables and for providing a logic output signal including the mechanisms for executing a predetermined function in response to the preselected input event.
7. A configurable input and output system according to claim 6 wherein the mechanisms of functional distribution include the mechanisms for mapping the event through a table for the logical function mechanisms that include the combinatorial logic calculation routine and where the mechanisms of functional distribution include the mechanisms to initiate the execution of a combinatorial logic routine.
8. 8. A configurable input and output system according to claim 1 wherein the logic function mechanisms include a software simulator of a programmable array.
9. 9. A configurable input and output system according to claim 8 wherein the programmable array is an array of AND gates by which the outputs can be specified with the logic functions of inputs.
10. A configurable input and output system according to claim 1 wherein the input values are state variables consisting of external signals, internally generated signals, counter states, change register states, and retention states.
11. 11. A configurable input and output system according to claim 10 wherein the external signal includes a signal degenerating from a presence sensor.
12. 12. A configurable input and output system according to claim 11 wherein the signal that is generated from the presence sensor includes a signal generated when an object is ahead of infrared light.
13. 13. A configurable input and output system according to claim 6 wherein the internally generated signals are variables of the internally generated state that is provided by a consecutive error counter.
14. 14. A configurable input and output system, comprising an input state array for receiving a plurality of input signals and having a plurality of elements respectively corresponding to one of the input signals; a holding arrangement that has elements to receive and store the states of the elements of the input state array; the mechanisms for controlling a clock signal provided in the holding arrangement for the synchronized operation of the system with the occurrence of the clock signal an array of the inverter Y having the elements to receive and selectively invert the elements of the retention mechanisms; an array of multiple entries; an input selection array Y for directing a corresponding bit from the holding array on one of the outputs of the multi-input array Y; an output inverter Y to selectively invert the output of the array Y of multiple inputs; an arrangement of the inverter OR having elements to receive and selectively invert the elements of the retention mechanisms; an array of multiple entries; an input selection array O for directing a corresponding bit from the holding array on one of the outputs of the array of multiple inputs; an output inverter O to selectively invert the output of the OR array of multiple inputs; a gate 0 for combining the outputs of the output inverter Y and the output inverter O.
15. 15. A configurable input and output system comprising a first array 0 exclusive to logically combine each of the respective elements of a state array of input with the respective elements of an inverted array Y; a first arrangement and to logically combine each of the respective elements of the exclusive 0 array with each of the respective elements of an enabled array Y; a first array O to logically combine the respective elements of the array Y into a single element; a first exclusive inverter array for combining a single array element OR with an inverter command signal to selectively provide an inverter or a non-inverted Y output signal; a second exclusive OR arrangement for logically combining each of the respective elements of the input state array with the respective elements of the inverted array O; a second array Y to logically combine the respective elements of the second exclusive OR array with the respective elements of an array enabled O; a second array O to logically combine the respective elements of the second array Y into a single element; a second inverted or exclusive array to combine a simple array element 0 with an inverted command signal to selectively provide an inverted or non-inverted output signal 0; an output 0 function to logically combine the inverted or non-inverted Y output signal with an inverted or non-inverted output signal 0 to provide an output signal.
16. 16. A configurable Y / O system according to claim 15 including an output signal conditioner for the output signal that alternately provides the direct channels to the output terminal, the shift registers, the pulse circuit, and a retention circuit.
17. 17. A configurable input and output system according to claim 15 wherein the output signal is provided to a counter.