MXPA97002495A - An extended memory system of architecture deharv - Google Patents

Abstract

The present invention relates to an extended memory system in a computer having a central processing unit, a data memory, a program memory, a first communication path between said central processing unit and said program memory, and a second separate communication path between said central processing unit and said data memory, said extended memory system comprising: first storage means for containing an ordered sequence of program memory addresses, wherein each of said memory addresses of program is associated with a different group of instructions which, in turn, are contained in said program memory, and second storage means for containing a series of groups of related data values, said second storage means include, at least , a unit of memory and logical means, said logical means include a plurality of registers that are able to address, separately and alternately, said second storage means, said logical means provide a plurality of programmable address increments for each memory unit, said programmable address increments include, at least, an increment by one, an increase endos, an increase in four, and an increase in an integer greater than one, said logic means further include an address register which, in turn, includes, at least, a decoder to detect an increment signal of address retrieved from said program memory by said central processing unit, said address increment signal determines a magnitude of said programmable address increment for said second storage means; said first and second storage means are each connected to a data collector associated with said second communication path separated by di cha dat memory

Description

AN EXTENDED MEMORY SYSTEM OF HARVARD ARCHITECTURE The present invention relates generally to computer architectures and particularly to an extended memory system for a computer based on the Harvard architecture. A computer that includes the following two characteristics is generally considered to have a "Harvard" architecture. Namely, the computer will be designed with instruction and data stores and independent collectors will be provided to allow the central processing unit ("CPU") of the computer to communicate separately with each of these stores. This is different from a computer architecture based on "von Neumann" or "Princeton", which generally uses the same physical store for both instructions and data and a single collector structure to communicate with the "CPU". Several approaches have been taken to design a microcomputer or microprocessor with a Harvard architecture, as represented by the following patents: Yasui et al., U.S. Patent. No. 5,034,887, issued on July 23, 1991, entitled "Microprocessor With Harvard Architecture"; Portanova et al., Patent of E.U.A. No. 4,992,934, issued February 12, 1991, entitled "Reduced Instruction Set Computing Apparatus And Methods"; Mehragardt et al., Patent of E.U.A. No. 4,964,046, issued October 16, 1990, entitled "Harvard Architecture Microprocessor With Arithmetic Operations And Control Tasks For Data Transfer Handled Simultaneously"; and Simpson, Patent of E. U.A. No. 4,494, 187, issued January 15, 1985, entitled "Microcomputer With High Speed Program Memory." Additionally, it should be noted that the "I ntel ¡860" 64-character microcomputer has been described as having a Harvard architecture on board, due to the provision of separate instruction and data cache routes. In this regard, a description of integrated circuit design of "I ntel i860" can be found in i860 Microprocessor Architecture, by Neal Margulis, Osborne McGraw-H ill, 1990. The use of separate instruction and data communication paths. In a Harvard architecture machine, it effectively increases the overall speed of the computer by allowing access to an instruction at the same time that data is accessed for this or another instruction. In the context of scheduled operations, the instruction is usually referred to as the "opcode" (the operation code), and the data is called the "operand". While the speed benefit from the use of the Harvard architecture is significant, the full potential of a machine based on Harvard architecture has yet to be realized. More specifically, it is thought that substantial advantages can be achieved by directing the nature, roles and potential cooperation between separate memory stores in a machine that is based on the Harvard architecture.

Accordingly, it is a primary objective of the present invention to provide a unique memory system that significantly extends the capacity of the Harvard architecture. It is another object of the present invention to provide an extended memory system that reduces the amount of memory space required to store a computer program. It is a further object of the present invention to provide an extended memory system that allows at least two different memory access procedures to be used. It is a further object of the present invention to provide an extended memory system that reduces the time required for frequently repeated memory operations. It is also an object of the present invention to provide an extended memory system that more effectively utilizes a desired data structure. It is still another object of the present invention to provide an extended memory system that is particularly advantageous in a process control computer. To achieve the above objectives, the present invention provides an extended memory system which includes an address store for containing an ordered sequence of program memory addresses and a store of values for containing a series of groups of related data values. Both the address store and the store of values are preferably connected to the same data communication path that is used by a separate data memory of the computer.

The address store determines the sequence of operations that will be implemented through its program memory address stack. In this regard, each of these program memory addresses identifies the location of the first instruction of a particular sub-routine that is contained in the program memory. The address store may also contain the address of one or more subroutine arguments which, in turn, is contained either in the value store or in the data memory. Therefore, the address store can be used as a location server for both the program memory and the data memory of a computer that is based on the Harvard architecture. The stock store also includes a logical interface to allow a plurality of different address increments to be programmably selected. This variable increment capability is particularly advantageous in a process control environment where a relatively large number of input values need to be read, transformed and evaluated quickly. For example, it may be useful for a process control computer to generate an expanded group of data values for each input signal that has been received from a particular process sensor. Assuming that a predetermined data structure is used for these groups of data values, then the number of steps required to register or retrieve this data can be substantially reduced by changing the address increment used with the value store. The additional features and advantages of the present invention will be more fully apparent from a reading of the detailed description of the preferred embodiment and the accompanying drawings in which: Figure 1 is a block diagram of a computer that characterizes a extended memory system according to the present invention. Figure 2 is a block diagram of the memory circuits Q and C of the extended memory system shown in Figure 1. Figures 3-3E represent a schematic diagram of the memory circuit Q. Figures 4-4A, represent a schematic diagram of the memory circuit C. Figures 5-5D, represent a schematic diagram of the programmable logic device of the Q register shown in Figure 3. Figures 6-6D, represent a schematic diagram of the programmable logic device of the register C shown in the Fig. 7-7E, represent a schematic diagram of the programmable logic device of the register D shown in Figure 4. Figure 8 is a diagrammatic illustration of the operation of the circuits of memory Q and D. Figure 9 is a diagrammatic illustration of the operation of memory circuits P and C. Referring to Figure 1, a block diagram of a computer 10 is shown. Computer 10 includes a Central Processor and Control Unit ("CPU") 12. According to one embodiment of the present, the "C PU" "12, is based on the processor" MI PROC "of" Radstone Technology pie ". However, it should be appreciated that other "CPU" or microprocessor circuits can be used and that the principles of the present invention are not limited to any particular construction or integration of the "CPU". It should also be appreciated that all circuits in the computer 10 can be integrated into a single integrated circuit of the microcomputer in the appropriate application. In accordance with a strict Harvard architecture configuration, the computer 10 includes a data memory 14, a program memory 16, and a separate collector structure for each of these memories. In this regard, the data memory 64k 14 is provided with a data collector 18 ("PC Collector"). The computer 10 also includes an index switch circuit 26, which allows the "CPU" 12 to access the data in the data collector 18. More specifically, index switch circuit 26, provides a 16-character address that is derived from one of eight address modes. The address mode is selected by the instruction to be executed. While the computer 10 employs a 16 character structure, it should be understood that in the appropriate application, other suitable collector widths may be employed. Similarly, the storage capacity of the data memory 14 and the memory a of the program 16 can also be altered. However, one of the advantages of the extended memory system of the invention is that the memory size of the program 16 may be considerably smaller than what might otherwise be required with a conventional Harvard architecture. Additionally, program memory 16 may use random access memory ("RAM"), electrically programmable read-only memory ("EPROM"), or a combination of both to store program instructions, as will be described below and operation system. For example, you can use the EPROM to store the operation system and those subroutines that are not likely to be changed, while RAM can be used to store those subroutines that may be more likely to be updated. The memory of the program 16 may also employ other suitable memory circuits in the appropriate application, such as EEPROM and snapshot memory. as shown in Figure 1, the computer 10 also includes a control collector 28, a priority interrupt collector 30, and a Programmable Interface 32. The Programmable Interface 32 provides a programmable port for input and output operations. In other words, the Programmable Interface 32 can be configured to receive input signals that are representative of analog and digital values of various sensors and is configured to transmit output signals for one or more control devices. Additionally, the Programmable Interface can be also use to receive and transmit communication signals. According to the present invention, the computer 10 includes an extended memory system 36, which is generally represented by the block marked "Q &C Memory" (Memory of Q and C) in Figure 1. As will be seen in In relation to Figure 2, the extended memory system 36 includes two separate memories, which are preferred herein as the memory Q and memory C. However, it should be noted in Figure 1, that both of these memories are connected to the data collector 18. The memories Q and C also receive control signals that are decoded in the memory of the program 16, such as "Q_operation" (operation of Q_) and "C_operation" (operation of C_).

Referring to Figure 2, a block diagram of the extended memory system 36 is shown. The extended memory system includes a group of compensators 100, which are used to receive various control and direction signals. These control and direction signals are selectively transmitted to three different registers, namely, register Q 102, register C 104 and register D 106. Thus, for example, register Q 102 will receive the signal of "Q_operation", while register C 104, will receive the signal "C_operation". However, these three registers will receive certain common signals, such as the memory clock signal ("MEMCLKB") and certain address signals from the memory data collector of program 22. The Q 102 register controls the operation of a memory circuit Q 256K 108. The memory circuit Q is provided to store an ordered sequence of memory addresses that ultimately defines the particular program that will be implemented by the computer 10. In great contrast to the normal programs that have been compiled and linked, the application program for the computer 10 is divided only between the memory of the program 16 and the memory circuit Q 108. In this respect, the memory of the program 16, is used to store the instructions, or "opcode", for a common group of subroutines that can be used in a variety of application programs. Therefore, for example, the memory of the program 16 may contain a number of different arithmetic and logical subroutines, such as to add two numbers together and expressions of "IF ... THEN".

In comparison, memory circuit Q 108 is designed to store address information which is associated with these subroutines. More specifically, the memory circuit Q 108 is adapted to store the addresses of these subroutines, such as the addresses of the first instruction of a subroutine, in an orderly sequence to define the computer program. Preferably, memory circuit Q 108 also stores the addresses of any arguments that may be required by these subroutines. These arguments, or operands, can be found in the data memory 14 or in the memory circuit C 110 which will be described below. With this division of responsibility to store the application program, it must be understood that the routines used by the program only need to be stored once, although they can be used repeatedly throughout the program. Therefore, only a minimum amount of storage capacity is required for the application program in the computer 10. The use of Q memory also has other advantages. For example, the speed of execution can be increased, because the normal subroutine, such as the promotion of one or more addresses in a stack, is avoided. Additionally, the subroutine arguments can easily be changed by a programmer without having to collect the program. Instead, the value of the argument can be changed directly in the memory location referenced in the memory Q. The memory circuit C 110 is controlled alternately by the register C 104 and the register D 106. The circuit of memory C 110, is adapted to store data values and in this regard, memory circuit C 110, can be used to the extent of the storage capacity that could otherwise be provided by the data memory 14. However, of In accordance with the present invention, register C 104 is designed to allow access to memory circuit C 110 in increments that can be varied automatically by program instructions. As will be described later, the memory circuit C 110 can be accessed in increments of one or two addresses, depending on the instruction used. In other words, an explicit instruction can be given to advance a counter in the register C 104 which determines the currently accessible address of the memory circuit C 110. The register D 106 is used in order to have access to two memory tables. different data in the memory circuit C 110 without having to transfer address pointers inside and outside the memory. In other words, the counter contained in register C 104 can be signaled to the address of a data table in memory circuit C 110 (where an address increment greater than one could be useful), while the counter contained in the register D 105, points to the address of another data table in the memory circuit C (where an address increment of one is appropriate). It should also be observed from Figure 2 that both the memory circuit Q 108 and the memory circuit C 110 are connected to the data collector 18. The memory circuit Q 108. it is connected to the data collector 18 through the data compensators 112, while the memory circuit C 110 is connected to the data collector through the data compensators 114. Consequently, it should be noted that the writing and reading operations for the memory circuit Q 108 and the memory circuit C 110, they are effectively multiplexed via the control signals "Q_operation" and "C_operation". A pair of address compensators 116 is also provided to present the current direction of the Q register 102 to an analyzer unmanner device connector. The current direction of the register Q 102 can also be read by the "CPU" 12 through the data compensators 112. In view of the fact that the ordered sequence of addresses in the memory circuit Q 108 defines the steps that will be implemented by the computer 10, the current direction of the memory circuit Q 108, provides another way of determining the current state of the programmed operations. Referring to Figures 3-4A, a schematic diagram of the extended memory system 36 is shown. The control line compensators 100 are shown comprised of a three-state octal compensator / line driver circuit U10 (74AS541), and three gate circuits "AND" U4, U12 and U39 (7408). The line driver circuit U10 receives the four less important characters of the memory data collector of the program 22 (PMO-PM3), two input / output control signals (1016, I029) and the two memory address characters Q most important (QA16-QA17). The use of these signals will be described later in connection with Figures 5-5D. The gate circuits "AND" U4, U12 and U39, will operate as compensators, since an input is connected to each of the internal AND gates to a reference of +5 volts. The conditions of the AND gate circuit U4 enable the signal "EMR", the memory read / write signal "R / W" and the memory clock signal "MEMCLK". The letter "B" is added to the label for these signals at the outputs to indicate that they represent compensated versions of the signals received from the control manifold 28. Similarly, the AND gate circuit U12 is used to compensate for the "Q_operation" signals. "and" C_operation ". The AND gate U39 is used both to compensate and to replicate the "CPU" clock signal of the "CPU" 12. The Q register is shown as comprised of an 18-character programmable logic device U1 ("PLD") and a pair of ocular line drivers U21 and U22 (74AS541). In the present embodiment, the PLD is a specific integrated circuit of gate 2100 application (EP1810), which has been programmed as shown in Figures 5-5D. However, it should be appreciated that other suitable logic circuits can be employed in the appropriate application. PLD U1, allows the "CPU" 12 to set or read an internal counter and increment this counter by one when instructed to do so. PLD U1 pulls out sixteen of the eighteen address lines to the memory array Q 108, while internally demultiplexes the two remaining major address lines to select one of four RAM banks 64k U23-U38 (6208) in the sort order. memory Q. In this regard, the RAM bank 0 is comprised of memory integrated circuits U23, U27, U31 and U35. Similarly, the RAM bank 1 is comprised of memory integrated circuits U24, U28, U32 and U36; the RAM 2 bank is comprised of memory integrated circuits U25, U29, U33 and U37; and the RAM 3 bank, is comprised of memory integrated circuits U26, U30, U34 and U38. Figure 3 also shows that the address compensators Q 116 are comprised of a pair of line drivers U7-U8 (74AS541) and two lines of the line driver U10. Additionally, Figure 3A shows that data compensators 112 are comprised of a pair of transceivers U5 and U6 (74AS645). Switching to Figure 4-4A, a schematic diagram of the register C 104, the register D 106 and the memory arrangement C 110 is shown. The register C 104 is comprised of a PLD U2 of 16 characters and the register D 106 is comprised of a PLD U3 of 16. characters, This circuit arrangement is similar to that described above in relation to the Q register 102 and the Q 108 memory arrangement, except that the programming for the C and D registers is different and the memory arrangement C 110 only has one bank memory card U15-U18 (6208). Both the C 104 register and the D 106 register allow the "CPU" 12 to be set or read in its internal 16-character counters and incremented by one when instructed. However, as indicated above, register C 104 also includes the ability to employ additional memory access procedures with increments by integers greater than one. In one form of the present invention, the register C 104 is programmed to allow increments of two and four. However, it should be appreciated that increments of additional or different integers may also be provided under the principles of the present invention. Additionally, it should be noted that the collector lines of the register C 104 and the register D 106 are compensated (via ocean line drivers U13-U14 and U19-U20) and united in common with the address collector C to the memory arrangement C 110. Similarly, data compensators 114 are shown comprised of a pair of ocular transceivers U9 and U11. These transceivers are provided to connect the data collector of memory C to the data collector "B" 18. Referring to FIGS. 5-5D, a schematic diagram of the register Q 102 (PLD U1) is shown. While the Q-register 102 has been provided with 20-character address capability in this particular mode, it is nevertheless treated as an 18-character address counter when the memory locations of 256k are physically contained in the memory circuit Q 108. Accordingly, the register Q 102 includes a group of five up / down counters of 4 characters 200-208, which operate to specify the address of the memory circuit Q 108. It should be understood that a greater or lesser number can be used. of ascending / descending counters, and that the specific circuit modes described herein are intended to be illustrative only of the principles of the present invention. However, the registration! 102 is constructed in this mode to set, read or increment the ascending / descending counters 200-208 in order to determine the current direction of the memory circuit Q 108. Each of the ascending / descending counters 200-208, receives a clock signal, such as CP4 for the counter 202. While the separate clock signals are generally displayed for these counters, it is only because the PLD EP1810 is divided into four ports. Consequently, it should be understood that the clock signals CP1, CP2, CP3 and CP4 represent the same clock signal. Since each of the counters 200-208 are similarly arranged, the counter 202 in Figure 5 will be described as a representative example. The counter 202 includes four data input ports which are connected to the input / output signal lines marked B12, B13, B14 and B15. The counter 202 may be loaded with the value of these lines of input / output signals by the signal line SETLSB4, which is connected to the port enabling the counter load. As indicated by the signal line marking, each of the data output ports of the counter 202 are connected to its input / output signal lines through a group of compensators 210-216. Consequently, the output signals Q12F, Q13F, Q14F and Q15F can be read from the input / output signal lines by activating the compensators 210-216 through the signal RDLSB4. The signals SETLSB1-4 and RDLSB1-4, as well as the signals SETMSB and RDMSB, are decoded from the signals in the selected lines of the data collector of the program memory 22 and the control collector 28, as indicated in Figure 3. These lines of the program memory data collector are marked IDO-ID3, and one of the control lines is marked 11016. As shown in Figures 5A-5C, a group of 1 of 8 decoders 218-232, are used to demultiplex each of the signals "SET ... "to write an address value in counters 200-208, and signals" RD ... "to read an address value of these counters. Figure 5D also shows a decoder 234, which is used to demultiplex the selected signals of the QBANKO-3 integrated circuit. As indicated above, the register Q 102 also includes the ability to increase the direction of the current directions of the memory circuit Q 108. The instruction for this operation is detected through the decoders 236-238 in Figure 5C. In this regard, it should be noted that the decoder 236 also receives the Q_operation signal, which is marked IQPO in Figure 5C. The decoders 236-238 produce the ADD1 signal that is routed to the carrier input port of the counter 208. The ADD1 signal may cause the address generated by the Q register 102 to advance by the value of the integer of one. Referring to Figures 6-6D, a schematic diagram of the C 104 record (PLD U2) is shown. As in the chaos of the Q 102 register, the C register includes a set of 4 character up / down counters 300-304 to specify 12 characters of the address for the memory circuit C 110. Similarly, the C register 104. includes a set of decoders 306-308 to produce the signals SETLSB and RDLSB. However, the register C 104 not only has the ability to control the reading and writing of the memory circuit C 110, but the register C also has the ability to control a plurality of address increments for the memory circuit C. In this regard, a set of decoders 310-312 is provided for demultiplexing an ADD1 signal, an ADD2 signal and an ADD4 signal. As the name of these signals implies, the register C 104 is capable of causing the address for the memory circuit C 110 to be increased by one, two or four. However, it should also be appreciated that the register C 104 may also be configured to increase the address of the memory circuit C 1 10 by other values of integers. In order to implement the capacity for variable address increments in the memory circuit C 1 10, the register C 104 includes a counter circuit 314 which is shown in Figures 6A-6C. This counter circuit 314 effectively takes place of the 4 character up / down counter which could be used otherwise to specify the 4 least important characters of the address for the memory circuit C 1 10. The counter circuit 314 includes a group of four abrupt changes 316-322 which are used to specify the four important characters of the address for the memory circuit C 1 10. For example, the abrupt change 316, is responsible for the increment signal ADD1 and the signal of CK1 watch. The abrupt change 316 is alternatively responsible for a combination of the ISETLSB signal and also the B0F signal or the C0F signal through the OR gate 326. The I SETLSB signal represents the SETLSB signal after it has been processed through the inverter 324. Consequently, as long as the current direction value of the register C 1 -4 is being read by the "CPU" 12, the output of the sudden change 316 is presented again at its input port through the XOR gate 328 and the gate AN D 330. The output signal of the sharp change 316 is also connected to the next sharp change 318 through gate AN D 332 in order to pass the less important previous character up the chain when the signal is received. ADD1. in a similar way, abrupt change 318 receives signal ADD2 when an increment is required by the value of the integer of two. Also, the third abrupt change 320 receives the outputs of both the first abrupt change 316 and the second abrupt change 318, and processes the three increment signals ADD1, ADD2 and ADD4. while the third sudden change 320 pass a signal add4"HIGH" through its output C2F upon the transition of appropriate clock signal, the ADD2 signal needs to be combined with the output of the second abrupt change 318 (via AND gate 334), and signal ADD1 needs to be combined with output signals from both the first and the second abrupt change 316-318 (via gate AND 336). Similar logic processing is also provided for the fourth abrupt change 322. For example, in order to cause an increase in the address of the memory circuit C 110 by four when the output signal C3F was "LOW", then the ADD4 signal needs combined with an output signal "HIGH" C3F of the third abrupt change 320 (via AND gate 338). Referring to Figures 7-7E, a schematic diagram of register D 106 (PLD U3) is shown. As in the case of the register Q 102 and the register C 104, the register D 106 includes a set of up / down counters of 4 characters 400-406 to specify the address of the memory circuit C 110. Similarly, the register D 106, includes a set of decoders 408-410 to produce the signals SETLSB and RDLSB. In addition to reading and writing, the register D also includes the ability to increase the current direction for the memory circuit C 110 through the signal ADD1 shown in Figure 7E. This signal from ADD1 is detected through the decoders 412-414, and transmitted to the carrier input port of the counter 406. Referring to FIGS. 8 and 9, two diagrammatic illustrations of the operation of the extended memory system are shown 36 Figure 8 specifically illustrates the division of responsibility between the memory circuit Q 108, the memory circuit P (program) 16 and the memory circuit D (data) 14 through the use of a simple "add" subroutine. In this regard, a portion of the "Q list" 500 is shown by identifying an illustrative group of memory locations Q and the data contained therein. For example, the value 3284 is stored in memory location Q AOOO, while the value 8291 is stored in the following memory location Q A001. A comment box is arranged adjacent to each of these address / data groups in the memory Q, so that the meaning of the list Q can be seen. In this particular portion of the list Q 500, the "CPU" 12 It has been programmed to add numbers together. Consequently, the Q AOOO memory location is used to store the start address for the "ADD" subroutine. The next two memory locations Q are used to identify the address of the two numbers to be added together. In this specific example, two analogous constants of "AC" will be added together.

It should also be noted that these values of these two analogous constants can be easily changed by the programmer without having to collect the Q 500 list. The last place in the memory Q in this portion of the Q 500 list is the start address to a subrrutine "STORE". Figure 8 also diagrammatically shows a portion of the memory of the program 16. This portion of the program memory 16 represents the subroutine "ADD" called from the list Q 500. The first instruction for this subroutine is an instruction to obtain the first argument address of the memory Q 108. This is achieved by causing the Q register 102 to increment by one the current memory address Q, and then by reading the value of the data collector "B". Since this value represents a memory location in the data memory circuit 14, the next instruction in the program memory is a command to obtain the data value AC (1) at this location in the data memory. The ADD subroutine then obtains and adds the second AC data value (2) for the first AC data value (1), and then returns to the next memory location in the Q 500 list. Figure 8 also diagrammatically shows three places adjacent memory in the data memory 14. In this regard, the data value of 0064 for AC (1) is stored in memory location 8291, while the data value 00C8 for AC (2) is stored in the location of memory 8293.

Turning now to Figure 9, a subroutine "AILoop" is shown diagrammatically in the memory of program 16. This particular subroutine has the advantage of a data structure section shown in memory C 110. In this example, each input signal analogous "Al" is stored in memory as an associated group of four different values. Therefore, the signal set for the analog input signal Al (1) includes a value of "Field" representing the pure signal received by the "CPU" 12, a value of "voltage" representing a processed value of the field signal, a graduation factor and a graduated version of the processed signal. In any case, it should be understood that a plurality of analog input signals need to be stored in memory, an illustrative data structure is used to store these values in adjacent groups of four. As a result, the variable increment capacity of the C 104 register is used in the AILoop subroutine in order to cause each analog input "field" signal value to be read and then stored in successively separate places in the memory C 110. More specifically, the command signal ADD4 is used to increase the memory C 110 by the value of the integer of four, since each analog input "field" signal is to be stored. This is shown by the "STAC4" instruction in the program memory in memory address AA15. As a result, it should be appreciated that it is necessary to exceed the minimum processing in order to read and store many signal values in the memory C 1 10. The present invention has been described in an illustrative form. In this regard, it is evident that those skilled in the art once they have received the benefit of the foregoing description, can make modifications to the specific embodiments described herein without departing from the spirit of the present invention. Such modifications will be considered within the scope of the present invention which is limited only by the scope and spirit of the appended claims.

Claims (21)

1. CLAIMS 1. In a computer having a data memory, a program memory and separate communication paths between a central processing unit of said computer and said data and program memories, an extended memory system comprises: first storage means to contain an ordered sequence of program memory addresses, wherein each program memory address is associated with a different group of instructions, which, in turn, are contained in said program memory; and second storage means for containing a series of groups of related data values, said second storage means includes at least one memory unit and logical means for providing a plurality of programmable address increments for said memory unit; said first and second storage means each being connected to a data collector in a communication path for said data memory. The invention according to claim 1, wherein said logic means includes a plurality of registers that are capable of separately and alternately directing said second storage means. The invention according to claim 1, wherein said programmable address increments include at least one increment by one and an increment by an integer greater than one. 4. The invention according to claim 3, wherein said programmable address increments include an increment by two, and an increment by four. The invention according to claim 1, wherein said first storage means includes at least one memory unit for containing said memory addresses of the program and each one of said program addresses contained in said first storage means, is the address in such program memory of the first instruction for a group of instructions representing a particular programmed procedure. 6. The invention according to claim 5, wherein said memory unit of said first storage means includes the address in said data memory of an argument during at least one of said programmed procedures. The invention according to claim 5, wherein said memory unit of said first storage means includes the address in said second memory of an argument of at least one of said programmed procedures. The invention according to claim 1, wherein said logic means includes an address register, which in turn includes at least one decoder for detecting an address increment signal recovered from such program memory by said unit. of central processing that determines the magnitude of the address increment for such second storage means. The invention according to claim 1, wherein said program memory includes both volatile and non-volatile memory circuits. 10. The invention according to claim 1, wherein said logic means includes a control register which in turn includes a compensating circuit that allows the current direction output of said control register to be read over said collector. data. 11. In a computer (10) having a data memory (14), a program memory (16), and separate communication paths (18, 20, 22, 24) a central processing unit (12) of said computer in such data and program memories, an extended memory system comprising: storage means (36) for containing an ordered sequence of program memory addresses, wherein each memory address of the program is associated with a different group of instructions that, in turn, are contained in said program memory (16); said storage means each being connected to a central processing unit. 12. The invention according to claim 11, wherein said storage means (36) are connected to a data collector (18) in a communication path for said data memory (14). The invention according to claim 11, wherein said storage means (36) includes at least one memory unit (102) for containing said memory addresses of the program and each memory address of the program contained in said means storage is the address in said memory of the program (16) of the first instruction for a group of instructions representing a particular programmed procedure. The invention according to claim 13, wherein said memory unit (102) of said storage means (36) includes the address in said data memory (14) of an argument for at least one of said procedures programmed. 15. On a computer having a data memory, a program memory and separate communication paths between a central processing unit of said computer and said data and program memories, an extended memory system comprising: storage means of values to contain a series of groups of related data values, said storage means of values being connected to a data collector in a communication path for said data memory, said storage means of values including at least one memory unit and logic means for providing a plurality of programmable address increments for said memory unit. The invention according to claim 15, wherein said programmable address increments include at least an increment by one and an increment by an integer greater than one. The invention according to claim 16, wherein said programmable address increments include an increment by two, and an increment by four. The invention according to claim 17, wherein said logical means includes a plurality of registers that are capable of separately and alternately directing said second storage means. The invention according to claim 15, wherein said logic means includes a control register, which in turn includes at least one decoder for detecting an address increment signal retrieved from said program memory by such unit of central processing that determines the magnitude of the address increment for said second storage means. 20. The invention according to claim 15, wherein said groups of related data values form part of a data structure. twenty-one . The invention according to claim 15, wherein said logic means includes a control register that is capable of causing a data value to be stored at predetermined address locations in said value storage means and then the current address said storage means of values is increased by an integer greater than one of a single instruction retrieved from said program memory. R ES U M EN An extended memory system of Harvard architecture that characterizes an address store to contain an ordered sequence of program memory addresses and a store of values to contain a series of groups of related data values. Each of the addresses contained in the address store is associated with a different group of instructions, such as a subroutine, which is contained in the program's memory. The address store may also contain the address of one or more instruction arguments which, in turn, are contained in the stock store or in a separate data store. Both the address store and the store of values are preferably connected to the same data communication path used by the computer's data memory. The stock store also includes a logical interface to allow a plurality of different address increments to be selected programmably.