MXPA96006747A - Phase cycle secured with response time controla - Google Patents

Abstract

A configuration for selectively controlling the response time of a secured phase cycle (PLL) type II (919), especially one that includes a phase detector (921-9) and an amplifier (921-11) of a type Integrator feedback inside an integrated circuit (921), comprises a controllable filter stage (925-2) cascaded with the amplifier (921-11). The filter stage (C3, C4, R2, R4, R5) and a switching configuration (Q2, Q3) to selectively bypass the filter section (C3, C4, R2, R4, R5), in response to a control signal determining the mode. In the described embodiment, the phase locked cycle (919) controls the frequency of a local oscillator (911) of a tuner (9) and the filter section (C3, C4, R2, R4, R5) has an amplitude response against frequency to increase the response time of the secured phase cycle (919) during a fine tuning mode, such that a demodulator (11) can continue to operate properly during the tuning mode.

Description

INSPECTED PHASE CYCLE WITH CONTROLLABLE RESPONSE TIME The invention relates to an assured phase cycle (PLL) with a controllable filter, to selectively control the response time of the assured phase cycle. Secured phase cycles (PLLs) are used in a variety of applications to "secure" the frequencies and / or phase of a controllable oscillator to that of a reference signal. For example, secured phase cycles are commonly employed in communication equipment tuners, such as radio and television receivers, to control the frequency of a local oscillator. An assured phase cycle includes a controllable oscillator for the generation of a controlled oscillator signal, a stable oscillator, such as a crystal oscillator, for the generation of a reference signal, and a phase detector for the generation of a signal of error, representing the phase and frequency relationships between the controlled oscillator signal and the reference signal. The error signal contains pulses that have either a relatively positive polarity, or a relatively negative polarity, depending on the direction of the phase and frequency differences between the input signals of the phase detector, and the duration of a variable that depends of the magnitude of the phase and frequency differences. The error signal is filtered by a filter, known as the "cycle filter", to generate a control signal. The control signal is coupled to the controlled oscillator to control the frequency, and hence the phase, of the controlled oscillator signal, in a feedback manner. As will be described later, depending on the type of phase locked cycle, either the frequency difference or the frequency and phase differences will be minimized in response to the control signal. At that point, it is said that the assured phase cycle is "insured". In a tuner, the controlled oscillator is used as the local oscillator of the tuner, and a "programmable" frequency separator is coupled between the controlled oscillator and the phase detector. In this case, the error signal represents the phase and frequency differences between the split frequency version of the local oscillator signal, produced by the programmable frequency separator, and the reference signal. When the assured phase cycle is ensured, the frequency of the local oscillator signal, generated by the controlled oscillator, is proportional to the frequency of the reference signal by the programmable division factor (usually referred to as "N") of the programmable frequency separator. The use of an assured phase cycle in a tuner has many advantages. The frequency of the local oscillator is very stable, since the frequency of the local oscillator is assured to that of the reference signal. In addition, the frequency of the local oscillator signal can be easily controlled, for example, to change channels, by digitally controlling the programmable division factor (N) of the programmable frequency separator. As noted above, depending on the type of phase locked cycle, either the frequency difference or the frequency and phase differences will be minimized in response to the control signal. In a "Type I" phase locked cycle, the error signal is coupled to a simple low pass filter network. An assured phase I type cycle only minimizes the frequency difference between the input signals of the phase detector. In a "Type II" phase locked cycle, the error signal is coupled to an integrator that includes an amplifier and a filter section configured in a feedback configuration. A phase II assured phase cycle minimizes both frequency and phase differences between the input signals of the phase detector due to the feedback cycle of the integrator. An assured phase II type cycle is useful in applications where both frequency stability and phase stability are desirable. Sometimes it is desirable to selectively change the response time of the secured phase circuit. In a type I assured phase cycle, this can be easily achieved by means of selectively changing the cycle filter, in response to a control signal. For example, the integrated circuit (IC) of the secured phase cycle of tuning control MB1507 includes an electronically controllable switch, which can be "turned on" to derive a first of two external low pass filter sections, which are coupled in cascade between an error signal output of the integrated circuit, and the control signal input of the local oscillator, in order to decrease the time required to tune to a new channel. However, the present inventor has recognized that it is much more difficult to selectively change the response time of a Type II assured phase cycle, without changing the basic nature of the assured phase cycle, or without significantly increasing the complexity of the cycle of cycle. insured phase. One reason for this is that the filter network is included in the feedback path of the integrator, rather than directly cascaded with the output of the phase detector. Another reason is that a significant number of the phase-locked phase components, including the phase detector and the integrator amplifier, are usually included in an insured phase-locked integrated circuit, and therefore, are not accessible for modification. . These problems are aggravated when it is desired to increase rather than selectively reduce the response time of the assured phase cycle. With such difficulties in mind, the inventor has invented, in accordance with one aspect of the invention, a configuration for selectively controlling the response time of a Type II secured phase cycle configuration, especially one that includes the phase detector. and the feedback type amplifier of the integrator inside an integrated circuit. More specifically, an additional filter section is cascaded with the integrator amplifier, and a filter control section is coupled to the additional filter section, to modify the operation of the additional filter section, in response to a signal of control that determines a mode. In accordance with another aspect of the invention, the filter control section comprises a switching configuration for selective shunting of the additional filter section, in response to the mode determination control signal. In accordance with yet another aspect of the invention, the additional filter section has an amplitude versus frequency response, to increase the response time of the secured phase cycle, in response to the mode determination control signal.

These and other aspects of the invention will be described in detail, with respect to the accompanying drawings. In the drawings: Figure 1 is a block diagram of a digital satellite television receiver, including a tuner system, with reference to which a preferred embodiment of the invention will be described. Figure 2 includes a block diagram of a * integrated phase locked phase control tuning circuit, which is used in the tuner system shown in Figure 1, and a schematic diagram of a circuit implementation of a controllable phase locked phase filter, which it is constructed in accordance with an aspect of the invention. Figure 3 is a flow diagram of a microprocessor control program for the tuner system shown in Figure 1. Figure 4 is a block diagram of a digital data demodulator for use in the satellite receiver that is shown in Figure 1, and it is useful to understand a problem to which an aspect of the invention is directed. Figure 5 shows a graphical representation of the amplitude versus frequency response characteristics associated with the controllable phase-locked filter shown in Figure 2, in accordance with an aspect of the invention. In the different Figures, the same or similar reference designations are used to identify the same or similar elements. The invention will be described with reference to a digital satellite television system in which television information is transmitted in encoded and compressed form, in accordance with a predetermined digital compression standard, such as MPEG. MPEG is an international standard for the coded representation of moving image and audio information, developed by the Group of Experts in Moving Images. The DirecTvMR satellite television transmission system operated by the Hughes Corporation of California, is this digital satellite television transmission system. In the transmitter, the television information is digitized, compressed and organized into a series or stream of data packets corresponding to respective portions of video and audio of the television information. The digital data is modulated on a radiofrequency carrier signal, in what is known as QPSK modulation (Quaternary Phase Shift Keying), and the radio frequency signal is transmitted to a satellite in the Earth's orbit, from which it is transmitted back to Earth. In the quaternary phase shift keying modulation, the phases of two quadrature phase signals, I and Q, are controlled in response to the bits of the respective digital data streams. For example, the phase is set to 0 degrees (°) in response to a low logic level ("0"), and the phase is set to 180 ° in response to a high logic level ("1"). The modulated I and Q signals in phase change are combined, and the result is transmitted as a modulated radiofrequency carrier signal in Quaternary phase shift keying. In accordance with the above, each cycle of the modulated quaternary phase shift keying carrier indicates one of four logical states, ie, 00, 01, 10 and 11. A satellite typically includes a number of transponders, to receive and re-transmitting the respective modulated radiofrequency carriers. In a conventional terrestrial television system, each radiofrequency carrier or "channel" contains information only for one television program at a time. In accordance with the above, to see a program, you only need to select the corresponding radio frequency signal. In a digital satellite television system, each radiofrequency modulated carrier carries information for many programs simultaneously. Each program corresponds to groups of video and audio packages that are identified by a single header attached to the packages, which identifies the program. In accordance with the above, to see a program, you need to select both the corresponding radio frequency signal and the corresponding packages. In the digital satellite television receiver shown in Figure 1, radio frequency signals modulated with digital signals representing video and audio information that have been transmitted by a satellite (not shown), are received by an antenna in the form of dish 1. The received radiofrequency signals of a relatively high frequency (for example, in the Ku frequency range between 12.2 and 12.7 GHz) are converted by a block converter 3, including a radio frequency amplifier 3-1, a mixer 3-3 and an oscillator 3-5, in radiofrequency signals of relatively lower frequency (for example, in the L band between 950 and 1450 MHz). The amplifier 3-1 is a "low noise" amplifier, and therefore, the block converter 3 is often referred to by the initials "LNB" by "low noise block converter". The antenna 1 and the low noise block converter 3 are included in a so-called "outdoor unit" 5 of the receiving system. The remaining portion of the receiver is included in a so-called "indoor unit" 7.

The indoor unit 7 includes a tuning system 9 for selecting the radiofrequency signal containing the packets for the desired program, from the plurality of radio frequency signals received from the outdoor unit 5, and for converting the selected radio frequency signal to a corresponding lower intermediate frequency (IF) signal. One aspect of the present invention relates to the construction of the tuning system 9 and will be described later in detail. The remaining portion of the indoor unit 7 demodulates, decodes, and decompresses the digital information carried in the form of a quaternary phase shift keying modulation by the intermediate frequency signal, to produce digital video and audio sample streams corresponding to the desired program, and, after that, converts the digital sample streams into respective analog video and audio signals, suitable for reproduction or recording. More specifically, a quaternary phase shift keying demodulator 11 demodulates the intermediate frequency signal to produce two IP and QP pulse signals containing respective data bit streams corresponding to the data represented by the modulated I and Q signals phase change generated in the transmitter. A decoder 13 organizes the bits of the IP and QP signals into blocks of data, corrects the transmission errors in the data blocks based on the error codes that have been embedded in the data transmitted in the transmitter, and reproduces the packets of data. MPEG audio and video transmitted. The video and audio packets are directed by a transport unit 15 to respective video and audio sections of a data processing unit 17, where they are decompressed and converted into respective analog signals. A microprocessor 19 controls the operation of different sections of the indoor unit 7. However, only the control signals generated and received by the microprocessor 19 necessary to describe an embodiment of the present invention are indicated in FIG. The digital satellite television receiver described so far is similar to the digital satellite system RCAMR type DSSMR television receiver commercially available from Thomson Consumer Electronics, Inc., of Indianapolis, Indiana. As stated above, one aspect of the present invention is related to the building uncle 1 tuning system 9. The tuning system 9 receives the radio frequency signal provided by the low noise block converter 3 at an input 901. The signals radio frequency input are filtered by a wideband filter 903, amplified by a radio frequency amplifier 905 and filtered by a tunable bandpass filter 907. The tunable bandpass filter (BPF) 907 selects the desired radio frequency signal and rejects unwanted radiofrequency signals. The resulting radiofrequency signal is coupled to a first input of a mixer 909. A local oscillator signal produced by a local oscillator (LO) 911 is coupled to a second input of the mixer 909. The output of the mixer 909 is amplified by an amplifier 913, and coupled to the input of an intermediate frequency filter 915 comprising a surface acoustic wave device. The output of the intermediate frequency filter 915 is coupled to the output 917 of the tuning system 9. The frequency of the local oscillator 911 is controlled by an assured phase cycle (PLL) configuration 919 comprising an integrated circuit (IC) 921 of assured phase cycle, an external frequency reference crystal 923, and an external filter network 925. The frequency of the local oscillator signal is controlled by the secured phase cycle 919, in accordance with the data generated by the microprocessor 19 Fig. 2 shows details of the assured phase cycle 919. As shown in Fig. 2, the phase locked phase integrated circuit 921 includes a "prescalar" frequency separator 921-1 to divide the frequency of the local oscillator signal, followed by a programmable frequency separator (-I-N) 921-3. The integrated phase-locked circuit 921 also includes an amplifier 921-5, which in combination with the outer glass 923, comprises a reference frequency oscillator. The output of the reference frequency oscillator is coupled to the input of a reference frequency separator (- ^ R) 921-7. The output signals of the programmable separator (- ^) 921-3 and the reference separator (-fR) 921-7 are coupled to respective inputs of a phase detector 921-9. The output signal of phase detector 921-9 is an error signal representing the frequency and phase differences between the split frequency version of the local oscillator signal produced at the output of the programmable separator (-? - N) 921-3 and the reference signal produced at the output of the reference spacer (-i-R) 921-7. The error signal contains pulses that have either a relatively positive polarity or a relatively negative polarity, depending on the phase direction and the frequency differences between the input signals of the 921-9 phase detector, and a variable duration that depends on the magnitude of phase and frequency differences. The error signal is coupled to an amplifier 921-11, which together with the external filter network 925, comprises a cycle filter 927, for filtering the error signal, to produce a tuning control voltage for the local oscillator 911 The tuning control voltage also controls the tuneable bandpass filter 907. The cycle filter 927 is constructed in accordance with one aspect of the invention and will be described later in detail. In operation, the frequency of the local oscillator signal is controlled in response to the tuning voltage, until the frequency and phase of the split frequency version of the local oscillator signal produced at the output of the programmable separator (- ^ - N) 921-3, are substantially equal to the frequency and phase of the reference signal produced at the output of the reference spacer (-R) 921-7. At that point, the assured phase cycle is "secured", and the frequency of the local oscillator signal is proportionally related to the frequency of the reference frequency signal produced by the reference frequency separator (- ^ R) 921 -7 by the programmable division factor (N) of the programmable separator (- ^ N) 921-3. The programmable division factor N is controlled in response to data generated by the microprocessor 19, in order to control the frequency of the local oscillator. For reasons of cost, it is desirable that the tuning system 9 has the following three characteristics: (1) comprising only a single conversion stage before the intermediate frequency filter stage; (2) that provides an intermediate frequency signal with a frequency low enough to allow a surface acoustic wave device to be used for so-called "digital symbol configuration" as well as normal intermediate frequency filtering; and (3) which is capable of being constructed using an integrated phase locked phase control tuning circuit, which is conventionally used for broadcast and cable receivers. Basically, these goals are achieved by: (1) selecting an intermediate frequency center frequency that is in the order of the difference (eg, 140 MHz) between the highest frequency of the radio frequency signal received from the frequency converter. blocks (for example, 1450 MHz) and the highest frequency of the local oscillator (for example, in the order of 1300 MHz), available through the use of a phase-locked integrated circuit of conventional terrestrial broadcasting control and tuning by cable; and (2) the use of a local oscillator signal with a frequency range q e 'is lower than, rather than higher than, the frequency range of the received radio frequency signals. In the exemplary tuning system, the center frequency of the intermediate frequency signal is 140 MHz. However, other intermediate frequencies are possible, using the guidelines stated above.

A relatively low intermediate frequency center frequency, for example, in the order of 140 MHz, allows a single conversion tuner to be used rather than a more expensive double conversion tuner, before the intermediate frequency filter section. This also allows a surface acoustic wave device, which provides so-called "digital symbol configuration", as well as a normal intermediate frequency filtering to be used. In a digital transmission system, what is known as a "digital symbol configuration" in the transmitter is performed to reduce inter-symbol interference, due to the limitations of the transmission bandwidth. It is also desirable to perform the digital symbol configuration on the receiver, to complement the digital symbol configuration performed on the transmitter. In addition, it is desirable that the intermediate frequency filter allows the symbol configuration, as well as the normal intermediate frequency filtering function, such that a separate digital filter is not required. As an example, what is known in the. Digital filter technique as a "high root cosine" response is suitable for the digital symbol configuration. The intermediate frequency 915 surface acoustic wave filter has such a response. The amplitude versus frequency characteristic of the surface acoustic wave filter 915 is shown in Figure 1. It has a center frequency of 140 MHz, and a relatively flat pass band of approximately 24 MHz, which corresponds to the bandwidth of the bands. received radio frequency signals. In the patent application of the United States of America with serial number 08 / 467,095, entitled "SAW Filter for a Digital Satellite Receiver Tuner", filed on June 6, 1995, for KJ Richter, MA Pugel and JS Stewart, and which is assigned to the same assignee of the present application, describes in detail a surface acoustic wave filter with these characteristics, which utilizes a lithium tantalate substrate. In addition, with an intermediate frequency center frequency of 140 MHz, and a frequency range of radio frequency input between 950 and 1450 MHz, the frequency range of the local oscillator is between 810 and 1310 MHz. The frequency range of 810- 1310 KHz of the local oscillator signal, allows the phase-locked phase control integrated circuits to be used, which are conventionally and widely used for broadcast and cable receivers, and which are therefore relatively inexpensive, more rather than an integrated phase-locked tuning control circuit, specially designed for satellite receivers. Such an integrated control cycle of phase locked tuning of broadcasting and cable is the TSA5515T, commercially available with Philips Semiconductors of the Netherlands and others. The maximum frequency of the local oscillator available using the TSA5515T and circuits. similar integrated, is in the order of 1300 MHz, which is adequate. The portion of the tuning system 9 described so far is the subject of the abovementioned United States patent application, serial number 08 / 467,097, entitled "Digital Satellite Receiver Tuner", filed on 6 June 1995, for MA Pugel and KJ Richter, and which is attached to the same assignee as the present application. The present invention specifically relates to provisions for controlling local oscillation 911 during the acquisition and fine tuning operation, which will now be described. The carriers of the radiofrequency signals transmitted by the satellite and received by the antenna 1, have very stable frequencies that remain in "nominal" values. Therefore, as long as the frequency of oscillator 3-5 of the low noise block converter 3 is stable and remains at its nominal value, the frequencies of the carriers of the radiofrequency signals received by the tuning system 9 of the indoor unit 7, will be at their nominal values. Unfortunately, the frequency of oscillator 3-5 can change with time and temperature. The frequency offsets of the oscillator 3-5, with respect to its nominal frequency, cause corresponding shifts of the carrier frequencies of the radio frequency signals received by the tuning system 9. To compensate for these frequency shifts, the frequency of the local oscillator 911 of the tuning system 9, under the control of the microprocessor 19, in response to information on the status of the frequency received from the quaternary phase shift keying demodulator, during two search operations. In Figure 3 the flow diagram of the microprocessor control program 19 for the tuning system 9 is shown, including the search operations. A first search may occur during an acquisition mode, after a new program is initially selected. When a new program is selected, the microprocessor 19 causes the local oscillator frequency to be set to a nominal local oscillator frequency corresponding to the nominal radio frequency of the transponder for the new program. After this, the state of a LOCK signal generated by the quaternary phase change keying demodulator 11 is monitored. The signal LOCK indicates whether the quaternary phase change keying demodulator 11 is operating correctly or not to demodulate the digital data carried by the intermediate frequency signal. For example, the signal LOCK has a low logic level when the quaternary phase shift keying demodulator 11 is not properly demodulating the digital data, and the signal LOCK has a high logic level when the quaternary phase shift keying desorulator is not. 11 is demodulating the digital data appropriately. If the LOCK signal has the logic level low after the local oscillator frequency has been set to the nominal local oscillator frequency, for the selected transponder, the frequency of the local oscillator 911 is changed to a range around the oscillator frequency local nominal, until the LOCF signal has the high logic level. The generation of the signal LOCK indicates the start of a stable state operation mode of the tuning system 9. During the steady state mode, a FREQUENCY signal generated by the quaternary phase shift keying demodulator 11 is monitored, to determine whether or not the frequency of the carrier of the intermediate frequency signal is centered within the pass band of the intermediate frequency surface acoustic wave filter 915, that is, if the carrier frequency of the intermediate frequency signal is on the frequency nominal intermediate frequency center, for example, 140 MHz in the present modality. The performance of the quaternary phase shift keying demodulator 11 will be degraded, and data errors will occur, if the frequency of the intermediate frequency carrier falls outside a predetermined range around the nominal center frequency. If the FREQUENCY signal indicates that a predefined frequency offset has not been exceeded, the frequency of the local oscillator 911 is changed to the left of the initial value set during the acquisition mode. However, if the FREQUENCY signal indicates that a predefined frequency offset has been exceeded, the frequency of the local oscillator 911 is changed during a second "fine tuning" search operation until the situation is corrected. One aspect of the present invention is directed to solving a problem that could occur during the fine tuning mode, as will now be explained. It has been found that the tuning system 9, which comprises the phase locked circuit integrated circuit 921 for terrestrial and cable broadcasting, works very satisfactorily under most circumstances. However, the secured phase loop integrated circuit 921 of terrestrial tuning has certain limitations that could result in temporary loss of video and / or audio information. The size of the smallest frequency changes of a local oscillator controlled by an assured phase cycle is related to the value of the smallest possible increments of the programmable division factor (N) of the programmable separator (- ^ - N), and with the frequency of the reference signal of the phase-locked integrated circuit 921. The phase-locked phase-locked-phase integrated circuits, such as the TSA5515T, are capable of changing the frequency of the local oscillator signal only in relatively large incremental frequency steps, for example, 62.5 KHz. As a result, during the two search operations, the carrier frequency of the intermediate frequency signal will change in the same relatively large steps. Unfortunately, the quaternary phase shift keying device 11 may not be able to track those relatively large frequency steps, possibly resulting in an interruption of the appropriate demodulation operation, and a loss of video and audio data. If a first search operation occurs during the acquisition mode, the loss of data is not noticeable, because a viewer will expect that the acquisition process for a new program will take some time. However, if the second operation or fine tuning operation becomes necessary during the steady state mode, the video and / or audio responses of the program currently being viewed may be interrupted. The possibility of such interruptions is reduced, by reducing the "rate of turn" of the secured phase cycle configuration 919, ie, the rate at which the tuning voltage is allowed to change the amplitude, during the tuning operation fine. More specifically, the response time of the cycle filter 927 increases in response to a FINE TUNING control signal generated by the icroprocessor 19. The problem to which this solution is directed will now be described in more detail, with respect to Figure 4 , which shows a block diagram of an implementation of the quaternary phase shift keying demodulator 11. As shown in FIG. 4, the intermediate frequency signal produced by the intermediate frequency acoustic wave filter 915 is coupled to the first respective inputs of the mixers 11011 and 1101Q. The letters "I" and "Q" mean "in phase" and "square". The output signal of a relatively stable frequency oscillator 1103 is directly coupled to the mixer 11011, and indirectly coupled to the mixer 1101Q by a phase change network 1105 of 90 degrees (90 °). The mixer 1101 E produces a baseband version "IA" in "phase", "near" (much lower frequency) of the intermediate frequency signal, while the mixer 1101Q produces a baseband version (QA) in "quadrature" ", close, of the intermediate frequency signal, which is changed 90 degrees with respect to the signal" in phase "(IA). The letter "A" means "analog." The signals IA and QA are coupled to respective analog-to-digital converters (ADCs) 11071 and 1107Q. Analog-to-digital converters 11071 and 1107Q also receive a clock signal from a "timing recovery cycle" 1109, and produce respective series of digital samples ID and QD. The letter "D" means "digital." The frequency and phase of the clock signal determine the frequency of the digital samples, and also the phase of the digital samples of the digital signals ID and QD relative to the analog signals IA and QA. The timing recovery cycle 1109 includes a controlled oscillator (not shown), from which the clock signal for analog-to-digital converters 11071 and 1107Q is derived. The controlled oscillator is controlled by a digital secured phase cycle (not shown) in such a way that the digital samples are synchronized with corresponding amplitude levels of the analog signals IA and Qa, ie the maximum and minimum sample values correspond with the maximum and minimum amplitudes of the analog signals. In other words, the timing recovery cycle 1109 synchronizes the sampling operation of the analog-to-digital converters 11071 and 1107Q with the intermediate frequency signal. Signals 1D and QD are also encrypted. U "" carrier recovery cycle "1111. The carrier recovery cycle 1111 demodulates the phase changes of the analog signals IA and QA representing the digital sample signals ID and QD, in order to form respective pulse signals IP and QP . The letter "P" means "impulse". Each of the IP and QP pulse signals contains a series of pulses corresponding to data bits. The data bits have either a low logic level ("0") or a high logic level ("1") corresponding to the phase changes of 0o and 180 °, respectively, of the I and Q signals of the radio frequency transmitter of transmitted Quaternary phase change. The IP and IQ signal components are coupled to the decoder 13, where the different data bits are formatted into MPEG data packets. The carrier recovery cycle 1111 includes a digital phase locked cycle (PLL) comprising a controlled oscillator 1111-1, a phase detector 1111-3 and a cycle filter 1111-5. The phase detector 1111-3 generates a phase error signal in response to the ID and QD signals, and to the output signal of the controlled oscillator 1111-1. The nominal frequency and the nominal phase of the output signal of the controlled oscillator 1111-1 corresponds to the nominal frequency and the nominal phase of the intermediate frequency signal and, therefore, to the nominal frequency and the phases of the analog signals IA and QA, and with the corresponding digital sample signals ID and QD. In operation, the phase changes of the signals represented by the ID and QD signals can be determined reliably from the phase error signal, if the phase and the frequency of the intermediate frequency signal are correct. However, if the date and the frequency of AI and QA are incorrect, the detected phase changes will not be at 0o or 180o, instead they will be changed from these values. In essence, a phase error causes an "inclination" of the "position" of the two-bit demodulated data, with respect to the ideal position of the two-bit data in a so-called "constellation" of data. A frequency error, for example, due to a frequency offset derived from the low noise block converter of the selected radio frequency signal, causes over time a so-called "rotation" of the position of the two-bit demodulated data of the Quaternary phase shift typing signal. The direction of rotation depends on whether the frequency offset is positive or negative. As shown in Figure 4, the data constellation for the Quaternary phase shift keying modulation has four points corresponding to the four possible logical combinations (00, 01, 10 and 11) of the respective two possible logical levels, represented by the two possible phase change values of the I and Q signals. The phase detector 1111-3 measures the position of the demodulated data, in relation to the ideal position in the data constellation. To correct the data rotation and tilt, the frequency, and hence the phase, of the output signal of the controlled oscillator 1111-1 is changed in response to the output signal from the phase detector 1111-3, until the rotation stops and the inclination is eliminated. In this point, the demodulated data is reliable and it is said that the cycle is "secured". A high-level SECURED signal is generated to indicate that the data is being demodulated reliably and can be decoded. The INSURED signal is generated by examining the derivative of the phase error signal, to determine when the change in the phase error falls below a previously determined limit. As noted above, during the acquisition mode, the microprocessor 19 monitors the signal SECURED, and the icroprocessor 19 adjusts the frequency of the local oscillator 911, until the INSURED signal has a high logic level. Within limits, the carrier recovery cycle 1111 can demodulate the quaternary phase shift keying data, even when the frequency of the intermediate frequency signal, and therefore the frequency of the signals IA and Qa is incorrect or is outdated However, if the frequency offset is too large, a portion of the frequency spectrum of the intermediate frequency signal will fall outside the passband of the surface acoustic wave filter 915, due to the change of the intermediate frequency signal with relation to the center frequency of the surface acoustic wave filter 915. This will cause a degradation of the signal to a noise ratio of the receiver. Accordingly, as stated above, the microprocessor 19 monitors a signal FREQUENCY generated by the carrier recovery cycle 1111, to indicate the frequency offset of the intermediate frequency signal. If the frequency offset exceeds a previously determined limit, the microprocessor 19 causes the frequency of the local oscillator to adjust to reduce the frequency offset during the fine tuning mode. The FREQUENCY signal is generated by integrating the phase error detected by the phase detector 1111-3. As stated above, the frequency of the local oscillator signal, and hence the frequency of the intermediate frequency signal, changes in relatively large frequency steps, for example 62.5 KHz, and may not be possible for the scrambler Quaternary phase shift keying 11 track such relatively large frequency steps. As a result, an interruption of the appropriate demodulation operation, and a loss of video and audio data may occur. The ability of the quaternary phase shift keying demodulator 11 to track relatively large frequency changes is a function of the cycle bandwidth of the carrier recovery cycle 1111, and more specifically the response of the cycle 1111 filter. 5. The cycle bandwidth of the bearer recovery cycle 1111 should not be made arbitrarily large, in order to decrease its response time, because an increased cycle bandwidth would degrade the signal to receiver noise characteristics and, therefore, both, the ability of the receiver to receive low level signals. It is also not desirable to decrease the cycle bandwidth of the secured phase cycle 919 in order to decrease its response time, because a decreased response time would result in excessively long acquisition times, when selecting frequencies, of new transponders. As stated above, to reduce the possibility of interrupting the demodulation process during the fine tuning operation, the response time of the secured phase cycle 919 of tuning control is increased selectively to reduce the index to which it is allowed changing the tuning voltage, and therefore the frequency of the local oscillator 911, during the fine tuning operation. Now this solution will be described in detail.

Referring again to Figure 2, and more particularly to the portion of the circuit marked "CYLINDER FILTER 927", as described above, the cycle filter 927 includes the amplifier 921-11 inside the phase-locked integrated circuit 921 , and an external filter net 925. The external filter net 925 includes a first filter stage 925-1 and a second filter stage 925-2 controllable, which are coupled in cascade between the internal amplifier 921-11 and the oscillator local 911. The first stage of filter 925-1 and the amplifier 921-11 of the integrated phase-locked circuit 921 form an integrator. More specifically, the first filter stage 925-1 includes a bipolar transistor Ql configured as a common emitter amplifier. The base of the transistor Ql is connected to the output of the amplifier 921-11 via a terminal of the integrated circuit. The emitter of the transmitter Ql is connected to ground signal. A load resistor R6 is connected between the collector of the transistor Ql and a source of a supply voltage (+ VCC). A section of the filter, which includes a resistor R1 and the capacitors Cl and C2, is connected in a negative feedback path between the collector of the transistor Q1 and the input of the amplifier 921-11 via a terminal of the integrated circuit to complete the integrator. The feedback is negative due to the signal inversion provided by the transistor Ql configured as a common emitter. The use of an integrator comprising the amplifier 921-11 and the first filter stage 925-1, connected in a negative feedback configuration, makes the phase locked cycle 919 a phase-locked type II cycle. An assured phase II phase cycle minimizes both phase and frequency differences between the split frequency version of the local oscillator signal, developed at the output of the programmable frequency separator (- ^ N) 921-3, and the signal of reference frequency developed at the output of the reference frequency separator (-fR) 921-7, and therefore stabilizes both the phase and the frequency of the local oscillator 911. The second filter stage 925-2 includes a section of two-pole, two-zero filter, including resistors R2, R4 and R5, and capacitors C3 and C4, and an electronically controlled switching section, comprising the field effect transistor Q2 and the resistor R3 of relatively low value . The conduction state of the transistor Q2 is controlled in response to the FINE TUNING signal generated by the microprocessor 19. The second filter section 925-2 is selectively controlled to either effectively derive the two-pole filter section, double zero (R2, R4, R5, C3 and C4), or to include the two-pole filter section, double zero in the path between the first filter section 925-1 and the local oscillator 911. More specifically, when the tuning system 9 is not in the fine tuning operation mode, the FINE TUNING signal has a low logic level, and the conduction channel of the transistor Q2 is caused to be in the low impedance state, or "on" . As a result, the resistances of the elements R2, R4 and R5, and capacitors C3 and C4 of the second filter section 925-2 are effectively derived due to the "on" transistor Q2 and the resistor R3 of relatively low value. In the fine tuning mode, the FINE TUNING signal has a high logic level, and the conduction channel of the transistor Q2 is caused to be in the high impedance state, or "off". As a result, the resistors R2, R4 and R5 and the capacitors C3 and C4 of the second filter section 925-2 are connected in the path between the first filter section 925-1 and the local oscillator 911. The amplitude Bode against the Frequency characteristic for the double zero filter section (R2, R4, R5, C3 and C4) of the second filter stage 925-2, shown by itself in the Figure as feature # 1. Amplitude levels they are indicated in decibels (dB) and the frequency axis is logarithmic. It is seen that feature # 1 contains two "poles" Pl and P2, and two "zeros" Zl and Z2, which occur in the order: pole Pl, zero Zl, zero Z2 and pole P2, at successively higher frequencies. The pole Pl is due to the resistance R2 and the capacitor C4; zero Zl is due to resistance R2 and capacitor C3; zero Z2 is due to resistance R5 and capacitor C4; and the pole P2 is due to the resistance R5 and the capacitor C3. Figure 5 also shows two Bode amplitudes against frequency characteristics of the overall cycle response of phase locked cycle 919. Feature # 2 is the cycle response when tuning system 9 is not in fine tuning mode , and the cycle filter 927 includes only the first filter stage 925-1, that is, the two-pole, double-zero filter section (R2, R4, R5, C3 and C4) of the second stage of the filter is derived. filter 925-2. Feature # 3 is the response of the cycle when the tuning system 9 is in fine tuning mode, and the cycle filter 929 includes the first filter stage 925-1 and the double-zero filter section, double zero (R2, R4, R5, C3 and C4) of the second filter stage 925-2 coupled in cascade. Feature # 3 has not been drawn to scale in terms of amplitude, with respect to features # 1 and # 2, to avoid overlapping features. Recalling that the overall amplitude versus the frequency characteristic of two stages connected in cascade results in the multiplicative product of the two individual characteristics, or the additive product when the amplitudes are expressed in decibel levels (dB), characteristic # 3 is the result of the additive combination of features # 1 and # 3. A pole of feature # 1 causes an increase in the slope (negative direction) of feature # 3. A zero of feature # 1 causes a decrease in the slope (negative direction) of feature # 3. The pole Pl reduces the overall cycle gain and, therefore, the overall cycle bandwidth. Without zeros Zl and Z2, the slope of feature # 3 would cross the amplitude level of 0 dB, with an inclination of more than 20 dB per decade of frequency, causing the cycle to be unstable and, therefore, subject to oscillations. Pole P2 occurs incidentally due to the topology of the circuit that requires resistance R5 and capacitor C3. However, the pole P2 is convenient because; it reduces the cycle gain (i.e., increases attenuation) for off-band signals, such as the reference frequency signal of the phase locked cycle 919. In Figure 5 it is seen that when the tuning system 9 it is not in the fine tuning mode (feature # 2), the cycle band amplitude is relatively large and, therefore, the response of the secured phase cycle 919 is relatively fast. In contrast, when the tuning system 9 is in the fine tuning mode (feature # 3), the cycle band amplitude is relatively small and, therefore, the response of the phase-locked cycle 919 is relatively slow. In the implementation of the second filter stage 925-2 shown in Figure 2, it is desirable that the resistor R4 isolate the output of the first filter stage 925-1 (in the collector of the transistor Ql) from the capacitor C4 , for the following reasons. The capacitor C4 has a relatively large capacitance. Without resistor R4 (that is, if resistor R4 were replaced with a direct connection), the capacitor C4 and resistor R5 series connection would be directly connected in bypass to the output of first filter stage 925-1, when the tuning system is in the acquisition mode, and the switching transistor is "on". This would tend to undesirably increase the acquisition time. However, the resistor R4 of relatively high value isolates the output of the first filter stage 925-1 from the capacitor C4 and, by the same, does not allow the capacitor C4 to significantly increase the acquisition time. further, with respect to capacitor C4 valued relatively high, it may be desirable to provide a previously determined time delay, before allowing the fine tuning operation to start after the acquisition mode, to allow the capacitor C4 to charge (or discharge) the voltage of tuning generated during the acquisition operation. The microprocessor 19 can provide that delay under the control program, as indicated in the flow chart shown in Figure 3. As shown in Figure 2, it may be desirable to add a dynamic "acceleration" circuit 925- 3 for the first filter stage 925-1, to change the response time of the secured phase cycle 919, in order to accelerate the acquisition operation. The acceleration circuit 925-3 includes bipolar transistors of the opposite conductivity type of push-pull Q3 and Q4, and a resistor R7. The common connected bases of transistors Q3 and Q4 are connected to one side of the capacitor Cl, and the emitters connected in common are connected, via resistor R7, to the other side of capacitor Cl. The collectors of transistors Q3 and Q4 are connected to respective sources of oppositely polarized supply voltages + VCC and -VCC. The following table shows the exemplary component values for the external filter network 925. Component Value resistance Rl 24 K (iloohms) capacitor Cl 4700 pf (picofarads) capacitor C2 0.1 μf (microfarads) resistance R6 2 K resistance R7 10 K resistance R2 1 M (megaohm) capacitor C3 0.27 μf resistance R3 2 K resistance R4 20 K resistance R5 470 ohm capacitor C5 220 μf In operation, when a large frequency change occurs, such as when a new transponder frequency is selected, a large error signal is generated, and a corresponding large voltage is developed through the resistor Rl. Depending on the polarity of the change, one of the transistors Q3 or Q4 will "turn on" and "charge" or "dissipate" current. This results in an effective increase in cycle gain (ie, feature # 2 is changed up), and a consequent decrease in acquisition time. As the phase locked cycle 919 approaches the desired frequency and the error signal decreases, the "on" transistor goes "off". In the patent application of the United States of America with serial number 08 / 504,849, entitled "Rapid Action Control System", filed on July 20, 1995, for David M. Badger, and assigned to the same assignee of the present application, an acceleration circuit, similar to the acceleration circuit 925-3, as well as other acceleration circuits are described in detail. Although the present invention has been described by way of example, in terms of a specific modality for a particular application, those skilled in the art will appreciate that modifications can be made to suit other applications. In this aspect, the invention can be employed whenever it is desired to change the response time of an assured phase cycle configuration, using a negative feedback type of the integrator, in which a filter section is included in the feedback path of an amplifier. Furthermore, in this aspect, although the invention has been described with respect to an application that requires an increase in the cycle response time, the invention can be used to decrease the response time of a cycle. In addition, although the invention has been described in terms of a specific circuit topology, the invention is applicable when other topologies are employed. For example, although the negative feedback of the integrator configuration shown in Figure 2 is due to the signal inversion provided by the transistor Ql configured as a common emitter, negative feedback can be provided in other ways. By way of example, the transistor Ql configured as a common emitter could be eliminated, if the amplifier 921-11 wan inversion amplifier. In addition, if an amplifier having both non-inverting and reversing inputs wused, instead of the single-input amplifier 921-11, negative feedback could be provided by means of the filter section coupling, including the resistance Rl and the capacitors Cl and C2, to the investment input, and a transistor Ql configured as a common emitter could be eliminated. It is intended that these and other modifications be within the scope of the invention, defined by the following claims.

Claims (21)

1. An apparatus, comprising: a phase locked phase configuration (919) including a controlled oscillator (911) for generating a controlled oscillator signal, having a controlled frequency, in response to an oscillator control signal, source (921-5, 923) of a signal representing a reference frequency, an element (921-9) for the generation of an error signal representing the phase and frequency relationship between the signal of the controlled oscillator and the signal representing the reference frequency, and a cycle filter (927) for filtering said error signal, to generate the control signal of the oscillator; and an element (19) for the generation of a control signal indicating the mode, for controlling the mode of operation of the secured phase cycle configuration (919); the cycle filter (927) of the secured phase cycle configuration (919) including an amplifier (921-11) and a first filter section (Cl, C2, Rl) coupled in a negative feedback configuration, to form a integrator, a second filter section (C3, C4, R2, R4, R5) coupled in cascade with said integrator and a filter control section (Q2, Q3), coupled to the second filter section (C3, C4, R2) , R4, R5) for modifying the operation of the second filter section (C3, C4, R2, R, R5), in response to the control signal indicating the mode. The apparatus recited in claim 1, characterized in that: the filter control section (Q2, Q3) comprises a switching configuration, to selectively bypass the second filter section (C3, C4, R

2, R4, R5) ), in response to the control signal indicating the mode.

3. The apparatus recited in claim 2, characterized in that: the second filter section (C3, C4, R2, R4, R5) has a response characteristic of amplitude versus frequency, to increase the response time of the cycle configuration of phase assured (919), while maintaining the stability of the secured phase cycle configuration (919).

4. The apparatus recited in claim 3, characterized in that: the response characteristic of amplitude against frequency includes a pole, a first zero, and a second zero at successively higher frequencies.

The apparatus recited in claim 3, characterized in that: the response characteristic of amplitude against frequency includes a pole, a first zero, a second zero and a second pole at successively higher frequencies.

6. The apparatus recited in claim 3, characterized in that: the second filter section (C3, C4, R2, R4, R5) includes a first capacitor (C3) and a first resistor (R2) coupled in parallel, the parallel combination being coupled in a serial relationship with the signal path between the element (921-9) for the generation of the error signal, and the controlled oscillator (911); and a second resistor (R5) and a second capacitor (C4) coupled in series, the series combination being coupled in a bypass relationship with the signal path between the element (921-9) for the generation of the error signal , and the local oscillator (911).

The apparatus recited in claim 1, characterized in that: the secured phase cycle configuration (919) comprises an integrated circuit (921) of phase locked cycle, including the element (921-9) for the generation of the signal error, and the amplifier (921-11) of the cycle filter (927).

8. The apparatus recited in claim 7, characterized in that: the integrator and the second filter section (C3, C4, R2, R4, R5) of the cycle filter (927) are cascaded in the order mentioned, between the element (921-9) for the generation of the error signal, and the controlled oscillator (911).

9. An apparatus, comprising: a radio frequency input (901) for receiving a plurality of radiofrequency carrier signals; an assured phase cycle (919) including a local oscillator (911) for the generation of a local oscillator signal, which has a controlled frequency, in response to a tuning control signal, an element (921-3) for divide the frequency of the local oscillator signal, a source (921-5, 923) of a reference frequency signal, an element (921-9) for the generation of an error signal representing the phase and frequency differences frequency between the split frequency local oscillator signal and the reference frequency signal, and a cycle filter (927) for filtering said error signal, to generate the tuning control signal; a mixer (909) coupled to the radio frequency input (901) and the local oscillator (911), to produce an intermediate frequency signal; an element (19) for controlling the operation of the secured phase cycle (919) in a plurality of operating modes; said control element generating a control signal indicative of which of said modes the secured phase cycle (919) will operate; the cycle filter (927) of the phase locked cycle (919) including an amplifier (921-11) and a first filter section (Cl, C2, Rl) coupled in a negative feedback configuration, to form an integrator, a second filter section (C3, C4, R2, R4, R5) cascaded with said integrator and a filter control section (Q2, Q3), coupled to the second filter section (C3, C4, R2, R4, R5) for modifying the operation of the second filter section (C3, C4, R2, R4, R5), in response to the control signal indicating the mode.

The apparatus recited in claim 9, characterized in that: the filter control section (Q2, Q3) comprises a switching configuration, for selectively shifting the second filter section (C3, C4, R2, R4, R5) ), in response to the control signal indicating the mode.

11. The apparatus recited in claim 10, characterized in that: the second filter section (C3, C4, R2, R4, R5) has a response characteristic of amplitude versus frequency, to increase the response time of the assured phase cycle (919), while maintaining the stability of the assured phase cycle (919).

12. The apparatus recited in claim 11, characterized in that: the response characteristic of amplitude against frequency includes a pole, a first zero, and a second zero at successively higher frequencies.

The apparatus recited in claim 11, characterized in that: the response characteristic of amplitude against frequency includes a pole, a first zero, a second zero and a second pole at successively higher frequencies.

14. The apparatus recited in claim 11, characterized in that: the second filter section (C3, C4, R2, R4, R5) includes a first capacitor (C3) and a first resistor (R2) coupled in parallel, the parallel combination being coupled in a serial relationship with the signal path between the element (921-9) for the generation of the error signal, \ and the local oscillator (911); and a second resistor (R5) and a second capacitor (C4) coupled in series, the series combination being coupled in a bypass relationship with the signal path between the element (921-9) for the generation of the error signal , and the local oscillator (911).

The apparatus recited in claim 9, characterized in that: the phase-locked cycle (919) comprises an integrated circuit (921) for phase-locked phase control, including the element (921-3) for dividing the frequency of the local oscillator signal, said elements (921-9) for the generation of the error signal, and the amplifier (921-11) of the cycle filter (927).

16. The apparatus recited in claim 15, characterized in that: the integrator and the second filter section (C3, C4, R2, R4, R5) of the cycle filter (927) are cascaded in the order mentioned, between the element (921-9) for the generation of the error signal, and the local oscillator (911).

17. The apparatus recited in claim 9, characterized in that: the intermediate frequency filter (915) having a center frequency is provided for filtering said intermediate frequency signal; the intermediate frequency signal having a nominal frequency corresponding to the center frequency of the intermediate frequency filter (915); an element (11) is provided to determine the deviation of the frequency of the intermediate frequency signal from the nominal frequency; and the control element (19) controls the phase locked cycle (919) to (1) establish an initial frequency of the local oscillator during an acquisition mode, and (2) change the local oscillator frequency of said initial oscillator frequency local, to reduce a frequency deviation of the intermediate frequency signal of the nominal intermediate frequency, during a fine tuning mode; the filter control section (Q2, Q3) modifies the operation of the second filter section (C3, C4, R2, R4, R5) to increase the response time of the assured phase cycle (919), in response to the control signal indicating the mode, during fine tuning mode.

18. An apparatus, comprising: an assured phase cycle configuration (919) including a controlled oscillator (911) for generating a controlled oscillator signal, having a controlled frequency, in response to an oscillator control signal , a source (921-5, 923) of a signal representing a reference frequency, an element (921-9) for the generation of an error signal representing the phase and frequency relationship between the controlled oscillator signal and the signal representing the reference frequency, and a cycle filter (927) for filtering said error signal, to generate the control signal of the oscillator; and an element (19) for the generation of a control signal indicating the mode, for controlling the mode of operation of the secured phase cycle configuration (919); the secured phase cycle configuration (919) comprising an integrated circuit (921) of phase locked cycle, including the element (921-9) for the generation of the error signal and an amplifier (921-11); the cycle filter (927) of the secured phase cycle configuration (919) including an amplifier (921-11) of the integrated circuit (921) of the assured phase cycle, and a first filter section (Cl, C2, Rl) ) coupled in a negative feedback configuration, to form a miter, a second filter section (C3, C4, R2, R4, R5) coupled in cascade with said integrator, the integrator and the second filter section (C3, 04, R2, R4, R5) of the cycle filter (927) being cascaded in the order mentioned between the element (921-9) for the generation of the error signal, and the controlled oscillator (911), and a section of filter control (Q2, Q3), cycled to the second filter section (C3, C4, R2, R4, R5) for modifying the operation of the second filter section (C3, C4, R2, R4, R5), in response to the control signal indicating the mode.

19. The apparatus recited in claim 18, characterized in that: the filter control section (Q2, Q3) comprises a switching configuration, to selectively bypass the second filter section (C3, C4, R2, R4, R5) ), in response to the control signal indicating the mode. The apparatus recited in claim 19, characterized in that: the second filter section (C3, C4, R2, R4, R5) increases the response time of the secured phase cycle configuration (919), in response to the control signal indicating the mode. The apparatus recited in claim 20, characterized in that: the second filter section (C3, C4, R2, R4, R5) decreases the cycle gain of the secured phase cycle configuration (919), while maintaining stability of the assured phase cycle configuration (919).