MXPA96006746A - Tuner system for a satelliteigital receiver with tuning provisions f - Google Patents

Abstract

The present invention relates to an apparatus for processing digital signals modulated with each other of a plurality of radiofrequency carrier signals, comprising: a radio frequency input for receiving the modulated plurality of radiofrequency carrier signals, an assured phase control cycle of tuning, including a local oscillator to generate a signal from the local oscillator, a mixer coupled to the radio frequency input and the local oscillator to produce an intermediate frequency signal, modulated with digital signals corresponding to a radiofrequency signal, a frequency filter intermediate having a central frequency, said intermediate frequency signal having a nominal frequency corresponding to the center frequency of the intermediate frequency filter, a digital signal demodulator including a carrier recovery cycle element, for the demodulation of the intermediate frequency, to produce c) the digital signals carried by the intermediate frequency signal, and an element for controlling the operation of the phase locked cycle of tuning control, in response to at least one control signal generated by the carrier recovery cycle, which indicates the state of the carrier recovery cycle operation, said control element controlling the tuned control phase phase cycle to establish an initial local oscillator frequency, corresponding to the selected radio frequency signal, during an acquisition mode, starting when the signal of selected radio frequency is initially selected, and ending when the carrier recovery cycle is appropriately modulating said intermediate frequency signal, and changing the local oscillator frequency of the initial local oscillator frequency, to reduce a frequency offset of the intermediate frequency signal of the inter frequency nominal means, during a fine tuning mode, said control element further changing, selectively, the relative response times of the secured phase cycle of tuning control and of the carrier recovery cycle, during said fine tuning mode, for allowing said bearer recovery cycle to track frequency changes of the intermediate frequency signal, due to changes in the frequency of the local oscillator and, thereby, maintain the appropriate demodulation of the intermediate frequency signal

Description

TUNER SYSTEM FOR A DIGITAL SATELLITE RECEIVER WITH FINE TUNING PROVISIONS The invention relates to a tuner system for a satellite receiver, especially one capable of receiving and processing television signals transmitted in a digital form. Satellite television reception systems typically comprise an "outdoor unit" that includes a dish-shaped receiving antenna, and a "block" converter, and an "indoor unit" that includes a tuner and a processing section of signal. The block converter converts the entire range ("block") of radiofrequency signals of a relatively high frequency transmitted by a satellite, into a lower and more manageable range of frequencies. In a conventional satellite television transmission system, the television information is transmitted in analog form, and the radiofrequency signals transmitted by the satellite are in the C (e.g., 3.7 to 4.2 GHz) and Ku (e.g. 11.7 to 14.2 GHz). The radiofrequency signal received from the satellite by the antenna of the receiver system is converted by the block converter to the L-band (for example, 900 to 2000 Mhz). A radio frequency filter section of the indoor unit's tuner selects one of the radio frequency signals received from the block converter corresponding to the selected channel, and a section of the local mixer / oscillator of the tuner converts the selected radio frequency signal to a lower intermediate frequency (IF) range for filtering and demodulation. Typically, the intermediate frequency range has a nominal center frequency of 479.5 MHz. Analogue satellite television systems typically employ modulated frequency modulation, and a baseband video signal is easily obtained from the intermediate frequency signal of 479.5 MHz through a modulated frequency demodulator, after being filtered by an intermediate frequency filter. A relatively simple surface acoustic wave (SAW) device can provide adequate filtering in an analog satellite television receiver. In the newer satellite television systems, such as the DirecTvMR operated by • the Hughes Corporation of California, television information is transmitted digitally. The radiofrequency signals are transmitted by the satellite in the Ku-band, and are converted by the block converter to the L-band. The frequency range of the radiofrequency signals transmitted by the satellite is a little smaller (for example, between 12.2 and 12.7 GHz) than that for the analogue satellite television system, and the frequency range of the radio frequency signals produced by the block converter is, in accordance with the above, a little smaller (for example, between 950 and 1450 MHz). As with analog satellite reception systems, the radiofrequency signal corresponding to the selected channel must be reduced in frequency to an intermediate frequency range for filtering and demodulation. In a digital satellite receiver, in addition to normal intermediate frequency filtering to select the desired radio frequency signal, and reject unwanted radio frequency signals, it is desirable that the intermediate frequency filter perform what is known as "symbol configuration". "to reduce the errors of the decoding due to the" interference between symbols "caused by the limitations of the amplitude of the band. However, the symbol shaping function can not easily be performed at relatively high intermediate frequencies, such as at the intermediate frequency of 479.5 MHz used in an analog satellite television receiver, especially when the intermediate frequency filter comprises a wave device surface acoustics As a result, a relatively expensive separate digital filter is required. It is possible to employ a second conversion stage to convert a first intermediate frequency signal, of a relatively high frequency (e.g., 479.5 MHz), into a second intermediate frequency signal of a lower frequency (e.g., less than 100 MHz ), before intermediate frequency filtration. However, the second conversion stage adds an undesirable cost to the receiver. It is also desirable that the tuner system of the digital satellite television receiver can be constructed using components that are readily commercially available and, therefore, are relatively inexpensive. Specifically, in this aspect, it is desirable that the tuner system can be constructed using a commercially available integrated circuit (IC), incorporating an assured phase cycle (PLL), to control the frequency of the local oscillator. Since there are currently a large number of tuner phase locked phase integrated circuits for conventional television receivers that receive and process widely available terrestrial and conventional terrestrial broadcast signals, it is particularly desirable that the tuner system of a receiver Digital satellite television can be constructed using this phase locked integrated cycle of the conventional tuner. In the United States patent application identified above, a single conversion tuner for a digital satellite television receiver is described, which allows the use of a surface acoustic wave filter with symbol configuration capabilities, and the use of the type of phase-locked integrated circuit that is conventionally employed in terrestrial broadcasting and cable tuning systems. Basically, these two desirable attributes are realized by: (1) the selection of an intermediate center frequency of the order of the difference (eg, 140 NHz) between the highest frequency of the radio frequency signal received from the block converter (per example, 1450 MHz) and the highest frequency of the local oscillator (for example, in the order of 1300 MHz), available when a phase-locked integrated circuit of conventional terrestrial broadcasting and cable tuning is used; and (2) the use of a local oscillator signal with a frequency range that is lower than, rather than higher than, the frequency range of the received radio frequency • signals. A single conversion tuning system for a digital satellite television receiver of the type described works very satisfactorily under most operating conditions. However, the present inventors have discovered that, due to the characteristics of the block converter of the outdoor unit, the nature of the digital signal desorption process, and certain limitations of the integrated circuit of phase locked tuning control of terrestrial and cable broadcasting, the reproduced image may occasionally be interrupted. More specifically, the conversion stage of the block converter of the outdoor unit usually includes a local oscillator which does not stabilize against variations in temperature and age. The result is that the frequency of the signal of the local oscillator of the block converter changes, causing a corresponding change of the frequencies of the carrier signals of the radio frequency signals received by the tuner of the indoor unit. As a consequence, the frequency of the intermediate frequency signal produced by the tuner also changes its nominal value. If the frequency of the intermediate frequency signal changes too far from its nominal value, the digitized signals modulated in the intermediate frequency signal can not be demodulated properly, and the information they represent can not be reconstructed properly. To overcome this problem, the tuner local oscillator frequency of the indoor unit can be changed during a fine tuning operation, in order to compensate for changes in the frequency of the intermediate frequency signal. If the frequency of the local oscillator is changed in sufficiently small steps, the operation of the digital demodulator can track the changes and the digital signals will continue to be appropriately demodulated during the fine tuning operation. However, if the frequency of the local oscillator signal is changed in steps that are too large, the operation of the digital demodulator may not be able to follow the changes, and the digital signals may not be properly demodulated during the fine tuning operation. . Unfortunately, the integrated circuits of the phase locked cycle conventionally employed in terrestrial broadcasting and cable tuning systems typically allow changes of the local oscillator frequency in relatively large steps, for example, in the order of 62.5 KHz. In accordance with the foregoing, the use of a phase locked integrated phase control circuit of conventional terrestrial tuning in a digital satellite television receiver can result in the interruption of video and audio responses. In accordance with one aspect of the present invention, in a preferred embodiment of the present invention, wherein the tuner of a digital satellite television receiver comprises a single conversion stage, using an integrated phase-locked loop control circuit of conventional terrestrial tuning to control the frequency of the local oscillator, the speed at which the secured phase cycle configuration controls the frequency of the local oscillator signal during a fine tuning mode is reduced. This allows the digital data demodulator to more easily track the frequency changes of the intermediate frequency signal during the fine tuning mode, and thereby reduces the possibility of interruptions of the video and audio responses. These and other aspects of the present invention will be described in detail., with reference to the accompanying drawings. In the drawings: Figure 1 is a block diagram of a digital satellite television receiver that includes a tuner system that is constructed in accordance with an aspect of the invention. Figure 2 includes a block diagram of an integrated phase locked phase control tuning circuit, which is used in the tuner system shown in Figure 1, and a schematic diagram of a circuit implementation of a phase filter. assured phase cycle that can be controlled, which is constructed in accordance with another aspect of the invention. Figure 3 is a flow chart of a microprocessor control program for the tuner system shown in Figure 1, in accordance with another aspect of the invention. Figure 4 is a block diagram of a digital data demodulator for use in the satellite receiver shown in Figure 1 and useful in understanding a problem solved in accordance with an aspect of the invention. Figure 5 shows a graphical representation of the amplitude versus frequency response characteristics associated with the controllable phase-locked filter shown in Figure 2. In the different Figures, the same or similar reference designations are used to identify the same or similar elements. The invention will be described with reference to a digital satellite television system in which television information is transmitted in encoded and compressed form, in accordance with a predetermined digital compression standard, such as MPEG. MPEG is an international standard for the coded representation of moving image and audio information, developed by the Group of Experts in Moving Images. The DirecTvMR satellite television transmission system operated by the Hughes Corporation of California, is this digital satellite television transmission system. In the transmitter, the television information is digitized, compressed and organized into a series or stream of data packets corresponding to respective portions of video and audio of the television information. The digital data is modulated on a radiofrequency carrier signal, in what is known as QPSK modulation (Quaternary Phase Shift Keying), and the radio frequency signal is transmitted to a satellite in the Earth's orbit, from which it is transmitted back to Earth. In the quaternary phase shift keying modulation, the phases of two quadrature phase signals, I and Q, are controlled in response to the bits of the respective digital data streams. For example, the phase is set to 0 degrees (°) in response to a low logic level ("0"), and the phase is set to 180 ° in response to a high logic level ("1"). The modulated I and Q signals in phase change are combined, and the result is transmitted as a modulated radiofrequency carrier signal in Quaternary phase shift keying. In accordance with the above, each cycle of the modulated quaternary phase shift keying carrier indicates one of four logical states, ie, 00, 01, 10 and 11. A satellite typically includes a number of transponders, to receive and re-transmitting the respective modulated radiofrequency carriers. In a conventional terrestrial television system, each radiofrequency carrier or "channel" contains information only for one television program at a time. In accordance with the above, to see a program, you only need to select the corresponding radio frequency signal. In a digital satellite television system, each radiofrequency modulated carrier carries information for many programs simultaneously. Each program corresponds to groups of video and audio packages that are identified by a single header attached to the packages, which identifies the program. In accordance with the above, to see a program, you need to select both the corresponding radio frequency signal and the corresponding packages. In the digital satellite television receiver shown in Figure 1, radio frequency signals modulated with digital signals representing video and audio information that have been transmitted by a satellite (not shown), are received by an antenna in the form of dish 1. The received radiofrequency signals, of a relatively high frequency (for example, in the Ku frequency range between 12.2 and 12.7 GHz) are converted by a block converter 3, including a radio frequency amplifier 3-1, a mixer 3-3 and an oscillator 3-5, in radiofrequency signals of relatively lower frequency (for example, in the L band between 950 and 1450 MHz). The amplifier 3-1 is a "low noise" amplifier, and therefore, the block converter 3 is often referred to by the initials "LNB" by "low noise block converter". The antenna 1 and the low noise block converter 3 are included in a so-called "outdoor unit" 5 of the receiving system. The remaining portion of the receiver is included in a so-called "indoor unit" 7. The indoor unit 7 includes a tuning system 9 for selecting the radio frequency signal containing the packets for the desired program, from the plurality of radio frequency signals received from the outdoor unit 5, and for converting the selected radio frequency signal to a corresponding lower intermediate frequency (IF) signal. The present invention relates to the construction of the tuning system 9 and will be described later in detail. The remaining portion of the indoor unit 7 descrambles, decodes, and decompresses the digital information carried in the form of a quaternary phase shift keying modulation by the intermediate frequency signal, to produce corresponding digital video and audio sample streams. to the desired program, and, after that, converts the digital sample streams into respective analog video and audio signals, suitable for reproduction or recording. More specifically, a quaternary phase shift keying demodulator 11 demodulates the intermediate frequency signal to produce two pulse signals IP and P containing respective data bit streams corresponding to the data represented by the I and Q signals modulated in phase change generated in the transmitter. A decoder 13 organizes the bits of the IP and QP signals into blocks of data, corrects the transmission errors in the data blocks based on the error codes that have been embedded in the data transmitted in the transmitter, and reproduces the packets of data. MPEG audio and video transmitted. The video and audio packets are directed by a transport unit 15 to respective video and audio sections of a data processing unit 17, where they are decompressed and converted into respective analog signals. A microprocessor 19 controls the operation of different sections of the indoor unit 7. However, only the control signals generated and received by the microprocessor 19, with which the invention relates directly, are indicated in FIG. The digital satellite television receiver described so far is similar to the digital satellite system RCAMR type DSSMR television receiver commercially available from Thomson Consumer Electronics, Inc., of Indianapolis, Indiana. As stated above, the present invention relates to the construction of the tuning system 9. The tuning system 9 receives the radio frequency signal provided by the low noise block converter 3 at an input 901. The radio frequency input signals they are filtered by a 903 broadband filter, amplified by a radio frequency amplifier 905 and filtered by a tunable bandpass filter 907. The tunable bandpass filter (BPF) 907 selects the desired radio frequency signal and rejects unwanted radio frequency signals. The resulting radiofrequency signal is coupled to a first input of a mixer 909. A local oscillator signal produced by a local oscillator (LO) 911 is coupled to a second input of the mixer 909. The output of the mixer 909 is amplified by an amplifier 913, and coupled to the input of an intermediate frequency filter 915 comprising a surface acoustic wave device. The output of the intermediate frequency filter 915 is coupled to the output 917 of the tuning system 9. The frequency of the local oscillator 911 is controlled by an assured phase cycle (PLL) configuration 919 comprising an integrated circuit (IC) 921 of assured phase cycle, an external frequency reference crystal 923, and an external filter network 925. The frequency of the local oscillator signal is controlled by the secured phase cycle 919, in accordance with the data generated by the microprocessor 19 Fig. 2 shows details of the secured phase cycle 919. As shown in Fig. 2, the phase locked phase integrated circuit 921 includes a "prescalar" frequency separator 921-1 to divide the frequency of the signal of the local oscillator, followed by a programmable frequency separator (- ^ - N) 921-3. The integrated phase-locked circuit 921 also includes an amplifier 921-5, which in combination with the outer glass 923, comprises a reference frequency oscillator. The output of the reference frequency oscillator is coupled to the input of a reference frequency separator (-s-R) 921-7. The output signals of the programmable separator (^ -N) 921-3 and the reference separator (-MR) 921-7 are coupled to respective inputs of a phase detector 921-9. The output signal of phase detector 921-9 is an error signal representing the frequency and phase differences between the split frequency version of the local oscillator signal produced at the output of the programmable separator (- ^) 921- 3 and the reference signal produced at the output of the reference spacer (-jR) 921-7. The error signal contains pulses that have either a relatively positive polarity or a relatively negative polarity, depending on the phase direction and the frequency differences between the input signals of the 921-9 phase detector, and a variable duration that depends on the magnitude of phase and frequency differences. The error signal is coupled to an amplifier 921-11, which together with the external filter network 925, comprises a cycle filter 927, for filtering the error signal, to produce a tuning control voltage for the local oscillator 911 The tuning control voltage also controls the tuneable bandpass filter 907. The cycle filter 927 is constructed in accordance with one aspect of the invention and will be described later in detail. In operation, the frequency of the local oscillator signal is controlled in response to the tuning voltage, until the frequency and phase of the split-frequency version of the local oscillator signal produced at the output of the programmable separator (- ^ N ) 921-3, are substantially equal to the frequency and phase of the reference signal produced at the output of the reference spacer (- = - R) 921-7. At that point, the assured phase cycle is "secured", and the frequency of the local oscillator signal is proportionally related to the frequency of the reference frequency signal produced by the reference frequency separator (- ^ R) 921 -7 by the programmable division factor (N) of the programmable separator (^ -N) 921-3. The programmable division factor N is controlled in response to data generated by the microprocessor 19, in order to control the frequency of the local oscillator. For reasons of cost, it is desirable that the tuning system 9 has the following three characteristics: (1) comprising only a single conversion stage before the intermediate frequency filter stage; (2) that provides an intermediate frequency signal with a frequency low enough to allow a surface acoustic wave device to be used for so-called "digital symbol configuration" as well as normal intermediate frequency filtering; and (3) which is capable of being constructed using an integrated phase locked phase control tuning circuit, which is conventionally used for broadcast and cable receivers. Basically, these goals are achieved by: (1) selecting an intermediate frequency center frequency that is in the order of the difference (eg, 140 MHz) between the highest frequency of the radio frequency signal received from the frequency converter. blocks (for example, 1450 MHz) and the highest frequency of the local oscillator (for example, in the order of 1300 MHz), available through the use of a phase-locked integrated circuit of conventional terrestrial broadcasting control and tuning by cable; and (2) the use of a local oscillator signal with a frequency range that is lower than, rather than higher than, the frequency range of the received radio frequency signals. In the exemplary tuning system, the center frequency of the intermediate frequency signal is 140 MHz. However, other intermediate frequencies are possible, using the guidelines stated above. A relatively low intermediate frequency center frequency, for example, in the order of 140 MHz, allows a single conversion tuner to be used rather than a more expensive double conversion tuner, before the intermediate frequency filter section. This also allows a surface acoustic wave device, which provides so-called "digital symbol configuration", as well as a normal intermediate frequency filtering to be used. In a digital transmission system, what is known as "digital symbol configuration" is performed in the transmitter to reduce inter-symbol interference, due to the limitations of the transmission bandwidth. It is also desirable to perform the digital symbol configuration on the receiver, to complement the digital symbol configuration performed on the transmitter. In addition, it is desirable that the intermediate frequency filter allows the symbol configuration, as well as the normal intermediate frequency filtering function, such that a separate digital filter is not required. By way of example, what is known in the digital filter technique as a "high root cosine" response is suitable for the digital symbol configuration. The intermediate frequency 915 surface acoustic wave filter has such a response. In Figure 1ee it shows the amplitude versus frequency characteristic of the surface acoustic wave filter 915. This has a center frequency of 140 MHz, and a relatively flat pass band of approximately 24 MHz, which corre- sponds to the bandwidth of the bands. received radio frequency signals. In the patent application of the United States of America with serial number 08 / 467,095, entitled "SAW Filter for a Digital Satellite Receiver Tuner", filed on June 6, 1995, for KJ Richter, MA Pugel and JS Stewart, and which is assigned to the same assignee of the present application, describes in detail a surface acoustic wave filter with these characteristics, which utilizes a lithium tantalate substrate. In addition, with an intermediate frequency center frequency of 140 MHz, and a frequency range of radio frequency input between 950 and 1450 MHz, the frequency range of the local oscillator is between 810 and 1310 MHz. The frequency range of 810- 1310 MHz of the local oscillator signal, allows the phase-locked tuning control integrated circuits, which are conventionally and widely used for broadcasting and cable receivers, to be used, and which are therefore relatively inexpensive, rather than an integrated phase locked phase control tuning circuit, specially designed for satellite receivers. Such an integrated phase-locked radio and cable phase tuning control circuit is the T? A5515T, commercially available with Philips Semiconductors of the Netherlands and others. The maximum frequency of the local oscillator available using the TSA5515T and similar integrated circuits is in the order of 1300 MHz, which is adequate. The portion of the tuning system 9 described so far is the subject of the abovementioned United States patent application, serial number 08 / 467,097, entitled "Digital Satellite Receiver Tuner", filed on 6 June 1995, for MA Pugel and KJ Richter, and which is assigned to the same assignee as the present application. The present invention specifically relates to provisions for controlling local oscillation 911 during the acquisition and fine tuning operation, which will now be described. The carriers of the radiofrequency signals transmitted by the satellite and received by the antenna 1, have very stable frequencies that remain in "nominal" values. Therefore, as long as the frequency of the oscillator 3-5 of the low noise block converter 3 is stable and remains at its nominal value, the frequencies of the carriers of the radio frequency signals received by the tuning system 9 of the unit for interiors 7, they will be at their nominal values. Unfortunately, the frequency of oscillator 3-5 can change with time and temperature. The frequency defects of the oscillator 3-5, with respect to the nominal frequency, cause corresponding phase shifts of the carrier frequencies of the radio frequency signals received by the tuning system 9. To compensate for these frequency shifts, the frequency is changed of the local oscillator 911 of the tuning system 9, under the control of the microprocessor 19, in response to information of the status of the frequency received from the quaternary phase shift keying demodulator, during two search operations. In Figure 3 the flow diagram of the microprocessor control program 19 for the tuning system 9 is shown, including the search operations. A first search may occur during an acquisition mode, after a new program is initially selected. When a new program is selected, the microprocessor 19 causes the local oscillator frequency to be set to a nominal local oscillator frequency corresponding to the nominal radio frequency of the transponder for the new program. After this, the state of a LOCK signal generated by the quaternary phase shift keying demodulator 11 is monitored. The signal LOCK indicates whether the quaternary phase change keying demodulator 11 is operating correctly or not to demodulate the digital data carried by the intermediate frequency signal. For example, the signal LOCK has a low logic level when the quaternary phase shift keying demodulator 11 is not properly demodulating the digital data, and the signal LOCK has a high logic level when the quaternary phase change keying demodulator 11 is properly demodulating the digital data. If the LOCK signal has the logic level low after the local oscillator frequency has been set to the nominal local oscillator frequency, for the selected transponder, the frequency of the local oscillator 911 is changed to a range around the oscillator frequency nominal local, until the LOCK signal has the high logic level. The generation of the signal LOCK indicates the start of a stable state operation mode of the tuning system 9.

During the steady state mode, a FREQUENCY signal generated by the quaternary phase shift keying demodulator 11 is monitored to determine whether or not the carrier frequency of the intermediate frequency signal is centered within the filter pass band. of intermediate frequency surface acoustic wave 915, that is, if the carrier frequency of the intermediate frequency signal is at the nominal intermediate frequency center frequency, for example, 140 MHz in the present embodiment. The performance of the quaternary phase shift keying demodulator 11 will be degraded, and data errors will occur, if the frequency of the intermediate frequency carrier falls outside a predetermined range around the nominal center frequency. If the FREQUENCY signal indicates that a predefined frequency offset has not been exceeded, the frequency of the local oscillator 911 is changed to the left of the initial value set during the acquisition mode. However, if the FREQUENCY signal indicates that a predetermined frequency derailment has been exceeded, the frequency of the local oscillator 911 is changed during a second "fine tuning" search operation until the situation is corrected. The present invention is directed to remediate a problem that could occur during the fine tuning mode, as will now be explained.

It has been found that the tuning system 9, which comprises the integrated phase-locked circuit circuit 921 of terrestrial and cable broadcasting, works very satisfactorily under most circumstances. However, the secured phase loop integrated circuit 921 of terrestrial tuning has certain limitations that could result in temporary loss of video and / or audio information. The size of the smallest frequency changes of a local oscillator controlled by an assigned phase cycle is related to the value of the smallest possible increments of the programmable division factor (N) of the programmable separator (- ^ N), and with the frequency of the reference signal of the phase-locked integrated circuit 921. Phase-locked earth-phase integrated circuits, such as the TSA5515T, are capable of changing the signal frequency of the local oscillator only in steps of relatively large increments, for example, of 62.5 KHz. As a result, during the two search operations, the frequency of the carrier of the intermediate frequency signal will change in the same relatively large steps. Unfortunately, the quaternary phase shift keying demodulator 11 may not be able to track those relatively large frequency steps, possibly resulting in an interruption of the appropriate demodulation operation, and a loss of video and audio data. If a first search operation occurs during the acquisition mode, the loss of data is not noticeable, because a viewer will expect the acquisition process for a new program to take some time. However, if the second fine tuning operation or operation becomes necessary during steady state mode, the video and / or audio response of the program you are watching at that moment may be interrupted. In the invention, the possibility of such interruption is reduced, by reducing the "turning rate" of the set-up cycle configuration 919, that is, the rate at which the tuning voltage is allowed to change the amplitude, during the fine tuning operation More specifically, the response time of the cycle filter 927 increases in response to a FINE TUNING control signal generated by the microprocessor 19. The problem to which this solution is directed will now be described in more detail., with respect to Figure 4, which shows a block diagram of an implementation of the quaternary phase shift keying demodulator 11. As shown in Figure 4, the intermediate frequency signal produced by the surface acoustic wave filter 915 of intermediate frequency is coupled to respective first inputs of the mixers 11011 and 1101Q. The letters "I" and "Q" mean "in phase" and "square". The output signal of a relatively stable frequency oscillator 1103 is directly coupled to the mixer 11011, and indirectly coupled to the mixer 1101Q by a phase change network 1105 of 90 degrees (90 °). The mixer 11011 produces an "in phase", "near" (base frequency) band (IA) version (much lower frequency) of the intermediate frequency signal, while the 1101Q mixer produces a "quadrature" baseband version (QA). , near, the intermediate frequency signal, which changes 90 degrees with respect to the signal "in phase" (IA). The letter "A" means "analog." Signals IA and QA are coupled to respective analog-to-digital converters (ADCs) 11071 and 1107Q. Analog-to-digital converters 11071 and 1107Q also receive a clock signal from a "timing recovery cycle" 1109, and produce respective series of digital samples ID and QD. The letter "D" means "digital." The frequency and phase of the clock signal determine the frequency of the digital samples, and also the phase of the digital samples of the digital signals ID and QD relative to the analog signals IA and QA. The timing recovery cycle 1109 includes a controlled oscillator (not shown), from which the clock signal for analog-to-digital converters 11071 and 1107Q is derived. The controlled oscillator is controlled by a digital secured phase cycle (not shown) in such a way that the digital samples are synchronized with corresponding amplitude levels of the analog signals IA and Qa, that is, the maximum and minimum sample values correspond with the maximum and minimum amplitudes of the analog signals. In other words, the timing recovery cycle 1109 synchronizes the sampling operation of the analog-to-digital converters 11071 and 1107Q with the intermediate frequency signal. The ID and QD signals are also coupled to a "bearer recovery cycle" 1111. The bearer recovery cycle 1111 demodulates the phase changes of the analog outputs IA and QA representing the digital sample signals ID and QD, in order to form respective IP and QP impule signals. The letter "P" means "impulse". Each of the IP and QP impulse templates contains a series of impuleoe corresponding to data bits. The data bits have either a low logic level ("0") or a high logic level ("1") corresponding to the phase changes of 0o and 180 °, respectively, of the I and Q signals of the radio frequency transmitter of transmitted Quaternary phase change. The IP signal components and IQ are coupled to the decoder 13, where the different data bits are formatted in MPEG data packets.

The carrier recovery cycle 1111 includes a digital phase locked cycle (PLL) comprising a controlled oscillator 1111-1, a phase detector 1111-3 and a cycle filter 1111-5. The phase detector 1111-3 generates a phase error signal in response to the signals ID and QD, and to the output signal of the controlled oscillator 1111-1. The nominal frequency and the nominal phase of the output signal of the controlled oscillator 1111-1 corresponds to the nominal frequency and the nominal phase of the intermediate frequency signal and, therefore, to the nominal frequency and the phases of the analog signals IA and QA, and with the corresponding digital sample signals ID and QD. In operation, the phase changes of the signals represented by the signals ID and QD can be determined reliably from the phase error signal, if the phase and the frequency of the intermediate frequency signal are correct. However, if the phase and frequency of AI and QA are incorrect, the detected phase changes will not be at 0o or 180o, but instead will be changed from these values. In essence, a phase error causes an "inclination" of the "position" of the two-bit demodulated data, with respect to the ideal position of the two-bit data in a so-called "constellation" of data. A frequency error, for example, due to a frequency offset derived from the low noise block converter of the selected radio frequency signal, causes over time a so-called "rotation" of the position of the two-bit demodulated data of the click-through signal for change of quaternary fae. The direction of rotation depends on whether the frequency offset is positive or negative. As shown in Figure 4, the data constellation for the quaternary phase shift keying modulation has four points corresponding to four possible logical combinations (00, 01, 10, and 11) of the two logical levels possibly reepective, represented by the two possible phase change values of the signals I and Q. The phase detector 1111-3 measures the position of the demodulated data, in relation to the ideal position in the data constellation. To correct the data rotation and tilt, the frequency, and hence the phase, of the output signal of the controlled oscillator 1111-1 is changed in response to the output signal from the phase detector 1111-3, until the rotation stops and the inclination is eliminated. At this point, the demodulated data is reliable and the cycle is said to be "insured". A high-level logical SECURED signal is generated, to indicate that the data is being demodulated reliably and that it can be decoded. The INSIGNED signal is generated by examining the derivative of the phase error signal, to determine when the change in the fae error falls below a previously determined limit.

As noted above, during the acquisition mode, the microprocessor 19 overrides the INSIGNED signal, and the microprocessor 19 adjusts the frequency of the local oscillator 911, until the INSURED signal has a high logic level. Within the limits, the carrier recovery cycle 1111 can demodulate the quaternary phase shift keying data, even when the frequency of the intermediate frequency signal, and therefore the frequency of the signals IA and Qa is incorrect or eeté outdated However, if the frequency offset is too large, a portion of the frequency spectrum of the intermediate frequency signal will fall outside the passband of the surface acoustic wave filter 915, due to the change of the intermediate frequency signal with relation to the center frequency of the surface acoustic wave filter 915. This will cause a degradation of the signal to a noise ratio of the receiver. Accordingly, as stated above, the microprocessor 19 monitors a signal FREQUENCY generated by the carrier recovery cycle 1111, to indicate the frequency offset of the intermediate frequency signal. If the frequency offset exceeds a previously determined limit, the microprocessor 19 causes the frequency of the local oscillator to adjust to reduce the frequency offset during the fine tuning mode. The FREQUENCY signal is generated by integrating the phase error detected by the phase detector 1111-3. As stated above, the frequency of the local oscillator signal, and hence the frequency of the intermediate frequency signal, changes in relatively large frequency steps, for example 62.5 KHz, and may not be possible for the scrambler click to change quaternary fae 11 to stop such relatively large frequency steps. As a result, an interruption of the appropriate demodulation operation, and a loss of video and audio data may occur. The ability of the quaternary phase shift keying demodulator 11 to track relatively large frequency changes is a function of the cycle bandwidth of the carrier recovery cycle 1111, and more specifically the response of the cycle 1111 filter. 5. The cycle bandwidth of the carrier recovery cycle 1111 should not be made arbitrarily large, in order to decrease its re-paging time, because a bandwidth whose increased cycle would degrade the signal to the receiver's noise characteristics and, therefore, both, the ability of the receiver to receive low level signals. It is also not desirable to decrease the cycle bandwidth of the secured phase cycle 919 in order to decrease its response time, because a decreased response time would result in excessively long acquisition times, when selecting new transponder frequencies. As stated above, to reduce the possibility of interrupting the demodulation process during the fine tuning operation, the response time of the secured phase cycle 919 of tuning control is increased selectively to reduce the index to which it is allowed changing the tuning voltage, and therefore the frequency of the local oscillator 911, during the fine tuning operation. Now you will describe this solution in detail. Referring again to Figure 2, and more particularly to the portion of the circuit marked "CYLINDER FILTER 927", as described above, the cycle filter 927 includes the amplifier 921-11 inside the phase-locked integrated circuit 921 , and an external filter net 925. The external filter net 925 includes a first filter stage 925-1 and a second filter stage 925-2 controllable, which are coupled in cascade 'between the internal amplifier 921-11 and the local oscillator 911. The first filter stage 925-1 and the amplifier 921-11 of the phase locked phase integrated circuit 921 form an integrator. More specifically, the first filter stage 925-1 includes a bipolar transistor Ql configured as a common emitter amplifier. The base of the transistor Ql is connected to the output of the amplifier 921-11 via a terminal of the integrated circuit. The emitter of the transmitter Ql is connected to ground signal. A load resistor R6 is connected between the collector of the transistor Ql and a source of a supply voltage (+ VCC). A section of the filter, which includes a return R1 and the capacitors Cl and C2, is connected in a negative feedback path between the collector of the transistor Q1 and the input of the amplifier 921-11 via a terminal of the integrated circuit to complete the integrator. The feedback is negative due to the signal inversion provided by the trainer Ql configured as a common emitter. The use of an integrator comprising the 921-11 amplifier and the first filter stage 925-1, connected in a negative feedback configuration, makes phase cycle 919 a guaranteed phase II type cycle. A type II phase-locked cycle minimizes both phase and frequency differences between the split-frequency version of the local oscillator signal, developed at the output of the programmable frequency separator (N) 921-3, and the frequency signal of reference developed at the output of the reference frequency separator (- ^ - R) 921-7, and therefore stabilizes both the fae and the frequency of the local oscillator 911. The second filter stage 925-2 includes a section of two-pole, two-zero filter, including resistors R2, R4 and R5, and capacitors C3 and C4, and an electronically controlled switching section, comprising the field effect transistor Q2 and the resistor R3 of relatively low value . The conduction state of the transistor Q2 is controlled in response to the FINE TUNING signal generated by the microprocessor 19. The second filter section 925-2 is selectively controlled to either effectively derive the doe-poles filter section, of double zero (R2, R4, R5, C3 and C4), or to include the filter section of doe poles, double zero in the path between the first filter section 925-1 and the local oscillator 911. M ee specifically, when the tuning system 9 is not in the fine tuning operation mode, the FINE TUNING signal has a low logic level, and the conduction channel of the transistor Q2 is caused to be in the low impedance state, or "on" . As a result, the resistances of the elements R2, R4 and R5, and the capacitor C3 and C4 of the second filter section 925-2 are effectively derived due to the traineist Q2"on" and the resistor R3 of relatively low value. In the fine tuning mode, the FINE TUNING signal has a high logic level, and the conduction channel of the transistor Q2 is caused to be in the high impedance state, or "off". As a result, the resistors R2, R4 and R5 and the capacitors C3 and C4 of the second filter section 925-2 are connected in the path between the first filter section 925-1 and the local oscillator 911. The amplitude Bode against the Frequency characteristic for the double zero filter section (R2, R4, R5, C3 and C4) of the second filter stage 925-2, shown by itself in the Figure as feature # 1. Amplitude levels they are indicated in decibels (dB) and the frequency axis is logarithmic. It is seen that feature # 1 contains two "poles" Pl and P2, and two "zeros" Zl and Z2, which occur in the order: pole Pl, zero Zl, zero Z2, and pole P2, at higher and higher frequencies. The pole Pl ee owes to the resistance R2 and the capacitor C4; the zero Zl ee owes to the resistor R2 and the capacitor C3; zero Z2 is due to resistance R5 and capacitor C4; and the pole P2 is due to the resistance R5 and the capacitor C3. Figure 5 also shows two Bode amplitudes against frequency characteristics of the overall cycle response of phase locked cycle 919. Feature # 2 is the cycle response when tuning system 9 is not in fine tuning mode , and the cycle filter 927 includes only the first filter stage 925-1, that is, the two-pole, double-zero filter section (R2, R4, R5, C3 and C4) of the second stage of the filter is derived. filter 925-2. Feature # 3 is the response of the cycle when the tuning system 9 is in the fine tuning mode, and the cycle filter 929 includes the first filter stage 925-1 and the double-zero filter section, double zero (R2, R4, R5, C3 and C4) of the second filter stage 925-2 coupled in cascade. Feature # 3 has not been drawn to scale in terms of amplitude, with respect to characteristic # 1 and # 2, to avoid overlapping features. Recalling that the overall amplitude versus the two-stage frequency characteristic connected in cascade results in the multiplicative product of the two individual characteristics, or the adve product when the amplitudes are expressed in decibel levels (dB), characteristic # 3 is the result of the adve combination of features # 1 and # 3. A pole of feature # 1 causes an increase in the slope (negative direction) of feature # 3. A zero of feature # 1 causes a decrease in the slope (negative direction) of feature # 3. The pole Pl reduces the overall cycle gain and, therefore, the overall cycle bandwidth. Without zeros Zl and Z2, the slope of feature # 3 would cross the amplitude level of 0 dB, with an inclination of more than 20 dB per decade of frequency, causing the cycle to be unstable and, therefore, subject to oscillations. Pole P2 occurs incidentally due to the topology of the circuit that requires resistance R5 and capacitor C3. However, the pole P2 is convenient because it reduces the cycle gain (i.e., increases the attenuation) for out-of-band signals, such as the reference frequency signal of the phase-locked cycle 919. In Figure 5 it is seen that when the tuning system 9 is not in the fine tuning mode (feature # 2), the cycle band amplitude is relatively large and, therefore, the response of the secured phase cycle 919 is relatively fast. In contrast, when the tuning system 9 is in the fine tuning mode (feature # 3), the cycle band amplitude is relatively small and, therefore, the response of the phase locked cycle 919 is relatively slow. In the implementation of the second filter stage 925-2 shown in Figure 2, it is desirable for the resistor R4 to isolate the output of the first filter stage 925-1 (in the collector of the transistor Ql) from the capacitor C4, for the following reasons. The capacitor C4 has a relatively large capacitance. Without resistor R4 (that is, if resistor R4 were replaced with a direct connection), the capacitor C4 and resistor R5 series connection would be connected directly bypass to the output of the first filter stage 925-1, when the tuning system is in the acquisition mode, and the switching transistor is "on". This would tend to undesirably increase the acquisition time. However, the resistor R4 of relatively high value isolates the output of the first filter stage 925-1 from the capacitor C4 and, by the same, does not allow the capacitor C4 to significantly increase the acquisition time. further, with respect to capacitor C4 valued relatively high, it may be desirable to provide a previously determined time delay, before allowing the fine tuning operation to start after the acquisition mode, to allow the capacitor C4 to charge (or discharge) the voltage of tuning generated during the acquisition operation. The microprocessor 19 can provide that delay under the control program, as indicated in the flow chart shown in Figure 3. As shown in Figure 2, it may be desirable to add a dynamic "acceleration" circuit 925- 3 for the first filter stage 925-1, to change the response time of the secured phase cycle 919, in order to accelerate the acquisition operation. Acceleration circuit 925-3 includes bipolar traneistores of opposite conductivity type push-pull Q3 and Q4, and a resistor R7. The common connected bases of transistors Q3 and Q4 are connected to one side of the capacitor Cl, and the emitters connected in common are connected, via resistor R7, to the other side of capacitor Cl. The collectors of transistors Q3 and Q4 they are connected to respective sources of oppositely polarized supply voltages + VCC and -VCC. The following table shows the exemplary component values for the external filter network 925. Component Value resistance Rl 24 K (kiloohms) capacitor Cl 4700 pf (picofaradioe) capacitor C2 0.1 μf (microfaradioe) resistance R6 2 K resistance R7 10 K resistance R2 1 M (megaohmioe) capacitor C3 0.27 μf resistance R3 2 K resistance R4 20 K resistance R5 470 ohms capacitor C5 220 μf In operation, when a large frequency change occurs, such as when a new transponder frequency is selected, ee generates a large error signal, and develops a large corresponding voltage across the resistor Rl. Depending on the polarity of the change, one of the transistors Q3 or Q4 will "turn on" and "charge" or "dissipate" current. This results in an effective increase in cycle gain (ie, feature # 2 is changed up), and a consequent decrease in acquisition time. As the phase locked cycle 919 approaches the desired frequency and the error signal decreases, the "on" transistor goes "off". In the patent application of the United States of America with serial number 08 / 504,849, entitled "Rapid Action Control System", filed on July 20, 1995, for David M. Badger, and assigned to the same transferee of the present application, an acceleration circuit is described in detail, similar to the acceleration circuit 925-3, as well as other acceleration circuits. Although the present invention has been described by way of example, in terms of a specific modality for a particular application, those skilled in the art will appreciate that modifications can be made to suit other applications. For example, the invention is not limited to being used in a tuner system for a satellite receiver, and can be employed as long as the size of the local oscillator pitch is relatively large with respect to the tracking capability of the carrier recovery cycle. In addition, although the present invention has been described in terms of a receiver, in which the response time of the secured phase cycle of tuning control is increased, during the fine tuning mode, to selectively change the times of relative response of the secured phase cycle of tuning control, and the carrier recovery cycle, during fine tuning mode, to allow the bearer recovery cycle to track frequency changes of the local oscillator and, thereby, maintain a demodulation of the intermediate frequency signal, it is possible to decrease the response time of the carrier recovery cycle, during fine tuning mode. However, it is considered preferable to increase the response time of the secured phase cycle of tuning control, because, as stated above, the decrease in the response time of the bearer recovery cycle may cause a degradation of the video and audio responses , due to a decrease in the signal to the operation of 'noise of the demodulator. In addition, although the invention has been described with respect to a system employing a carrier recovery cycle, for the demodulation of a modulated quaternary phase shift keying carrier, the invention can also be applied to systems employing carrier recovery cycles. , for demodulation bearers modulated with digital data in different ways, such as QAM (quadrature amplitude modulation). It is intended that these and other modifications be within the scope of the present invention, defined by the following claims.

Claims (20)

1. An apparatus for processing digital signals modulated with each other, of a plurality of radiofrequency carrier signals, comprising: a radiofrequency input (901) for receiving the modulated plurality of radio frequency carrier signals; an assured phase cycle (919) of tuning control, including a local oscillator (911) for generating a local oscillator signal; a mixer (909) coupled to the radio frequency input (901) and the local oscillator (911) to produce an intermediate frequency signal, modulated with digital signals corresponding to a radiofrequency signal selected from the plurality of radiofrequency signals; An intermediate frequency filter (913) having a center frequency; said intermediate frequency signal having a nominal frequency corresponding to the center frequency of the inter-frequency frequency filter (913); a digital signal demodulator (11) including a carrier recovery cycle element (1111), for the demodulation of the intermediate frequency, to produce the digital signals carried by the intermediate frequency signal; and an element (19) for controlling the operation of the secured phase cycle (919) of tuning control, in response to at least one control signal generated by the bearer recovery cycle (1111), which indicates the operating state of the carrier recovery cycle (lili); said control element (19) controlling the secured phase cycle (919) of tuning control to (1) establish an initial local oscillator frequency, corresponding to the selected radio frequency signal, during an acquisition mode, starting when the signal selected radio frequency is initially selected, and ending when the carrier recovery cycle (1111) is appropriately desinging said intermediate frequency signal, and (2) changing the local oscillator frequency of the initial local oscillator frequency, to reduce a phase shift frequency of the intermediate frequency signal of the nominal intermediate frequency, during a fine tuning mode; said control element (19) further changing, selectively, the relativ ee times of the secured phase cycle (919) of the tuning control and of the carrier recovery cycle (1111), during said fine tuning mode, to allow that said carrier recovery cycle (1111) tracks frequency changes of the intermediate frequency signal, due to changes in the local oscillator frequency and, thereby, maintaining the appropriate demodulation of the intermediate frequency signal.

2. The apparatus recited in claim 1, characterized in that: the frequency of the local oscillator (911) is changed in steps long enough during the fine tuning mode, to temporarily interrupt the appropriate demodulation of the intermediate frequency signal, by the digital demodulator (11) due to the inability of the carrier recovery cycle (1111) to track large step changes of the frequency of said local oscillator (911) fast enough.

3. The apparatus recited in claim 1, characterized in that: the radio frequency signals have frequencies that are greater than the frequency range that is used for conventional terrestrial and cable television broadcasting; and the element of the set-up cycle (919) of the tuning control comprises an integrated circuit (921) for controlled phase-locked tuning control, which is normally employed in a terrestrial broadcasting and cable television receiver.

4. The apparatus recited in claim 3, characterized in that: the radio frequency input (901) is adapted to receive the radio frequency signal from a block converter (3), which is capable of offsetting the frequencies of the radio frequency carriers. radiofrequency of the respective nominal frequencies.

5. The apparatus recited in claim 1, characterized in that: radio frequency signals are modulated by quaternary phase shift keying with digital signals; and the demodulator (11) is a quaternary phase shift keying demodulator. The apparatus recited in claim 1, characterized in that: the control element (19) increases the response time of the secured phase cycle (919) of tuning control during the fine tuning mode. The apparatus recited in claim 6, characterized in that: the phase locked cycle (919) of the tuning control includes a controllable filter (925) which determines the response time of the secured phase cycle (919) of control tuning; and the control element (19) controls said filter (925) to increase the response time of the secured phase cycle (919) of tuning control, during the fine tuning mode. The apparatus recited in claim 7, characterized in that: the filter (925) includes first (925-1) and second (925-2) filter stages; and the control element (19) controls the second filter step (925-2) to increase the response time of the locked phase cycle element (919) of the tuning control, during the fine tuning mode. The apparatus recited in claim 8, characterized in that: the local oscillator (911) is responsive to a tuning control signal, which determines its oscillation frequency; the phase locked cycle (919) of tuning control includes an element (921-9) for comparing the oscillation frequency of the local oscillator (911) with a reference value, to generate an error signal; the filter (925) is coupled to the comparison element (921-9) for filtering the error signal, to produce the tuning control signal for the local oscillator (911); the first (925-1) and second (925-2) filter stages are cascaded between the comparison element (921-9) and the local oscillator (911); and the second filter stage (925-2) includes a filter section (C3, C4, R2, R4, R5) and a switching section (Q2, Q3), to selectively bypass the filter section (C3, C4, R2, R4, R5) of the second filter stage (925-2), under control of the control element. The apparatus recited in claim 9, characterized in that: the comparison element (921-9) is coupled to the filter element (925), by means of an amplifier (921-11); and the first filter stage (925-1) includes a filter section (Cl, C2, Rl), which is coupled in a negative feedback configuration with the amplifier (921-11). 11. An apparatus for processing digital processing signals modulated with each other, of a plurality of radio frequency carrier signals, comprising: a radio frequency input (901) for receiving the modulated plurality of radiofrequency carrier signals; a first secured phase cycle element (919), including a local oscillator (911) for generating a local oscillator signal; a mixer (909) coupled to the radiofrequency input (901) and the local oscillator (911) to produce an intermediate frequency signal, modulated with digital signals corresponding to a radio frequency signal selected from the plurality of radio frequency signals; An intermediate frequency filter (915) having a center frequency; said intermediate frequency signal having a nominal frequency corresponding to the center frequency of the intermediate frequency filter (915); a digital signal demodulator (11) including a second phase locked phase element (1111), for the demodulation of the intermediate frequency, to produce the digital signals carried by the intermediate frequency signal; and an element (19) for controlling the operation of the first phase-locked phase element (919), in response to when a control signal generated by the second stage phase element (1111) indicates the state of the phase. operation of the second secured phase cycle element (1111); said control element (19) controlling the first phase locked phase element (919) to (1) establish an initial local oscillator frequency, corresponding to the selected radio frequency signal, during an acquisition mode, beginning when the signal of selected radio frequency is initially selected, and ending when the second assured phase cycle (1111) is appropriately demodulating said intermediate frequency signal, (2) maintaining said initial frequency of the local oscillator during a steady state mode, and (3) changing the frequency of the local oscillator of the initial local oscillator frequency, to reduce a frequency deviation of the intermediate frequency signal of the nominal intermediate frequency, during a fine tuning mode; said control element (19) further controlling the first phase locked phase element (919) to increase the response time of the first phase locked phase element, to allow the second phase locked phase element (1111) track frequency changes of the intermediate frequency signal, due to frequency changes of said local oscillator (911) and, thereby, maintain the appropriate demodulation of the intermediate frequency signal during the fine tuning mode. 12. The apparatus recited in claim 11, characterized in that: the radiofrequency signals have frequencies that are greater than the frequency range that is used for conventional terrestrial radio broadcasting and cable television transmissions; and the first phase locked phase element (919) comprises an integrated phase locked phase tuning control circuit (921), which is normally used in a terrestrial broadcast and cable television receiver. 13. The apparatus recited in claim 11, characterized in that: the radio frequency input (901) is adapted to receive the radio frequency signal from a block converter (3), which is capable of offsetting the frequencies of the carrier signals of radiofrequency of the respective nominal frequencies. The apparatus recited in claim 11, characterized in that: the first phase locked phase element (919) is a phase locked cycle; and the second cycle phase element insured (1111) is a carrier recovery cycle. 15. The apparatus recited in claim 14, characterized in that: the radiofrequency signals are modulated by quaternary phase shift keying with the digital signals; and the demodulator (11) is a quaternary phase shift keying demodulator. 1

6. The apparatus recited in claim 11, characterized in that: the first secured phase cycle element (919) includes a controllable filter (925) that determines the response time of the first secured phase cycle element (919); and the control element (19) controls said filter (925) to increase the response time of the first phase locked phase element (919), during the fine tuning mode. 1

7. The apparatus recited in claim 16, characterized in that: the filter (925) includes first filter steps (925-1) and second (925-2); and the control element (19) controls the second filter stage (925-2) to increase the response time of the first phase locked phase element (919), during the fine tuning mode. 1

8. The apparatus recited in claim 17, characterized in that: the local oscillator (911) is responsive to a tuning control signal, which determines its oscillation frequency; the first phase-locked cycle (919) includes an element (921-9) for comparing the oscillation frequency of the local oscillator (911) with a reference value, to generate an error signal; the filter (925) is coupled to the comparison element (921-9) for filtering the error signal, to produce the tuning control signal for the local oscillator (911); the first (925-1) and second (925-2) filter stages are cascaded between the comparison element (921-9) and the local oscillator (911); and the second filter stage (925-2) includes a filter section (C3, C4, R2, R4, R5) and a switching section (Q2, Q3), to selectively bypass the filter section (C3, C4, R2, R4, R5) of the second filter stage (925-2), under the control of the control element (19). 1

9. The apparatus recited in claim 18, characterized in that: the comparison element (921-9) is coupled to the filter element (925), by means of an amplifier (921-11); and the first filter stage (925-1) includes a filter section (Cl, C2, Rl), which is coupled in a negative feedback configuration- with the amplifier (921-11), in order to form a integrator; the comparison element (921-9) and the amplifier (921-11) are included in an integrated circuit; the filter section (Cl, C2, Rl) of the first filter stage (925-1), and the filter section (C3, C4, R2, R4, R5) of the second filter stage (925-2) , they are external to the integrated circuit. 20. An apparatus for processing digital processing signals modulated with each other, of a plurality of radiofrequency carrier signals, comprising: a radiofrequency input (901) for receiving the modulated plurality of signaling radiofrequency carriers; a first secured phase cycle element (919), including a local oscillator (911) for generating a local oscillator signal; a mixer (909) coupled to the radio frequency input (901) and the local oscillator (911) to produce an intermediate frequency signal, modulated with digital signals corresponding to a radio frequency signal selected from the plurality of radiofrequency signals; An intermediate frequency filter (915) having a center frequency; said intermediate frequency signal having a nominal frequency corresponding to the center frequency of the intermediate frequency filter (915); a digital signal demodulator (11) which 'includes a second phase-locked phase element (1111), for the demodulation of the intermediate frequency, to produce the digital signals carried by the intermediate frequency signal; and an element (19) for controlling the operation of the first phase locked phase element (919), in response to at least one control signal generated by the second phase locked phase element (1111), which indicates the state of operation of the second secured phase cycle element (1111); said control element (19) controlling the first phase locked phase element (919) to (1) establish an initial local oscillator frequency, corresponding to the selected radio frequency signal, during an acquisition mode, starting when the signal of selected radio frequency is initially selected, and ending when the second assured phase cycle (1111) is appropriately demodulating said intermediate frequency signal, (2) maintaining said initial frequency of the local oscillator during a steady state mode, and (3) changing the frequency of the local oscillator of the initial local oscillator frequency, to reduce a frequency offset of the intermediate frequency signal of the nominal intermediate frequency, during a fine tuning mode; said first secured phase cycle element (919) having a first reset time during acquisition mode, a second response time greater than the first reset time, during a steady state mode, and a third response time greater than the second response time, during fine tuning mode.