MXPA96004442A - Method for connecting series separable conditional access modules, circuit for inserting a default sequence and circuit to detect such sequence for the implementation of met - Google Patents

Abstract

The present invention relates to a method for coupling in series separable conditional access modules as well as a circuit for inserting a predetermined sequence and a circuit for detecting said sequences. Where each module has a stream of data passing through it, formed by fixed-length packets separated by a fixed-length space, the method consists of filling the space between packets (G1, G2, G3) with a sequence constant default that does not interfere with the useful content of the packets (P2, P3, P4), this sequence being used to regenerate a packet clock (RP), using only this data stream. Application to a television for payment. Figure

Description

METHOD FOR CONNECTING IN SERIES CONDITIONAL ACCESS MODULES SEPARABLE. CIRCUIT TO INSERT A DEFAULT SEQUENCE AND CIRCUIT TO DETECT SUCH SEQUENCE FOR THE IMPLEMENTATION OF THE METHOD.

DESCRIPTION OF THE INVENTION The present invention relates to a method for coupling in series separable conditional access modules. It also refers to a circuit for inserting a predetermined sequence as described in the method, and to a circuit for detecting said sequence. In the field of digital pay television, the decoders currently on the market include, as schematically shown in Figure 1, an input circuit 1 or "front end" consisting among other things of a demodulator, a demultiplexer 2 associated with a demixer 3, a microprocessor. 4 connected to the demixer 3 to supply notably the control word, RP, and video 5 and audio 6 circuits connected to the output of the demultiplexer. An integrated circuit card 7 that notably includes data authorized for program access is connected in a known manner to the microprocessor 4 of the decoder. The decoder receives a ".multiplexer" signal at its input, which contains a large number of programs, some being blank, and others being mixed. The video signal is sent on the input circuit 1, which makes it possible to recover at the output a data stream, CD or a "transport stream" consisting of fixed-length packets separated by a fixed-length space between packets , each packet being detected by a packet clock, RP. The role of the demultiplexer, demixer, microprocessor and integrated circuit card is notably to mix the combined packages that belong to the selected program with respect to which the user has the right of access. Currently, service providers that wish to transmit mixed programs, define the specialties of their own decoder, and in particular those of their access control system. These specific or secret elements of the conditional access sub-system avoid its standardization. To remedy these disadvantages and allow the production of normal, future digital television reception systems, it has been proposed to isolate the conditional access sub-system within a separable module in an integrated circuit card format or PCMCIA format. In this case, several separable modules can be connected to a single decoder. The entire data stream is obtained at the output of the decoder input circuit and passes successively through each module connected in cascade. Each module makes it possible to mix and demix packages that refer to this. In this way, when the conditional access information used for the selected program is recognized by the module and when the user has access to this program, then and only in such cases are the corresponding packets of the data flow that are demixed while they maintain their relative positions. A decoder of the above type is shown schematically in Figure 2. The decoder includes an input circuit 1 ', which receives the high-frequency signal S, demodulates it to obtain the CDO data stream or "transport stream" and the package clock, RPL, and then sends it to the input of the first separable module A. Each separable module also includes a demultiplexer 2 ', associated with a demixer 3' and a microprocessor 4 '. This can be in the integrated circuit card format or in the format of a PCMIA module such as those that exist in the world of microcomputation. The data stream CD1, partially demixed by the previous circuits, leaves the module displacement in time with respect to the current through a dedicated output, as shown on the contact surface 5 '. It is then sent to a dedicated input of the second separable module B, where it undergoes an identical processing according to the number of separable modules that can be connected to the decoder. The data stream CD2 leaves the last module and is sent to the input of a demultiplexer 6 'in the decoder, which is connected in a known manner to the audio 8' and video 7 'circuits. In addition, the decoder includes a microprocessor 9 'connected to each microprocessor 4' located in each separable module and demultiplexer 6 '. As mentioned above, the data stream in the output of a module is deviated in time with respect to the data stream in the input, and therefore it is necessary to have a clock that allows to find the data, as in the case of the decoders currently used. In addition, the data stream is divided into packets of fixed-length bits separated from each other by a fixed-length space, in this case, a packet clock RPO is associated with the data stream to indicate the start and end of a package. The package clock is usually used in the detachable module. Thus in Europe, the proposed common contact surface provides an input packet clock RP0-RP1 and an output packet clock RP1-RP2, which requires two dedicated contact surface pins, as presented in the Figure 2, which corresponds to the DVB propositions in the course of standardization. In the United States, the proposed separable module provides a packet clock at the module input, but no packet clock at the output. Although this proposition makes it possible to save a contact surface pin, it has the disadvantage that the separable module must be able to provide, in the decoder and possibly in the other modules, information with respect to the delay given in the packets of the current. data passing through it, so that the decoder and the separable modules are able to reconstruct the packet clock from the data stream that they re-enter through a correct displacement of the reference pack clock. The object of the present invention is to correct the above disadvantages by proposing a method that makes it possible not only to use dedicated pins in the adjoining module / decoder surface, to obtain the packet clock in each module and in the decoder. The object of the present invention is a method for coupling in series separable conditional access modules without resorting to a packet clock signal, each module passing through it a data stream formed by fixed length packets separated by a space of fixed length, characterized in that the space between packets is filled with a predetermined sequence that does not interfere with the useful content of the packets, this sequence being used to regenerate a packet clock. According to a preferred embodiment, the predetermined sequence consists of a series of increments or reductions of binary data. Preferably, the predetermined sequence is continued by a data item of determined and identical value located at the start of all packets. Another object of the present invention is a circuit for inserting the predetermined sequence located at the output of the decoder input circuit. The circuit includes a multiplexer that receives the original data stream in a first input and, in a second input, the data in the predetermined sequence that comes from means generating the predetermined sequence, a packet start detector and packet terminator. allowing them to be selected either the first entry or the second entry. Still another object of the present invention is a circuit for detecting the predetermined sequence located in the modules and the decoder. This circuit includes: - a comparator that receives in a first input the current of data that incorporate the predetermined sequence between each packet and in a second input the data of the predetermined sequence; - means for generating the data of the predetermined sequence, these means being directed by the output of the comparator for sending the first data item of the predetermined sequence when the comparator detects inequality and for sending the next data item of the predetermined sequence when the comparator detects equality, and - means for generating a pulse corresponding to the length of a packet, said means being activated by detection of the last data item of the predetermined sequence. Other features and advantages of the present invention will emerge after reading the description of the preferred embodiment, this description being given with reference to the accompanying drawings, in which: Figure 1, already described is a block diagram of a decoder according to the prior art; Figure 2, already described, is a block diagram of a decoder provided with separable modules, according to the prior art; Figure 3 is a block diagram of a decoder provided with separable modules according to the present invention; Figure 4 is a diagram of an insertion circuit according to the present invention; Figure 5 is a timing control diagram explaining the operation of the insertion circuit; Figure 6 is a diagram of a detection circuit according to the present invention; and Figure 7 is a timing control diagram explaining the operation of the detection circuit. To simplify the description, in the Figures, the same references designate the same components. In accordance with the present invention, to avoid the use of at least one pin dedicated to the packet clock RPO at the interface between the decoder and the detachable module, use is made of the fact that, in the systems currently defined in the states United and in Europe, the CD data stream is divided into fixed-length packets, the packets being separated by a space between packets that is also of fixed length.

Therefore, the invention consists in filling this space between fixed-length packets with a predetermined sequence. This sequence is constant and does not interfere with the useful content of the packets. It is used to regenerate the package clock. The predetermined sequence preferably consists of binary data increment or reduction series. It can be continued by a data item of determined and identical value located in all packages, at the beginning of these packages. As an example, in the case of standard European DVBs in the course of the discussion, based on the standard MRP2 system, the data stream is divided into 1504-bit packets (188 octets) separated from each other by a 128-bit space. bits (16 bytes). These 16 octets are filled with the sequence that varies from 0 to 15, the start of a packet is then identified by the succession of 16 octets successively taking an increment value on the scale from 0 to 15. The probability of detecting a false synchronization then it is equal to 5.10 + 37. This probability is calculated assuming that the sequence can not arise partially with a series of the same length of data streams. In addition, the data stream defined by the standard MPGE2 system has a constant octet at the beginning of the packet used for synchronization. According to another feature of the invention, this octet can be included at the end of the predetermined sequence to further reduce the probability of false detection. The use of a predetermined sequence consisting of a series of octet increments has been described. It is obvious to one skilled in the art that any strictly monotonic increase or reduction sequence can be used.

An explanation of the modifications made to the decoder in Figure 2 will now be given, to implement the previous method. In this case, the high-frequency signal S, at the input of the decoder, is sent on an input circuit 1 ', identical to that of Figure 2. At the output of this input circuit 1', the data stream CDO and the RPO package clock are obtained in a known manner. According to the invention, the CDO data stream and the packet clock RPO are sent on a circuit 10 to insert a predetermined sequence which will be described in more detail below. A data stream CDO 'including the predetermined sequence between each packet is obtained at the output. This data stream CDO 'is sent via a dedicated pin of the contact surface 5' to the first separable module A. In this first module A, it is processed by the detection circuit 11 'for the predetermined sequence in order to obtaining the package clock required to perform the operations performed by the demultiplexer 2 ', the demixer 3' and the microprocessor 4 ', which have the same functions as those of the embodiment of Figure 2. These functions are not part of the present invention and therefore will not be described in any detail. Once processed, the new data stream CD1 is sent by means of a dedicated output of the contact surface at the input of the second separable module B identical to the first separable module A with respect to its structure. Therefore, a contact surface 5 ', a detection circuit 11' for the predetermined sequence, a demultiplexer 2 ', a demixer 3' and a microprocessor 4 'are included. The data stream CD1 suffers, in the module B, a processing similar to that which is suffered in the module A. The new data stream CD2 is then sent to the decoder in the mode presented with the two separable modules. The data stream CD2 is then sent to the input of the demultiplexer 6 'and to the input of a detection circuit 11' for the predetermined sequence identical to that of the separable modules for recovering the packet clock RP2 which is sent on the demultiplexer 6 '. The other circuits, particularly the video circuit 7 ', the audio circuit 8' and the microprocessor 9 'are identical to the decoder circuits in Figure 2 and operate in the same way. A description will now be given, referring to Figures 4 and 5, of a circuit mode 10 'to insert the predetermined sequence. As shown in Figure 4, the circuit includes an ultiplexer 100, which receives the octets of the original data stream CDO at an input A. In this other input B receives the octets of the predetermined sequence. Moving from input A to input B and vice versa, it is determined by a selection pulse, selecting A / B, which is obtained from a packet limit detection circuit 101 that receives the packet clock RPO at its input. The octet of the predetermined sequence can be obtained in different ways. Thus, in the embodiment presented in Figure 4, the circuit includes a counter 102 that counts from 1 to 16 in the clock speed CB or octet clock. The counter includes an input readjustment 1, which is activated by one end of the packet pulse PF that comes from the packet start and packet detection circuit 101. With each clock pulse, the counter 102 sends a data item , which corresponds to the number of the octet in the sequence to a table 103, which contains the different values of the packets, the pulse selector A / B is in logic 0 and the input A of the multiplexer 100 is selected to allow the bytes to pass of the original CDO data stream. In this way, a data stream CDO 'is obtained at the output of the multiplexer, with the insertion of a predetermined sequence. An explanation will now be given, referring to Figures 6 and 7 of a circuit mode 11 'to detect the predetermined sequence. The circuit therefore includes a comparator 110 which receives at its input A the octets of the data stream provided with the predetermined sequence as CDO, CD1, CD2 and, at their input B, the octets of the predetermined sequence coming from a circuit that defines the predetermined sequence. In the embodiment of Figure 6, this circuit consists of a counter 111 that counts the octet clock frequency. This is because the octet clock CB is applied to the "clock" input of the counter 111. In addition, the counter receives the comparator output at its input 1 when A = B and at its readjustment input the output of the comparator when A ^ B. In the presented mode, the counter counts between 1 and 16. The counter output is sent as an address to a table 112 that contains the value of the octets of the predetermined sequence. The octet of the predetermined sequence corresponding to the number of octets coming from the counter is sent to the B input of the comparator 110. When the counter exceeds the value 16, it sends a pulse N >16 at the "start" input of a pulse generator 113, which actually consists of a monostable multivibrator with a length of 188 bytes, this generator giving the RP packet clock at its output. The operation of the circuit will be better understood by the timing control diagram in Figure 7. In this Figure, BS corresponds to the data stream CDO1, CD1, CD2 provided with the predetermined sequence. When the system is started, the counter is set to 1. The actual octet coming from the data stream is compared to the octet of the predetermined sequence whose range is given by the counter. If A B, the counter is readjusted to l, if A = B the counter is incremented. When the counter reaches the value of 17, it sends a pulse represented by N > 16 in Figure 7, which drives the monostable multivibrator 113, as represented by RP in the Figure. However, since the monostable multivibrator may not be reset to 0 and its pulse has a duration corresponding to one packet, that is 188 octet CB clock cycles in the presented mode, no detection can be triggered again from a generator default sequence 113. In this way, as shown in Figure 7, the false sequence, FS drives a pulse N > 16, but this pulse does not affect the RP package clock. It is obvious to those skilled in the art that the predetermined sequence generation circuits can be modified, as mentioned for the circuit for inserting said sequence. The output value of the counter can be used as the value of the octet of the predetermined sequence or other means to direct the table that can be produced by any type of memory. In addition, the method of the present invention can also be applied to any module with a processing function of a multiplexer formed by fixed length packets separated by a fixed length space.

Claims (13)

1. A method for coupling in series separable conditional access modules, each module having a stream of data passing through them, formed by fixed length packets separated by a fixed length space, characterized in that the space between packets is filled with a constant predetermined sequence that does not interfere with the useful content of the packets, this sequence being used to regenerate a packet clock, using only this data stream.

2. The method in accordance with the claim 1, characterized in that the predetermined sequence consists of a series of increments or reductions of binary data.

3. The method in accordance with the claim 2, characterized in that the predetermined sequence is continued by a data item of defined and identical value located at the start of all the packets.

4. A circuit for inserting the predetermined sequence to implement the method according to claims 1 to 3, characterized in that it includes a multiplexer that receives the original data stream (CDO) in a first input and in a second input the data of the predetermined sequence that come from the means generating the predetermined sequence a packet start and packet start detector that allows either the first or the second input to be selected.

5. The insertion circuit according to claim 4, characterized in that the means for generating the predetermined sequence consist of a memory consisting, in successive directions, of the different data of the predetermined sequence, the addresses being incremented in each octet clock cycle. and they are sent back to the starting address of each package end.

6. The insertion circuit according to claim 5, characterized in that the address of the memory made by the counter incremented by 1 in each packet clock cycle and readjusted to 1 in each packet end.

7. The insertion circuit according to claim 4, characterized in that the means for generating the predetermined sequence consist of a reset adjuster to the initial value of the predetermined sequence in each packet term and incremented by 1 in each octet clock cycle.

8. A circuit for detecting the predetermined sequence for implementing the method according to claims 1 to 3, characterized in that it includes: a comparator that receives, in a first input, the data stream that incorporates the predetermined sequence between each packet and, in one second entry, the data of the predetermined sequence; means for generating the data of the predetermined sequence, these means being directed by the comparator output to send the first data item of the predetermined sequence when the comparator detects an inequality and for sending the next data item of the predetermined sequence when the comparator detects an equality, and means that generate a pulse corresponding to the length of a packet, these means being activated by the detection of at least one data item in the predetermined sequence.

9. A circuit according to claim 8, characterized in that the means for generating the data of the predetermined frequency consist of a table containing, in successive directions, the various data of the predetermined sequence, the direction of this table being fixed towards the first address each time the comparator detects an inequality and increases or decreases each time the comparator detects an equality, the table being associated with the means that send a pulse N > 16 when all addresses of the tables have been scanned.

10. The circuit according to claim 9, characterized in that the address is performed by a counter readjusted to 1 in the initial direction each time the comparator detects inequality, and increasing or decreasing each time the comparator detects an equality, the output of the comparator directing the table and the counter being incremented or reduced in a scale of limit values and sending a pulse at the end of the scale (N> 16).

11. The circuit according to claim 10, characterized in that the means for generating the data of the predetermined sequence consist of a counter whose output directly gives the values of the octet of the predetermined sequence.

12. The circuit according to any of claims 8 to 11, characterized in that the means for generating a pulse corresponding to the length of a pack consist of a monostable multivibrator that can not be readjusted to 0.

13. A method for coupling in series any module with a processing function of a multiplexer formed by fixed length packets, separated by a fixed length space, characterized in that the space between packets is filled with a constant predetermined sequence that does not interfere with the content useful of the packages, this sequence being used to regenerate a package clock.