JP2564679B2 - Facsimile receiver using satellite broadcasting - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is, for example, a broadcasting satellite (BS), a communication satellite (CS).
The present invention relates to a facsimile receiving apparatus using satellite broadcasting, which prints based on type information data transmitted by using, for example.

[Prior Art] In satellite television broadcasting using a communication system that transmits a video signal and an audio signal using a communication satellite,
If the video signal and the audio signal are scrambled for communication, the video signal and the audio signal can be normally transmitted only to the communication destination having the receiving system including the scramble key information and the descrambling device. In such a communication system, information can be simultaneously transmitted from one transmission side to a plurality of n communication destinations.

FIG. 5 shows the configuration of such a communication system. In the figure, 100 is a transmission system, 200 is a communication satellite, and 300 is a reception system.

The video signal SV and the audio signal SA are supplied to the scramble device 101 that constitutes the transmission system 100, and each signal is scrambled based on the control signal SC, and for example, the scrambling key can be changed. , The communication destination that can be normally transmitted is controlled.

The audio signal SA is PCM (Pulse Code Modulation), and is transmitted through a communication path capable of transmitting other digital data.

For PCM audio signals, for example, pseudo random signals (P
Scrambling using N signal). The video signal is scrambled by, for example, a scanning line signal switching method (line rotation) or a scan transfer method (line permutation).

The video signal and PCM audio signal scrambled by the scrambler 101 are supplied to the modulator 102. In the modulator 102, the PCM audio signal is modulated by, for example, the 4-phase DPSK method, and then combined with the video signal, and the combined signal is FM-modulated.

The FM modulated signal from the modulator 102 is the transmitter 103 for the communication satellite.
After being frequency-converted by, the signal is transmitted to the communication satellite 200.

Further, the FM modulated signal from the communication satellite 200 is received by the CS antenna and the CS converter 301 included in the receiving system 300, frequency-converted, and then supplied to the CS tuner 302.

The tuner 302 demodulates the FM modulation signal of the selected channel to obtain a video signal and a 4-phase DPSK modulation signal. Further, the 4-phase DPSK modulated signal obtained by FM demodulation is demodulated to obtain a bit stream signal.

The video signal and the bit stream signal from the tuner 302 are supplied to the descrambling device 303 to be descrambled.

If the descrambler 303 has the key information for descrambling the video signal and the bit stream signal, the descrambler 303 normally performs the descrambling to obtain the original video signal SV and audio signal SA.
Are obtained and normally viewed by the monitor 304.

By the way, in recent years, with the demand for more sophisticated and diversified information, in addition to video and audio information, type information (facsimile information) that complements the information and provides detailed explanations is needed. ing.

In order to transmit such print information, the conventional facsimile communication using a telephone line is used.

For example, as shown in FIG. 5, a facsimile device 104 is provided on the transmitting system 100 side, and a facsimile device 305 is provided on the receiving system 300 side which is an individual communication destination.
And the facsimile machines 104 and 305 are
Connected with a telephone line 400.

When transmitting the type information, the type information is transmitted from the facsimile device 104 to the destination facsimile device 305 via the telephone line 400. Then, the facsimile device 305
From, a print screen (recording paper) 306 on which type information is recorded is output.

By the way, in the facsimile communication through the telephone line 400, although it is called the broadcast communication, the communication is not performed strictly at the same time, and a time lag occurs. This time lag increases as the number of destinations increases.

Further, as the number of communication destinations increases, the time required for communication increases, and the use time of the line increases, so that the cost required for communication increases.

Furthermore, it is necessary to transmit video signals and audio signals and print information in association with each other, but video signals and voice signals are sent using communication satellites, while print information (facsimile information) is Since they are separately transmitted by facsimile communication, transmission management becomes complicated.

Therefore, it is considered that the print information is also transmitted using a communication satellite. In this case, the communication system is configured as shown in FIG. 6, for example.

In the figure, reference numeral 105 is a facsimile signal generator. The type information FI is supplied to the signal generator 105. In this signal generator 105, a facsimile signal SI is formed based on the type information FI. This facsimile signal
SI is supplied to the scrambler 101 in synchronization with the clock CLK.

FIG. 7 shows the frame structure of the facsimile signal SI.

The facsimile signal SI includes a data packet portion PAC consisting of 272 bits (34 bytes) of digital data, and 16 bits (2 bits added to the head of the data packet portion PCA.
Byte) mode control unit MC and packet format. One frame consists of 32 packets,
A 16-bit (2-byte) frame synchronization signal FC is added to the beginning of the frame. In other words, one frame is 9232
It consists of bits (1154 bytes).

In this case, the mode control unit MC determines whether the packet is the facsimile apparatus SI.

Further, although not shown, the packets of the facsimile signal SI include a packet including a control signal such as a program selection signal and a packet for which an image signal is obtained. Since the above packet transmission method is adopted, data of various services having various bit rates can be time-division multiplexed and transmitted at the same time, and a flexible and highly expandable system can be constructed.

The facsimile signal SI is sequentially transmitted in frame units. In each frame, 16 bits of the frame synchronization signal FC are transmitted, and then 32 packets of signals are transmitted by 4-bit interleaving.

That is, in order to protect the data against a burst error, the lower 4 bits of the first byte are sequentially transmitted from packet 1 to packet 32 as shown by arrow A in FIG. 4 bits are sequentially transmitted from packet 1 to packet 32, then the lower 4 of the 2nd byte
Bits are transmitted sequentially from packet 1 to packet 32,
In the same manner, the upper 4 bits of the 36th byte are finally transmitted sequentially from packet 1 to packet 32.

It should be noted that the 16-bit frame synchronization signal FC does not fluctuate over time, has the same code pattern at all times, and is not protected by error correction additional bits.

The facsimile signal SI from the signal generator 105 is inserted into a predetermined area of the frame structure of voice data, and is scrambled based on the control signal SC together with the PCM voice signal.

In the transmission system 100, other configurations are the same as those in the example of FIG. 5, and the facsimile signal SI is modulated by the modulator 102 together with the PCM voice signal by the 4-phase DPSK method, and this is combined with the video signal and FM-modulated. FM modulated signal is transmitter 103
Is transmitted to the communication satellite 200.

In the receiving system 300, the video signal and the bit stream signal from the CS tuner 302 are supplied to the descrambling device 303 and descrambled, as in the example of FIG.

If the descrambling device 303 has the key information for descrambling the video signal and the bit stream signal, the descramble device 303 normally descrambles the original video signal SV, audio signal SA and A facsimile signal SI is obtained.

The video signal SV and the audio signal SA from the descrambler 303 are supplied to the monitor 304, and the image and sound are reproduced and viewed.

Further, 307 is a type information recording device, and this recording device 3
In 07, the facsimile signal S from the descrambler 303 is sent.
I and clock CLK are provided. This recording device 307
Is configured, for example, as shown in FIG.

In FIG. 1, the facsimile signal SI and the clock CLK from the descrambler 303 are supplied to the data capturing section 1. In this data acquisition unit 1, a facsimile signal
The frame synchronization signal FC is detected from the SI, the frame synchronization signal is reproduced, data is taken in based on the reproduced frame synchronization signal, and deinterleave processing is performed.

The deinterleaved data output from the data acquisition unit 1 is supplied to the signal processing unit 2. The signal processing unit 2 performs error correction processing and processing such as discrimination between a control signal including a program number and a page number and an image signal.
Then, the image signal of the required program and page is supplied from the signal processing unit 2 to the image receiving unit 3 for printing.

FIG. 9 shows the structure of the main part of the data acquisition unit 1.

In the figure, a facsimile signal SI from the descrambler 303 and a clock CLK for sampling this signal SI are supplied to the frame synchronization signal reproduction circuit 11 and the deinterleave circuit 12.

The frame synchronization signal FC ′ output from the frame synchronization signal reproduction circuit 11 is supplied to the deinterleave circuit 12.
In the deinterleave circuit 12, the write address is initialized by the frame synchronization signal FC ', the one-frame facsimile signal SI is once written in the built-in memory, and is read out so as to be the code string before interleaving and is stored in the memory 13 Stored in.

Here, the reproduction circuit 11 uses the frame sync signal FC of the signal SI.
It is necessary to reproduce the frame synchronization signal FC ′ that exactly matches the timing of the frame synchronization signal F ′, and to stabilize the frame synchronization signal F even when the reception environment is bad and noise is mixed.
It is necessary to regenerate C '. Therefore, the reproduction circuit 11 is configured to perform the reproduction operation of the frame synchronization signal FC 'as follows.

That is, when a code pattern of the frame synchronization signal FC first arrives as a reference, when the same code pattern arrives a predetermined number of times consecutively in the frame period from this reference, a regular frame synchronization signal is detected. Then, the reproduction of the frame synchronization signal FC 'synchronized with it is started.

Further, when the same code pattern does not arrive in the frame cycle, it is determined that the regular frame sync signal is not detected, and the same processing is performed with reference to the time when another frame sync signal FC arrives.

Further, once the reproduction of the frame synchronization signal is once started, the reproduction of the frame synchronization signal FC ′ is stopped only when the code pattern of the frame synchronization signal FC does not arrive continuously for a predetermined number of times in the frame period, and In addition, the detection of the regular frame sync signal for reproducing the frame sync signal is performed in the same manner as described above. That is, once the frame synchronization signal F
After the reproduction of C ′ is started, even if the code pattern of the frame synchronization signal FC does not arrive the number of times less than the predetermined number of times, the frame synchronization signal FC ′ is protected and the reproduction is continued.

FIG. 10 shows a reproducing circuit for performing the reproducing operation as described above.
11 shows an example of 11.

In the figure, 20 is a frame sync signal pattern detection circuit that detects the code pattern of the frame sync signal FC based on the facsimile signal SI and the clock CLK and outputs a detection signal, and 21 is the code of the reference frame sync signal FC. 1 frame counter for measuring the frame period from the time when the pattern arrives, 22 is a coincidence pulse when the same code pattern arrives at the frame period from the time when the code pattern of the reference frame synchronization signal FC arrives The first multiplexer 23 to output, when the same code pattern does not arrive in the frame period from the time when the code pattern of the reference frame synchronization signal FC arrives,
It is a 2nd multiplexer which outputs a mismatch pulse.
The multiplexers 22 and 23 select the A input when the frame synchronization signal FC 'is not reproduced and the B input when the frame synchronization signal FC' is reproduced.

Further, 24 is a coincidence counter that counts the coincidence pulses and gives an output when it reaches a preset predetermined value, and 25 indicates an output when the mismatch pulses are counted and reaches a preset predetermined value. When the output of the coincidence counter 24 is given, the non-coincidence counter 26 gives 1 in response to the detection signal from the pattern detection circuit 20 to measure one frame period to reproduce and output the frame synchronization signal FC '. A frame counter, 27 is a flip-flop that outputs a frame synchronization signal synchronized with the clock CLK, and 28 is a multiplexer according to whether or not the frame synchronization signal is being reproduced.
A selection signal output circuit that supplies selection signals to 22 and 23.

To briefly explain the operation, first, the frame synchronization signal F
Before the reproduction of C'is performed, the A inputs are selected in the multiplexers 22 and 23, respectively. When the code pattern of the frame synchronization signal FC arrives first, the pattern detection circuit
The detection signal is output from 20 and this detection signal
It is output as a coincidence pulse via 29, AND gate 30, and multiplexer 22. As a result, the 1-frame counter 21 is reset, the clock CLK is counted, and the 1-frame counter 21 outputs a signal after a frame period.

The signal output from the 1-frame counter 21 one frame later and the detection signal from the pattern detection circuit 20 are simultaneously supplied to the AND gate 30, so that the AND gate 30
Matching pulses are sequentially output from 30.

When this match pulse continues for a predetermined number of times, a gate output is supplied from the match counter 24 to the AND gate 32, and the detection signal from the pattern detection circuit 20 is sent to the inverter 2
It is supplied as a reset signal to the 1-frame counter 26 via the 9, AND gate 32 and the OR gate 33. As a result, the 1-frame counter 26 outputs the frame synchronization signal FC 'in a frame cycle in response to the detection signal from the pattern detection circuit 20.

When the frame synchronization signal FC 'is output, a corresponding signal is output from the flip-flop 27, which is supplied as a reset signal to the 1-frame counter 26 via the OR gate 33. Even if the detection signal is not supplied, the 1-frame counter 26 stably outputs the frame synchronization signal FC '.

Also, when the reproduction of the frame synchronization signal FC ′ is started,
The B inputs are selected in the multiplexers 22 and 23, respectively. When the pattern detection circuit 20 does not output the detection signal in the frame cycle, the flip-flop 27
The output signal is output as a mismatch pulse via the AND gate 31 and the multiplexer 23, and the mismatch counter 25 outputs a signal when the mismatch pulse continues for a predetermined number of times. This allows the match counter
24 is reset, and the input of the clock CLK to the 1-frame counter 26 is blocked by the AND gate 34, and 1
The output of the frame synchronization signal FC 'from the frame counter 26 is stopped.

[Problems to be Solved by the Invention] In the configurations of FIGS. 9 and 10, the counters 21 and 26 for counting one frame period, the same code in the frame period from the code pattern of the reference frame synchronization signal FC It requires a coincidence counter 24 for counting the number of times the pattern has arrived or has not arrived, a mismatch counter 25, multiplexers 22 and 23, a gate circuit, a deinterleave circuit including a read and write counter, etc. There is a drawback that

Therefore, an object of the present invention is to satisfactorily reproduce and protect a frame synchronization signal and perform interleave processing with a simple configuration.

[Means for Solving the Problems] The present invention uses a communication path for transmitting voice in PCM in satellite television broadcasting to time-division-multiplex digital facsimile information with PCM voice information, and perform interleave processing. It is a facsimile receiving apparatus for receiving a facsimile broadcast which is applied and transmitted.

Then, comparing with the code pattern of the frame synchronization signal,
When they match, the frame synchronization signal pattern detecting means for outputting a pattern detection signal, and the frame synchronization signal reproduced based on the detection signal output from the frame synchronization signal pattern detecting means and the clock synchronized with the input data And a microprocessor for performing deinterleave processing.

Further, the microprocessor receives the detection signal as the reference signal, and in response thereto, counting means for starting the counting of the clock and, based on the count value of the counting means, the frame period from the time when the reference signal is given. The discriminating means for sequentially discriminating whether or not the detection signal is output at every frame cycle, and based on the output of the discriminating means, before the frame synchronization signal is reproduced, from the time when the reference signal is given. When the output of the detection signal is continuous a predetermined number of times in the frame period, based on the output of the output means for reproducing the frame synchronization signal synchronized with the detection signal and the determination means,
After the frame synchronization signal is reproduced, only when the detection signal is not output a predetermined number of times in the frame cycle, the protection means for stopping the reproduction of the frame synchronization signal and the frame synchronization signal based on the output of the discrimination means. Before there is no detection signal output from the reference signal in the frame period, and after the frame sync signal is played,
When the output of the detection signal is not consecutive a predetermined number of times in the frame period, a setting means for newly setting the reference signal by giving the detection signal different from the reference signal as the reference signal to the counting means, A deinterleave processing means for taking in input data and performing deinterleave processing when the frame synchronizing signal is being reproduced by the output means.

[Operation] According to the configuration described above, the microprocessor 40 performs the processing to reproduce and protect the frame synchronization signal FC ′ and also performs the deinterleave processing. Therefore, the hard counter, gate circuit, and deinterleave as in the conventional example are performed. No circuit is required, and the circuit configuration is simple.

[Example] An example of the present invention will be described below with reference to FIG. A facsimile receiving apparatus using satellite broadcasting of the present invention receives a facsimile broadcasting using satellite television broadcasting by a broadcasting satellite, a communication satellite, or the like. The embodiment shown in FIG. 1 corresponds to the data acquisition unit (FIG. 9) of the type information storage device 307 (FIG. 8) of the communication system (FIG. 6) using a communication satellite. In FIG. 1,
Portions corresponding to those in FIGS. 9 and 10 are designated by the same reference numerals. In this embodiment, facsimile broadcasting is performed using a communication path for transmitting PCM audio signals of satellite television broadcasting using a communication system. This communication path is packet-type digital transmission, and data of various services of various bit rates can be time-division multiplexed and simultaneously transmitted. For this reason, a high quality facsimile transmission is possible without disturbing other signals, and the system is flexible and highly expandable.

In the figure, facsimile signal SI and clock CL
K is supplied to the frame synchronization signal pattern detection circuit 20. The pattern detection circuit 20 has the same configuration as that of the example of FIG. That is, the code pattern of the frame synchronization signal FC is stored in advance, and this code pattern and the clock CL
The bit pattern of the signal SI that is sequentially input in synchronization with K is compared, and when they match, the detection signal SD is output. The detection signal SD from the pattern detection circuit 20 is supplied to the microprocessor (MPU) 40.

Further, the clock CLK is supplied to the frequency dividing circuit 50. The frequency dividing circuit 50 is provided to lengthen the interrupt cycle so that the microprocessor 40 has a margin of processing as described later. The frequency division ratio of the frequency dividing circuit 50 is 16 which is the number of bits of the frame synchronization signal FC and 92 which is the number of frame bits.
Any common divisor of 32 will suffice, and in this example it is divided by 8.
A clock (hereinafter referred to as “divided clock”) CLK ′ output from the frequency dividing circuit 50 is supplied to the microprocessor 40.

Also, the facsimile signal SI and the clocks CLK, CLK ′
Is supplied to the serial-parallel conversion circuit 60. The number of parallel bits of the conversion circuit 60 is determined in consideration of the number of data buses of the microprocessor 40 and the operation speed,
In this example, it is set to 8 bits. In this case, the clock CLK is used as a shift clock, and the clock CLK 'is used as a latch signal for parallel output. This conversion circuit
The parallel data output from the 60 is a microprocessor
Supplied to 40.

In the microprocessor 40, the detection signal SD from the pattern detection circuit 20 and the division clock CL from the division circuit 50
The frame synchronization signal FC 'is reproduced and protected based on K'. That is, the detection signal SD and the divided clock
The transition to the interrupt processing is performed by CLK ', and the frame sync signal FC' is reproduced and protected. In addition, the microprocessor 40 uses the regenerated frame sync signal.
Based on FC ', the conversion circuit 60 performs deinterleaving processing of the facsimile signal SI converted into parallel data. The data deinterleaved by the microprocessor 40 is supplied to and stored in the memory 13 as write data.

Frame sync signal FC 'in microprocessor 40
The reproducing operation of is performed as follows.

When the code pattern of the frame synchronization signal FC first arrives, that is, the first detection signal SD is used as a reference signal to start counting the divided clock CLK ′, and the frame cycle is detected based on this count value. It is assumed that the regular frame synchronization signal is detected when the same code pattern arrives a predetermined number of times, for example, three times consecutively in the frame cycle, and the reproduction of the frame synchronization signal FC ′ synchronized with it is started. When the same code pattern does not arrive in the cycle, it is assumed that the normal frame sync signal is not detected, and the time when the code pattern of another frame sync signal FC arrives, that is, another detection signal SD is used as a new reference signal. Processing is performed to detect a normal frame synchronization signal and reproduce the frame synchronization signal FC '.

Further, once the reproduction of the frame synchronization signal FC ′ is started, the reproduction of the frame synchronization signal FC ′ is stopped only when the code pattern of the frame synchronization signal FC does not arrive for a predetermined number of times continuously in the frame cycle. The detection of the regular frame synchronization signal for newly reproducing the frame synchronization signal FC 'is performed in the same manner as described above.

Further, the operation of the deinterleave processing in the microprocessor 40 is performed as follows.

That is, when the frame synchronization signal FC 'is being reproduced, the conversion circuit 6 is operated by the divided clock CLK'.
The 1-byte parallel data starting from 0 is taken in, deinterleaved so as to obtain a code string before interleaving, and written in the memory 13.

The microprocessor 40 performs the reproduction and protection of the frame synchronization signal FC 'and the deinterleave processing as described above, and constitutes the following means (see FIG. 2).

That is, the detection signal SD is given as a reference signal, and in response thereto, the counting means 401 which starts counting the divided clock CLK ′, and the time when the reference signal is given based on the count value of the counting means 401. From the discriminating means 402 for sequentially discriminating whether or not the detection signal SD is output in each frame period for each frame period, based on the output of the discriminating means 402, before the reproduction of the frame synchronization signal FC ′ is performed. When the output of the detection signal SD is repeated a predetermined number of times in the frame period from the time when the reference signal is given, the output means 403 for reproducing the frame synchronization signal FC ′ synchronized with the detection signal SD, and the discrimination means 403 Frame sync signal F based on output
Based on the output of the discriminating means 403 and the protection means 404 that stops the reproduction of the frame synchronization signal FC ′ only when the output of the detection signal SD is not continued for a predetermined number of times in the frame period after C ′ is reproduced. , Frame sync signal F
When the detection signal SD is not output from the reference signal in the frame cycle before C'is reproduced, and when the frame synchronization signal FC 'is reproduced, the detection signal SD is continuously output a predetermined number of times in the frame cycle. If not, the setting means 405 for newly setting the reference signal by supplying the detection signal SD different from the detection signal SD given as the reference signal to the counting means 401 as the reference signal as described above, and the output described above. When the frame synchronization signal FC 'is reproduced by the means 403, the deinterleave processing means 406 which takes in the parallel data SI from the conversion circuit 60 and performs the deinterleave processing in units of 4 bits is configured.

Next, the operation of the microprocessor 40 will be described with reference to FIGS. 3 and 4 are flowcharts of interrupt processing for reproduction, protection, and deinterleave processing of the frame synchronization signal FC '.

At the time of start-up, only the interrupt by the detection signal SD is permitted, and the input of the detection signal SD shifts to the interrupt processing of FIG.

In FIG. 3, in step n1, in order to use the interrupted detection signal SD as a reference signal, subsequent interrupts of the detection signal SD are prohibited, and the process proceeds to step n2 to interrupt the divided clock CLK ′. Allow and exit.

FIG. 4 is a flowchart of interrupt processing by input of the divided clock CLK ′ after the code pattern of the reference frame synchronization signal arrives by the interrupt processing of FIG.

When the divided clock CLK 'is input, the process proceeds to the interrupt processing of FIG. 4, and in step n1, 1 is added to the count value of the divided clock counter as the counting means inside the microprocessor 40, and the process proceeds to step n2. Then, it is determined whether or not the count value of the frequency-divided clock counter is the frame synchronization signal transmission period, that is, whether or not the frame cycle has started from the time when the interrupted detection signal SD (reference signal) is given. When it is determined that the frame sync signal
Move to step n3 to perform a process for confirming whether the FC has actually arrived.

In step n3, it is determined whether or not frame synchronization is established, that is, whether or not the frame synchronization signal FC 'is being reproduced. If it is determined that reproduction is not being performed, then the process proceeds to step n16 to detect. When it is determined whether the signal SD is output, and when it is determined that the signal SD is not output, it is necessary to search for and set another frame synchronization signal FC that is another reference, so the coincidence counter is reset in step n22. After that, the process proceeds to step n23, the interrupt is prohibited by the divided clock CLK ', and further, the process proceeds to step n24, the interrupt by the detection signal SD is permitted, and the process ends. Therefore, in this case, by inputting another detection signal SD, the process shifts to the interrupt process shown in FIG.

When it is determined in step n16 that the detection signal SD is output, the process proceeds to step n17, where the detection signal SD
1 in the count value of the built-in coincidence counter that counts the number of output of
Then, the process proceeds to step n18 and whether or not the count value of the coincidence counter reaches a preset predetermined value, that is, whether or not the detection signal SD is continuously output a predetermined number of times in the frame period from the reference detection signal SD To judge. When it is determined in step n18 that the predetermined value is reached,
Step as if detecting a legitimate frame sync signal
Moving to n19, reproduction of the frame synchronization signal FC ′ is started and then moving to step n20. In step 20, 1-byte parallel data is fetched, deinterleaved, and written in the memory 13 so as to obtain a code string before interleaving. Then, the process goes to step n21 to reset the divided clock counter. When it is determined in step n18 that the predetermined value is not reached, the process proceeds to step n21.

Frame synchronization is established in step n3,
That is, when it is determined that the reproduction of the frame synchronization signal FC 'has started, the process proceeds to step n4, and it is determined whether or not the detection signal SD is output. If not, the process proceeds to step n5 and the detection signal SD 1 is added to the count value of the built-in non-coincidence counter that counts the number of times that is not output.

In step n6, whether or not the count value of the mismatch counter reaches a preset predetermined value, that is, after the reproduction of the frame synchronization signal FC ′ is started, the detection signal SD is continuously output a predetermined number of times in the frame cycle. If it is determined that the predetermined value has been reached, another frame reference signal FC serving as another reference must be searched for and set again.
Stop playing. Then, the process shifts to step n8 to disable the interrupt by the divided clock, and further enables the interrupt by the detection signal SD in step n9. Therefore, in this case, the third detection signal SD described above is input by inputting another detection signal SD.
The process moves to the interrupt process shown in the figure.

If it is determined in step n6 that the count value of the mismatch counter has not reached the predetermined value, the process proceeds to step n14, in which 1-byte parallel data is fetched, deinterleaved in 4-bit units, and written in the memory 13. Then, the process goes to step n15 to reset the divided clock counter.

When the detection signal is output in step n4, the mismatch counter is reset in step n13, and then the process proceeds to step n14, in which 1-byte parallel data is fetched, deinterleaved in units of 4 bits, and written in the memory 13. Then move to step n15,
Reset the divided clock counter.

If it is determined in step n2 that it is not during the frame synchronization signal transmission period, the process proceeds to step n10 to determine whether frame synchronization has been established.If frame synchronization has not been established, an interrupt by the divided clock CLK ′ is not generated. The process ends and waits for an interrupt by the next divided clock CLK '. On the other hand, when the frame synchronization is established, the process shifts to step n11, 1 byte of parallel data is taken in, deinterleaved in units of 4 bits and written in the memory 13, and the interrupt by the divided clock CLK 'is completed. , Wait for the interrupt by the next divided clock CLK ′.

As described above, according to the present example, the reproduction, protection and deinterleave processing of the frame synchronization signal FC 'are performed by the processing of the microprocessor 40.
The circuit configuration can be simplified as compared with a hardware configuration as shown in the example. In contrast to the processing by hardware, the processing by the microprocessor
The processing content can be easily changed by changing the software. This is a flexible and highly expandable system in addition to the fact that the present embodiment transmits facsimile data by packet format digital transmission using a satellite television broadcasting communication channel.
Further, if the digital signal processing on the transmitting side is software processing by a microprocessor, the entire system including the transmitting side and the receiving side can be made extremely flexible and highly expandable.

In the embodiment described above, the frequency dividing circuit 50 for dividing the clock CLK and the serial / parallel conversion circuit 60 are provided. However, the frequency dividing circuit 50 and the conversion circuit 60 are not limited to the processing time of the microprocessor 40. It is provided in consideration. Therefore, the frequency dividing circuit 50 and the converting circuit 60 may be omitted depending on the processing time of the microprocessor 40 and the number of data buses.

[Effects of the Invention] As described above, according to the present invention, since the reproduction, protection and deinterleave processing of the frame synchronization signal are performed by the microprocessor processing, the hard counter, the gate circuit and the deinterleave circuit as in the conventional example. An external circuit such as is unnecessary, and the circuit configuration can be greatly simplified. In the microprocessor processing, the processing content can be easily changed by changing the software. Therefore, in addition to transmitting facsimile data by packet-type digital transmission using a satellite television broadcasting communication path, a flexible and highly expandable system can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a functional block diagram of a microprocessor, FIG. 3 and FIG.
FIG. 7 is a flow chart for explaining the operation of the microprocessor, FIGS. 5 and 6 are configuration diagrams of a communication system using a communication satellite, FIG. 7 is a diagram showing a frame configuration of a facsimile signal, and FIG. 8 is type information recording. FIG. 9 is a configuration diagram of the apparatus, FIG. 9 is a configuration diagram of a main part of a data capturing section, and FIG. 10 is a configuration diagram of a frame synchronization signal reproducing circuit. 1 ... Data capture unit 13 ... Memory 20 ... Frame sync signal pattern detection circuit 40 ... Microprocessor 50 ... Dividing circuit 307 ... Type information recording device 401 ... Counting means 402 ... Discriminating means 403 ... ... output means 404 ... protection means 405 ... setting means 406 ... deinterleave processing means

Claims (1)

(57) [Claims] 1. A facsimile broadcast for time-division-multiplexing digital facsimile information with PCM voice information by using a communication path for transmitting voice by PCM in satellite television broadcast, and interleave processing for transmission. In the facsimile receiving apparatus, a clock generation circuit that generates a clock that is a reference for digital signal processing in synchronization with received data, and a frame that indicates the beginning of a frame that is an information transmission unit from the received data in synchronization with this clock A frame synchronization signal pattern detection circuit that detects a synchronization signal and outputs a detection signal, and a microprocessor that reproduces the frame synchronization signal in synchronization with the clock based on the detection signal are provided. The signal is given as a reference signal, and in response thereto, the clock is counted. And a determining means for sequentially determining, for each frame cycle, whether or not the detection signal is output in the frame cycle from the time when the reference signal is given, based on the count value of the counting means. When the output of the detection signal is continued for a predetermined number of times in a frame period from the time when the reference signal is given, based on the output of the determination means, the detection signal is detected. Output means for reproducing a frame synchronization signal synchronized with, and based on the output of the determining means, only when the detection signal is not output a predetermined number of times in a frame period after the frame synchronization signal is reproduced. Based on the protection means for stopping the reproduction of the frame synchronization signal and the output of the discrimination means, before the frame synchronization signal is reproduced, the frame frequency is changed from the reference signal. When the output of the detection signal is not output for a predetermined number of times in the frame period after the detection signal is not output in the above, and when the frame synchronization signal is reproduced, a signal different from that given as the reference signal is output. Setting means for giving the detection signal as a reference signal to the counting means to newly set the reference signal, and deinterleaving processing by fetching the received data while the frame synchronizing signal is being reproduced by the output means. And a de-interleave processing means for performing the above.