MXPA95002546A - Synchronized exploration circuit - Google Patents

Abstract

The present invention relates to a synchronization circuit, comprising: a synchronization input signal source at an input frequency, an oscillator for providing an output signal at an output frequency that is an integral, greater multiple of the input frequency, means responsive to the input signal and a feedback signal representative of the output signal to generate a control signal that is indicative of a difference in phase or frequency between the input and output signals, the oscillator which responds to the control signal for synchronized track tracking of the output signal of the oscillator with respect to the input signal, the control signal presenting a periodic variation that tends to result in a deviation of the output signal of the oscillator from its synchronized track condition according to the periodic variation, and means coupled to the oscillator to offset one phase of the s output signal in relation to the corresponding phase of the periodic variation of the control signal to counteract said deviation

Description

SYNCHRONIZED EXPLORATION CIRCUIT The invention relates to securing the phase of a controlled voltage oscillator with respect to a synchronization input signal. The recurrent scanning circuits of the television receivers are synchronized with respect to the synchronization or sync component of the received video signal, which includes the horizontal and vertical synchronization components that delineate horizontal lines and vertical fields. The NTSC standard video signal, for example, is defined by two successive fields of 262.5 horizontal lines each, at a horizontal line frequency of 15.734 Hz, designated as fH or lfH or ÍH. The horizontal lines of the two fields are interleaved by successive deployment to form a complete 525-line video frame that uses a speed of 29.97 Hz. Efforts to improve the image quality of television receivers have included the development of the visual display systems explored progressively or without interlacing, in which a complete frame of 525 lines is deployed during the time allocated to one of 262.5 lines per field in the video signal. This requires that horizontal lines be scanned at a display frequency equal to twice the video signal frequency, or 2fH, while sync is operated with the video signal. It is necessary for a television receiver of this type to generate a horizontal trigger signal at a display frequency that is twice the original frequency of the video signal, effectively inserting horizontal trigger pulses precisely between the pulses obtained from the signal of sync entry. Similarly, one can display a video signal of lfH, at some other multiple of the video signal frequency. For example, a video signal of lfH or 2fH can be displayed at a display scanning frequency of 4fH, or another multiple can be used. A circuit for generating a deployment frequency signal conveniently involves a secured phase cycle of multiplication that tracks the synchronization component of the received input signal. In an assured multiply phase cycle, for example, to develop the secured horizontal trigger signals with respect to a received video signal, a voltage oscillator controlled at a frequency which is some multiple of the input signal is normally operated. The output of the controlled voltage oscillator is counted upside down by that multiple, in other words, lfH, for example, using one or more counters or flip-flops as a frequency divider. The countdown of the signal lfH from the frequency divider is fed back to a phase comparator that responds to the synchronization component of the video signal and generates an output voltage as a function of the phase alignment and between the synchronization component of the video signal and the oscillator. The output of the phase comparator provides a tuning voltage for controlling the frequency of the oscillator, allowing the television receiver to search and secure for the synchronization component of the video signal. Assuming that the input video signal is stable, the phase comparator generates a tuning voltage when the cycle is secured, where the average or direct current component of the tuning voltage is stable. The tuning voltage, however, may vary periodically at the speed of the synchronization signal, for example, on a ramp or in the manner of a sawtooth, depending on the circuit used to filter the tuning voltage. The sawtooth modulates the output frequency of the oscillator during the period of the synchronization of the input signal, even when the countdown of the signal lfH is correctly maintained in the phase with the video synchronization signal. A trigger signal can be generated from that circuit at a multiple of the lfH signal by touching lightly to a point in the frequency divider chain that produces an output at a higher frequency than the lfH feedback signal that is the basis of assured phase control. Inconveniently, The pulses at that higher frequency do not occur symmetrically between the pulses at the controlled lfH frequency due to the sawtooth modulation of the oscillator frequency introduced by the alternating current component of the tuning voltage. The effect of these periodic variations on the oscillator frequency can be seen in relation to an example where the controlled voltage oscillator operates at 32fH. The output of the oscillator is divided by its frequency by 32 to produce a feedback signal of lfH for the phase comparator. The frequency of the oscillator is divided by 16 to provide a 2fH signal for the controller deflection circuit used for horizontal scanning without interlacing. When the output frequency of 32fH varies during a lfH cycle due to a modulation of the tuning voltage, the horizontal lines alternated to 2fH will be of an unequal length. A tearing effect occurs in the display because the alternate lines are of different lengths and are not aligned vertically. The resonance effects of the deflection circuit tends to increase this tearing effect, which is very inconvenient in a non-interlaced display. The output of the phase comparator is normally coupled to the oscillator through a low pass filter which can reduce the amount at which the output frequency of the oscillator is modulated at a speed of lfH. However, excessive filtering reduces the response and the ability to keep track of the assured phase cycle. Additionally, a plurality of phase locked cycles can be cascaded, wherein a first phase cycle ensures a 2fH trigger signal is generated from the synchronization input signal and a second phase assured cycle associated with the deflection circuit synchronizes the scan with the generated 2fH trigger signal. However, there are conflicting requirements in the two assured phase cycles, and sufficient attenuation of the lfH component can not be achieved without sacrificing some other system parameter. Figure 1 is a schematic block diagram showing the elements of the synchronization circuit of the invention as applied to a television receiver. Figures 2 (a) and 2 (b) are timed diagrams comparing video synchronization and horizontal scanning trigger signals in a non-interlaced display television receiver. Figures 3 (a) to 3 (h) are timed diagrams comparing the horizontal synchronization signal, the tuning voltage, the oscillator output and the trigger signals developed by the circuit of Figure 1.

Figure 4 is a visual display diagram showing a recurring divider effect. Figures 5 (a) and 5 (b) are frequency spectra, respectively, illustrative of the signals as shown in Figure 3 (d), and how it is corrected according to a feature of the invention. Figure 6 is a detailed circuit diagram showing an exemplary circuit for biasing the phase of the 2fH trigger signal in relation to the video synchronization signal. Figure 7 is a logic table showing the output of the circuit according to Figure 6. Figure 8 is a block diagram illustrating a delay alignment circuit for resetting the phase of the 2fH trigger signal. Figure 9 is a block diagram illustrating a first configuration of the invention of a synchronization circuit, with a first delay in a feedback path and a second delay in an output. Figure 10 is a block diagram showing a second configuration of the invention having a delay in a feedback path leading to a frequency divider. Figure 11 is a block diagram showing a third configuration of the invention that includes the combination of a low pass filter and a delay. Figures 12 (a) to 12 (f) are timed diagrams comparing the horizontal synchronization signal, the tuning voltage, the oscillator output and the trigger signals developed by the circuits of Figures 9 and 10. In a circuit of In synchronization, an oscillator provides an output signal at a frequency that is an integral multiple greater than that of the synchronization input signal. A control circuit, responsible for the input signal and a feedback signal representative of the output signal, generates a control signal that is indicative of a difference in phase or frequency between the input and output signals. The oscillator responds to the control signal for tracking the synchronized track of the output signal with respect to the input signal. The control signal has a periodic variation that tends to result in a deviation of the oscillator output signal from its synchronized track tracking condition according to the periodic variation. The phase of the output signal is deviated in relation to the corresponding phase of the periodic variation • of the control signal to counteract this deviation. Figure 1 illustrates a synchronization circuit 22, especially for a television receiver, in accordance with an exemplary embodiment of the invention. The synchronization circuit 22 includes a first secured phase cycle 24 responsive to a synchronization input signal 26 at a frequency sync, and a second secured phase cycle 54 that responds to an output 167 from the first secured phase cycle 24 The synchronization input signal 26 may be the horizontal scan or sync component of a standard video signal, resorting to a frequency of lfH. In order to provide a non-interlace scan, the synchronization circuit 22 develops a trigger output 32 at a multiple of the input sync frequency, for example at twice the frequency sync, or at a frequency of 2fH. For this purpose, a controllable oscillator 34 or VCO generates an output signal to a first, relatively high, multiple of the frequency sync, such as 32fH. At least one divider 42 counts down the output of oscillator 34 over a splitter period to provide a trigger signal at a multiple other than the frequency sync, such as 2fH in the example shown. Other specific multiples of the sync frequency can be used to scan or for other purposes in the television receiver. +++ Two frequency dividers 42, 44 are provided in the illustrated mode. A selectable phase divider 42 has a chargeable counter 74 that divides by 16 to develop a 2fH signal from an output of the 32fH oscillator 34. The other divider 44 divides by 32 by means of a counter 72, to provide a signal 48 of lfH which is fed back for phase co-operation with the input signal 26 in the assured phase cycle 24. The output signal 32 to 2fH is coupled to the deflection circuit 52 of the television receiver, example, providing a trigger or reference signal for the second assured phase cycle 54, associated with the rewinding of the horizontal deflection and the transformer and the return transformer, not shown, of the television receiver. The synchronization input signal 26 and the ensured feedback phase signal 48 developed by dividing the output frequency of the oscillator 36, provides the inputs to a phase comparator 58 operable to compare the secured phase signal 48 and the synchronization signal. 26. The secured phase cycle 24 produces a tuning voltage 62 having an average value representing the amount of alignment of the two-input phase. The phase comparator 58 and the filter 68 generate an output waveform shown in Figure 3 (b), with a periodic component at the frequency sync, and a direct current component or average value 65. If the two signals of input 26, 48 remain aligned in phase and frequency, direct current component 65 remains constant. If one or the other of the signals 26, 48 advances or is delayed with respect to the other in phase or frequency, the DC component 65 changes. The tuning voltage of the phase comparator 62 is generated by means of a filter 68 having a transfer function G (s), generally a low pass function, to provide control of the oscillator 34. In this way, the cycle of insured phase 24 seeks and maintains a lock or a track of the oscillator frequency and of the phase with input synchronization signal 26. Frequency dividers 42, 44 each have a period of division by which they have cycles repetitively . The divisor 42 that divides by 16 has a binary counter 74 of 4 bits. The frequency divider 44 that divides between 32 includes a 5-bit binary counter 72. The counter which divides by 32 is synchronized to an input signal 26 of lfH by the action of a phase comparator 58 and an oscillator 31, but the divider 74 between 16 must be adjusted in order to ensure that the division cycles of the two counters begin in the same period of oscillator 36 of 32fH. This adjustment must be carried out by coupling the output of lfH of the counter 72 which divides between 32 with the counter 74, or by directly connecting the line 49 of lfH and the trigger line 152 of the pre-adjusted counter in Figure 1. The period of division of the counter 74 then begins in the same period 32fH as the division period of the counter 72, although the counter 74 that divides by 16 has cycles over two division periods for each division period of the counter 72 that divides by 32 This can lead to the modulation problem of lfH that was mentioned above. In carrying out a feature of the invention, the counter 74 can be charged in parallel, and a phase deviation circuit 142 is provided to divert the phase of the division period of the counter 74 that divides by 16 and thus adjust the phase of the 2fH period used to develop the trigger signal 32, relative to a synchronization signal phase 26. This is convenient for eliminating the modulation of the 2fH countdown output 32 of the synchronization circuit 22, at an input frequency of lfH. The output signal 32 is then adjusted by a delay alignment block 160 to provide a driving signal 167 with the correct phase relationship with respect to the original sync output 26. The driving signal 167 of 2fH is used as the synchronization input for the next secured phase cycle 54. The secured phase cycle 54 is conventional and includes a phase comparator 258, a low pass filter 268, a controlled oscillator 234 for driving the deflection circuit 52, and a return of 2fH feedback for the phase comparator 258 from the deflection circuit 52. An additional delay block 264 can be inserted in the feedback signal, for example, to adjust the phase to center the horizontal image. The operation of the synchronization circuit 22 can be seen from the timed diagrams of Figures 2 (a), 2 (b) and 3 (a) through 3 (h). A standard video signal arranged for the interlaced video fields containing the first and second successive fields during the successive vertical intervals. In Figure 2 (a), any other horizontal line m, m + 2 is transmitted between the pulses of lfH over the synchronization input signal 26, and the fields of odd or even number lines interspersed in successive displays during the periods alternating verticals, to provide a complete framework. For non-interlaced scanning, however, the horizontal scanning speed must be twice as fast as the horizontal sync video speed, as illustrated in FIG. 2 (b) by the driving signal 167. As shown in FIGS. Figures 2 (a) and 2 (b), the pulses of lfH and the pulses of 2fH are aligned. These signals are idealized, and may only be appropriate in a particular mode to bypass the phase of the 2fH signal relative to the input of lfH, for example, as an element to horizontally center the video in the display. The horizontal trigger pulses for the deflection circuit must be separated with the same interval between pulses. However, the phase comparator 58 produces a tuning voltage 62, illustrated in Figure 3 (b) which periodically varies at a rate of lfH about an average value 65. The filter 68 can reduce the periodic component generated by the operation of the phase comparator, but will not normally completely remove the periodic component. Moreover, excessive filtering could inconveniently change the response of the assured phase cycle. The tuning voltage 62 thus causes a periodic variation of lfH in the pulse amplitude of the oscillator output 36, shown in an exaggerated manner in Figure 3 (c). The pulses 102 at the output 36 of the oscillator 34, for example, are wider than the average pulse amplitude over a period of lfH, when the tuning voltage 62 is relatively greater than its average 65. The pulses 104 that occur when the Tuning voltage 62 is relatively lower than average, they are narrower. The variation does not adversely affect the period of the counter 72 that divides by 32, which operates to maintain the phase locked cycle 24 in sync with the sync input signal 26 to lfH, because over the period of the signal 26 the average of the longest and shortest pulses are around the 32 cycles. If the counter 74 that divides by 16 will be operated at 15 to bypass the phase of the frequency division period that divides by 16 relative to a synchronization input signal phase 26. More particularly, the division period between 16 during the which the counter 74 counts by means of a division cycle is changed in relation to the signals 26, 48, of lfH and in relation to the division period of the counter which divides by 32, which is synchronized by the operation of the phase cycle secured 24 with respect to the input signal 26. The amount of this change is sufficient to move the dividing period dividing by 16 relative to signals 26, 48 of lfH to a point where some 102 longer pulses of 32fH and some shorter pulses 104 of 32fH fall within each division period, so that the successive 2fH division periods are substantially equal in time, as shown by the signal l of output 32 in Figure 3 (e). In other words, the division period of 2fH is changed sufficiently, with respect to the tuning voltage 62 and the feedback signal 48, so that the average value of the tuning voltage 62 around its zero voltage line of alternating current 65, is the same during each successive counting cycle that divides between 16 or division period. In Figures 3a-3h, this phase or time change is represented by the interval tl-t2. The extent of the phase change of the period 16 divided by 16 relative to the period of lfH can be adjusted to a predetermined count number of cycles of 32fH. This number is selected to obtain the optimal phase relationship between the period of dividing by 16 and the synchronization signal period of lfH. As shown in Figure 5 (b), we found the selection of the phase with respect to the 32fH period or count that is closer to the optimal phase to reduce the lfH modulation of the frequency of the horizontal triggers of 2fH in as much as 18dB. Figure 1 together with Figure 6-8 illustrate an embodiment of the invention wherein the phase of the division periods of the counter 74 dividing by 16 of can be changed by a specific account number of 32fH cycles in relation to the division period of the counter 72 that divides by 32, and with respect to the input sync signal 26. The phase shift circuit 142 includes a timing circuit 110 coupled between the LFH signal 49 from the counter 72 and a preselected input 152 of the counter 74 which divides by 16. The phase deflection circuit 142 provides an account at which the counter 74 that divides by 16 produces an output pulse on the trigger signal 32 of 2fH, thereby determining the phase of the division cycle. In the embodiment shown, the count is established from an output of a microprocessor or controller 115 of the television receiver, by means of a timed circuit 110, for example, by preloading an account in the counter 74 that divides by 16 into a end of the signal of lfH. The counter 74 then begins to cycle through two split periods or two 16-count progressions until it is reloaded again. Any particular account is capable of being pre-loaded as necessary to obtain the desired phase change of the 2fH signal, up to a resolution of one part in 16. The counter 74 that divides by 16 is thus reset with each cycle of the signal of lfH, keeping the counter 74 in sync with the counter -72, and, at the same time, the output signal 32 of 2fH becomes symmetric due to the phase change. The use of the microprocessor 115 to set the pre-charged account is only an alternative. Computer equipment bridges, circuit switches or other elements are also possible means for providing a phase selection input 132 for the inputs 153 of the counter 74. Figure 6 shows a phase shift circuit 142 in greater detail, to divert the phase of the division period of 2fH in relation to. a phase of synchronization signals 26 or 48, so that the average value of the tuning voltage 62 is equal during the successive periods of output signals 32 of 2fH. The timing circuit 110 is synchronous with the signal of 32fH and preload 18 the counter 74 during each cycle of lfH. The output signal 36 of the oscillator at 32fH is coupled by means of an inverter, controller 117 to the clock inputs of two cascaded D-flipflops 121, 123 and to the four-bit clock input of the binary counter 74. The counter 74 is loaded in parallel or prefixed by the microprocessor 115 on a four-bit bus 132, coupled to the parallel input 153 of the counter 74. A serial bus configuration is an alternative possibility, not illustrated. The input D of the first flipflop 121 is coupled by means of an inverter 119 to the feedback signal 49 input signal to lfH, so that the change of state in the frequency of lfH appears on the output of flipflop 121 in the next period of the signal of 32fH, and is coupled to the input D of the following flipflop 123 in cascade. The output of the second flipflop 123 is coupled to an input of a NAND gate 134, whose other input is coupled to the D input of the flipflop by means of an inverter 136. In the count 32fl, the output of the counter 72 which divides by 32 goes high, shown as the signal 49 in Figures 3 (h and 6, and the input to the first flipflop 121 goes low, as does the output of the NAND gate 134 a later count.Binary counter 74 is then loaded from the bus 132 with a pre-selected start count The signal 49 of lfH does not change the state for a number of 32fH cycles, but the counter 74 during each cycle of lfH.The output signal 36 of the oscillator at 32fH is coupled by means of an inverter , controller 117 to the clock inputs of two cascaded flipflops-D, 121, 123 and to the four-bit clock input of binary counter 74. Counter 74 is loaded in parallel or pre-set by microprocessor 115 on a four-bus. bits 132, coupled to the parallel input 153 of the counter 74. A serial bus configuration is an alternative possibility, not illustrated. The input D of the first flipflop 121 is coupled via an inverter 119 to the feedback synchronization input signal 49 to lfH, so that the state change in the frequency of lfH appears on the output of the flipflop 121 in the period next of the 32fH signal, and is coupled to the D input of the next cascaded flipflop 123. The output of the second flipflop 123 is coupled to an input of a NAND gate 134, whose other input is coupled to the D input of the flipflop by means of an inverter 136. In the count 32a, the output of the counter 72 that divides by 32 goes high, shown as the signal 49 in Figures 3 (h) and 6, and the entry to the first flipflop 121 goes low, as does the output of the NAND gate 134 one count later. The binary counter 74 is then loaded from the bus 132 with a pre-selected start account. Signal 49 of lfH does not change the state for a number of 32fH cycles, but the charge signal of the counter goes higher after a 32fH clock cycle, allowing the binary counter 74 to count pulses of 32fH from the voltage oscillator checked. The counter 74 counts 32 pulses, that is to say through two division periods at 2fH, until it is reloaded again at the next start end of the signal 49 of lfH. The binary counter 74 operates as the counter that divides by 16 according to this mode. The four outputs of the binary counter 74 are coupled as inputs to a gate circuit 143 which provides a pulse output for at least one, but usually a series of clock cycles adjacent to 32fH. The gate circuit 143 includes a NAND gate 144 and a NOR gate 148, the outputs of which are coupled to an additional NAND gate 154. In addition to providing an output at a speed of 2fH or dividing by 16 from the counted 32fH output of the oscillator 34, the gate circuit 143 provides an output pulse of 2fH which is low for 3 clock cycles of 32fH during each period of 2fH. This pulse amplitude is obtained due to the logical arrangement shown in the table of Figure 7. The binary counter 74 can be charged to any 4-bit number and also to cycles continuously. By choosing the start count loaded within the binary counter 74 from bus 132, the position of the low cycle phase during each 2fH period can be placed anywhere from the 16 count positions to 32fH occurring during the period of division of 2fH. As part of a set function of the television receiver, a desired phase deviation for the timed end of the output signal 32 of 2fH is selected relative to the timed end of the synchronization signal 26, so that the average value of the tuning voltage 62 is equal in the. successive periods of 2fH of the trigger signal 32. It is allowed to vary in amplitude the individual 32fH pulses of the oscillator 34, but the division periods of 2fH are equal in time because the longer and shorter pulses 102, 104 are distributed more or less equally in successive periods, instead of long pulses being counted predominantly during one period and short pulses predominantly during the next. As a result, the duration of each successive period of 2fH is substantially the same. As shown in Figure 5 (b), the frequency spectrum of the output signal 32 is substantially corrected for the inconvenient modulation. Although the modulation at the frequency of lfH is eliminated as explained above, the phase position of the transitions on the signal 32 of 2fH has shifted relative to the period of lfH. This may be convenient for maintaining a particular phase relationship between the 2fH signal and the synchronization input signal, for example, with the 2fH pulses aligned with the lfH signal, so that the deflection circuit 52 coupled to the second Secured phase cycle 54 operates at the step with the synchronization input signal 26. According to another characteristic of the invention, the phase relationship of the output signal 32 of 2fH is adjustable with respect to the synchronization input signal 26 by a delay alignment circuit 160, as generally shown in Figure 1 and in a specific embodiment in Figure 8. In Figure 8, the delay is established in a coordinated manner with the establishment of the pre-charged account in the counter 74 using, for example, the same four-bit data signal coupled as the inputs 153 to the counter 74. The delay alignment circuit 160 comprises two monostable 164, 166 in cascade. The first monostable 164 controls the change of time or delay between the ends of the output signal 32 of 2fH and the driving signal 167 of 2fH which is supplied to the second secured phase cycle 54. The second monostable 166 controls the amplitude of the signals. pulses of the driving signal 167. The monostable 164 provides a selectable delay, for example, controlled by the microprocessor 115 by means of the timing circuit 110 in Figure 1. The extension of the delay can be chosen as an established function to coordinate with the number of cycles of 32fH by which the trigger output signal 32 is changed by a preset binary counter 74. For example, the adjustable delay of the monostable 164 is set to compensate for the change in the image due to the delay introduced in the divider 42. The pulse amplitude of the monostable 164 is determined by the time constant of a capacitor Cl and one of the resistors selected from Rl-Rn, coupled to the monostable 164 by means of a switching matrix 165. In the example shown, one of the 16 resistors Rl-Rn is selected by a 4-bit input from the timing circuit 110. The amplitude of the pulse of the monostable 166 is set by the values of the capacitor C2 and a resistor Ra, to an amplitude that is suitable for use in the second secured phase cycle 54. In the secured phase cycle multiplier 24, as shown and described, the output signal 32 and the driving signal 167 are generated in a first multiple of the 26 sync received video signal. The controlled voltage oscillator 34 provides the clock signals 36 to a second multiple of the received signal frequency which is greater than the first multiple. By inserting a phase change for the dividing period of the divider 74 to obtain the phase alignment described, the modulation of the output signal 32 is avoided. The phase of the driving signal 167 is then corrected to the required driving phase. Figures 1 and 9-11, represent alternative configurations of the invention in which the delay circuits and the frequency dividers are coupled in different arrangements in relation to each other and in relation to the low pass filter and the oscillator. Figures 12 (a) -12 (f) show the timed AF signals at the labeled points of Figures 9 and 10, comparable to Figures 3 (a) -3 (h) and Figure 1. In Figures 9 and 10, the phase locked cycles 210, 220 each have a phase comparator 201, a low pass filter 202 and VCO 203, coupled in series to a sync signal D of lfH, with a feedback path for the comparator of phase 201 including a frequency divider 204 and a delay 205 necessary to ensure the symmetric output of the oscillator. Conveniently, VCO 203 operates at the same frequency as the scanning circuit, not shown, and produces a symmetrical 2fH driving signal, synchronized with the sync signal D of lfH. The output E of the phase comparator 201 is coupled to a low-pass filter 202, whose output F is the control signal or the tuning voltage for VCO 203. The output A of VCO 203 in each case is a symmetric signal of 2fH where the durations of the alternate cycles, ta-tb and tb-tc, are equal. In Figure 9, the delay alignment block 206 adjusts the output A to achieve the pulse phase necessary to control the additional circuits such as the second assured phase cycle 54 of Figure 1. Figures 9-11 use the same reference numbers to identify the corresponding circuit elements. The circuit of the invention in Figure 10 provides the same delay and feedback functions in a secured phase cycle 220 of 2fH, but requires only one delay, i.e., the delay 205 inserted in the feedback path. By placing the delay 205 upstream of the frequency divider 204, the output signal coupled to the second phase locked phase circuit 54 corrects the phase, and at the same time the feedback signal B2 can be adjusted appropriately in the phase relative to the output A of VCO 203, to obtain a symmetric operation of the oscillator. As shown in FIGS. 12 (a) -12 (f) the VCO signal 203 is in each case symmetric, but is out of phase, for example, the interval tc-td, with the synchronization input D and with the tuning voltage F for VCO 203. In Figures 9 and 12 (d), the feedback signal B to lfH is out of phase with the synchronization input D. In Figures 10 and 12 (e), the feedback signal B2 is not only symmetric, but is in phase with the synchronization input D. The frequency divider 204 then divides the oscillator frequency for input to the phase comparator 201. By operating VCO 203 out of phase with the signals C or B2 throughout the feedback loop, both circuits provide a symmetric 2fH signal, or is, without modulation of lfH, and both circuits provide a phase comparison signal C for the phase comparator 201 that keeps the circuit insured. A further configuration of the invention, as shown in the secured phase cycle 230 of Figure 11, provides a delay in the path of the tuning voltage or the control signal F in place of the feedback path, to operate the VCO with a symmetrical output. In Figure 11, the analog delay 207 is coupled to the output of the low pass filter 202 for this purpose. The low-pass and delay functions can, for example, be produced in a simple analog circuit with a multi-pin transfer function. In all the configurations of the invention shown, the phase locked cycle generates a tuning voltage of the oscillator control signal which is indicative of the difference in phase or frequency between the horizontal sync input signal of lfH and the output signal of the oscillator, wherein the frequency of the output signal is an integral multiple greater than the input signal frequency. The phase detector generates a tuning voltage, even after filtering, which has a periodic variation, that is, at a speed of lfH. The tuning voltage, when applied to the input of the oscillator control, tends to produce a deviation of the output signal of the oscillator from its synchronized track condition, that is, from its average period. Thus, the cyclic variation of lfH in the tuning voltage produces a variation of lfH from the average period of the oscillator output of 2fH. This variation could occur for other oscillators that provide the scanning pulse at other major multiples of the synchronization input signal. Due to the frequency control provided by the assured phase cycle, the average period of the oscillator output is still in the average period of the input sync signal. By controlling the phase of the output signal of the oscillator relative to the phase of the periodic variation in the voltage of the tuner, the deviation of the output of the oscillator is counteracted. In Figure 1, this is accomplished by directly deviating the phase of the 2fH output signal by selecting the appropriate 32fH cycle of VCO 34 from which the divider 42 begins its countdown. In Figures 9 and 10, the deviation of the oscillator is counteracted by deviating the phase of the feedback signal from the oscillator, and in Figure 11, directly deriving the phase from the tuning voltage produced by the phase detector 201.

Claims (36)

NOVELTY OF THE INVENTION Having described the foregoing invention, it is considered as a novelty and, therefore, the content of the following is claimed as property CLAIMS

1. A synchronization circuit, which includes: a synchronization input signal source (SYNC) at an input frequency; an oscillator (34 or 203) for providing an output signal at an output frequency that is an integral, greater multiple of the input frequency; characterized by elements (24 or 210 or 220 or 230) that respond to the input signal and a feedback signal representative of the output signal to generate a control signal that is indicative of a difference in phase or frequency between the signals of input and output, the oscillator being responsible for the control signal for synchronized track tracking of the output signal of the oscillator with respect to the input signal, the control signal presenting a periodic variation tending to result in a deviation of the output signal of the oscillator from its synchronized track condition according to the periodic variation; and the elements (142 or 204, 205 or 204, 208) coupled to the oscillator to derive a phase of the output signal relative to the corresponding phase of the periodic variation of the control signal to counteract that deviation.

2. A circuit, according to claim 1, characterized in that the phase shunt element includes a frequency divider (204) coupled to a time change circuit (205) in a path of signal generation of output, the feedback signal being developed at an output (B2) of the time change circuit.

3. A circuit, according to claim 1, characterized in that the deviation of the output signal of the oscillator produces a variation of a period of the output signal according to the periodic variation of the control signal.

4. A circuit, according to claim 3, characterized in that the average period of the output signal remains unaffected by the periodic variation of the control signal and tracks the average period of the input signal of synchronization.

5. A circuit, according to claim 1, further characterized by a scanning circuit (52) driven by the output signal at a higher frequency than the input signal but synchronized therewith.

6. A circuit, according to claim 1, characterized in that the phase deflection element includes a frequency divider (204) coupled to a time change circuit (205) in a path of the feedback signal. .

7. A circuit, according to claim 6, characterized in that the output signal is obtained at an output (B2) of the time change circuit.

8. A circuit, according to claim 1, characterized in that the periodic variation of the control signal occurs at the input frequency.

9. A circuit, according to claim 1, characterized in that the oscillator (34 or 203) develops an oscillatory signal at an oscillatory frequency greater than the output frequency and that is an integral multiple of the input frequency, and includes a divider (42 or 204) that responds to the oscillatory signal to generate the output signal.

10. A circuit, according to claim 9, characterized in that the phase deflection element (142) includes elements (110) to deflect a phase of a divider division period in relation to a phase of the synchronization input signal.

A circuit, according to claim 10, further characterized by elements (160) for changing a phase of the output signal to compensate for a phase deviation generated by the phase deflection element.

12. A circuit, according to claim 11, further characterized by a scan circuit (52) driven by the output signal phase changed to a higher frequency than the input signal but synchronized with it.

13. A circuit, according to claim 1, further characterized by a scanning circuit (52) for a video display that responds to the output signal of the oscillator and has a scan interval established for the period of the output signal and subject to its variation.

14. A synchronization circuit, which includes: a source of a synchronization input signal (SYNC) at an input frequency; an oscillator (34 or 203) for providing an output signal at an output frequency that is higher, integral multiple of an input frequency; characterized by the element (24 or 210 or 220 or 230) that responds to the input signal and a feedback signal representative of the output signal to generate a control signal that is indicative of a difference in phase or frequency between the input and output signals, the oscillator being responsible for the control signal for tracking the synchronized track of the output signal of the oscillator with respect to the input signal, the control signal presenting a periodic variation that tends to give as resulting in a deviation of the oscillator output signal from its synchronized track condition according to the periodic variation; and the elements (142 or 204, 205 or 204, 208) coupled to the control signal that generates elements to deflect a phase of the feedback signal relative to a corresponding phase of the output signal and counteract that deviation.

15. A circuit, according to claim 14, characterized in that the deviation of the output signal of the oscillator includes a variation of a period of the output signal around an average period.

16. A synchronization circuit responsive to a synchronization signal at a sync frequency, which includes: a controllable oscillator (34) for generating an oscillatory signal at a first frequency multiple sync; at least one divider (42) for the countdown of the oscillatory signal over a period of division, to provide an output signal to a second multiple of the frequency sync; a phase comparator (58) operable to compare an oscillator output and a synchronization signal to produce a tuning signal coupled to the oscillator to synchronize the output signal with the synchronization signal; characterized by: the element (142) for deflecting a phase of the division period in relation to a phase of the synchronization signal.

The circuit, according to claim 16, characterized in that the tuning signal has a periodic component at the frequency sync, and wherein the phase shunt element provides a phase shunt which reduces a periodic component of the same frequency in the output signal.

18. The circuit, according to claim 17, characterized in that the phase shunt element provides a phase shunt such that the output signal has successive periods of substantially equal duration.

19. The circuit, according to claim 16, further characterized by the element (160) for changing a phase of the output signal to obtain a predetermined phase alignment with the synchronization signal.

20. The circuit, according to claim 19, characterized in that the phase change element includes a monostable (164, 166).

21. The circuit, according to claim 16, characterized in that the divider includes a digital counter (74) and the phase bypass element includes the element (121, 123, 136, 134, 152, 143) for at least one of the predefined or predetermined initial accounts of the counter and trigger an output to a predetermined counter account.

22. The circuit, according to claim 21, further characterized by the element (115) for selecting the predetermined count, so that the phase of the division period can be selected in relation to the phase of the signal of synchronization, to set the average value of the substantially equal tuning signal during successive periods of the trigger signal.

23. The circuit, according to claim 16, characterized in that the divider (42) includes a first digital counter. (74) operable to count the first multiple of the frequency sync backwards with respect to the second multiple of the frequency sync and which further includes a second counter (72) operable for the countdown of the frequency sync.

24. The circuit, in accordance with claim 23, characterized in that the phase shifter element (142) includes the element (121, 123, 136, 134, 152) for charging the first digital counter (74) to a pre-determined account. established

25. The circuit, according to claim 24, characterized in that the first digital counter (74) is fed with a load signal (a 152) so that the first digital counter is charged to the preset count during each period of the synchronization signal.

26. The circuit, according to claim 25, further characterized by a controller (115) coupled to the first digital counter (74) to provide the pre-set count.

27. The circuit, according to claim 26, further characterized by a delay element (160) coupled to the output signal, wherein the delay element can be set to a predetermined delay by the controller (115). ).

28. The circuit, according to claim 25, further characterized by a delay element (160) coupled to the output signal to provide a pulse signal to a delay that can be established with respect to the signal of output, and wherein the preset count of the first digital counter (74) and the pre-set delay are coordinated to align a phase of the driving signal with respect to the synchronization input signal.

29. The circuit, according to claim 16, further characterized by a scanning circuit (52) that responds to the output signal to scan at a second multiple of the frequency sync.

30. The circuit, according to claim 29, characterized in that the frequency sync represents a horizontal video line scan frequency and wherein the output signal has a frequency of twice the sync frequency for a scan without interlazo.

31. The circuit, according to claim 29, further characterized by an assured phase cycle (54) coupled to the scanning circuit, the phase-locked circuit being that which responds to an output of the bypass element of the circuit. phase (142).

32. The circuit, according to claim 19, characterized in that the phase change element (160) and the phase shunt element (142) are coordinated to maintain the predetermined phase alignment with the synchronization input signal. .

The circuit, according to claim 32, characterized in that the phase shunt element (142) includes a digital counter (74) and the phase change element (160) includes a monostable (164) with a selectable pulse width, a controller (115) that can be operated to select the predetermined count.

34. A synchronization circuit, including: a source of a synchronization input signal (SYNC); a source (34) of clock signals; characterized by the element (24) for synchronizing the clock signals with respect to the input signal, the clock signals displaying a periodic variation in the frequency within each period of the synchronization input signal; a splitter (42) coupled to the source of clock signals to divide the frequency of the clock signals to obtain a frequency output signal greater than that of the input signal; the element (142) for deriving a phase of a division period of the divisor in relation to a phase of the synchronization input signal in order to counteract the periodic variation in the frequency.

35. A circuit, in accordance with the claim in claim 34, further characterized by the element (160) to change a phase of the output signal to compensate for a phase deviation generated by the phase shunt element.

36. A circuit, according to claim 35, further characterized by a scanning circuit (52) driven by the phase change output signal at a frequency higher than the input signal but synchronized therewith.