JPH04188961A - Phase variable phase locked loop circuit - Google Patents

Abstract

PURPOSE:To improve the performance of a monitor for high vision signal reproduction by outputting a clock pulse whose phase is varied for an input synchronizing signal from a frequency divider. CONSTITUTION:This circuit is comprised of an input terminal 1, a phase comparator 2, a filter circuit 3, a voltage controlled oscillator 4. the frequency divider 5, a shift register 6. and an output terminal 7. Also, it is comprised in such a way the clock pulse whose phase is varied for the input synchronizing signal can be outputted from the frequency divider 5. Therefore, the display position in a horizontal direction of an image can be adjusted by controlling the width of a blanking period appearing at the right and left sides of image display by generating the synchronizing signal capable of adjusting phase difference for the input synchronizing signal and synchronizing it with a video signal by using the synchronizing signal as a horizontal synchronizing signal. Thereby. it is possible to contribute to the Improvement of the performance of the monitor for high vision signal reproduction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked circuit, and more particularly to a phase-locked circuit capable of outputting a synchronization signal whose phase with respect to an input synchronization signal is arbitrarily changed.

Currently, experimental broadcasting is being carried out regarding high-definition broadcasting, and equipment such as high-definition signal playback monitors to receive this broadcasting is being developed. In order to popularize this, it is necessary to develop easy-to-use equipment that is easy to adjust.

[Prior art] In a high-definition signal reproduction monitor, MUSE
The RC and B video signals decoded by the decoder and the MU
Synchronizing signals for synchronizing the video signals generated inside the SE decoder are separated and input separately.

FIG. 4 is a video signal waveform diagram, and as shown in the figure, the phase of the horizontal synchronizing signal is shifted from approximately the center of the horizontal blanking period,
If the image is biased toward the back porch, the image will be displayed biased to the left of the center as shown in Figure 5, and if the horizontal synchronization signal is out of phase and biased toward the front porch, the image will be displayed from the center. Displayed biased to the right.

In such cases, conventionally, a one-jit multivibrator was used to delay the phase of the horizontal synchronization signal to adjust the display position of the image.

[Problem to be solved by the invention]

Therefore, with the method of using a one-jit multivibrator to delay the phase of the horizontal synchronization signal, it is possible to delay it but not to advance it, and the amount of delay is limited by the timing circuit used for the one-jit multivibrator. Since it is constrained to a constant, it is impossible to obtain an arbitrary amount of delay, and the phase of the horizontal synchronization signal cannot be precisely controlled.

An object of the present invention is to generate a synchronization signal having an arbitrary phase difference with respect to an input synchronization signal.

[Means to solve the problem]

FIG. 1 is an electric circuit block diagram for explaining the principle of the phase-variable phase synchronization circuit of the present invention. As shown in the figure, the phase difference between the input synchronization signal and the clock pulse output from the shift register 6 is detected. a phase comparator 2 that outputs a detection signal, a filter circuit 3 that removes unnecessary components of the detection signal output from the same phase comparator 2, and changes the oscillation frequency by the output from the filter circuit 3. a voltage-controlled oscillator 4 that outputs a clock pulse at a first frequency; and a frequency divider that divides the clock pulse output from the voltage-controlled oscillator 4 and outputs a clock pulse of a first frequency and a clock pulse of a second frequency. 5, and the shift register 6 which operates a circuit with the clock pulse of the first frequency applied from the frequency divider 5 to delay the phase of the clock pulse of the second frequency and output the delayed clock pulse, The frequency divider 5 outputs a clock pulse of the second frequency as a clock pulse whose phase is changed with respect to the input synchronizing signal.

[Effect]

In the present invention, with the above-described configuration, a clock pulse whose phase is changed with respect to an input synchronizing signal is output.

FIG. 3 is a waveform diagram for explaining the operation of a phase-variable phase synchronized circuit according to an embodiment of the present invention, where T is the period of the clock pulse of the first frequency input to the shift register 6,
When the number of stages of the shift register 6 used is N, the comparison waveform B whose phase is delayed by t-NT from the output waveform C of the clock pulse of the second frequency output from the frequency divider 5 is output from the shift register 6. and is input to the phase comparator 2 as a comparison signal.

When the phases of the input synchronization signal waveform A and comparison waveform B become synchronized in the phase comparator 2, the falling portions of both signal waveforms match as shown in FIG. Output waveform C whose phase is advanced by NT
is obtained from the frequency divider 5.

Instead of the horizontal synchronizing signal shown in FIG. 4, the clock pulse of the output waveform C output from the frequency divider 5 is used, and the horizontal synchronization with the video signal is achieved at the falling edge of the clock pulse. By controlling the number of stages N, the width of the blanking periods appearing on the left and right sides of the image display shown in FIG. 5 can be adjusted arbitrarily, and the widths of the left and right blanking periods can be made the same. Alternatively, the display position of the image can be shifted to one side and the width of the blanking period can be shifted to the other side.

〔Example〕

FIG. 2 is an electric circuit block diagram of a phase-variable phase synchronized circuit showing an embodiment of the present invention.
The horizontal synchronization signal and the clock pulse output from the shift register 6 as a comparison signal are input to the phase comparator 2, and the phase difference between the two human input signals is detected by the phase comparator 2. is detected and the detection signal is input to a filter circuit 3, which removes unnecessary high frequency components contained in the detection signal and inputs it to a voltage controlled oscillator 4.

The voltage controlled oscillator 4 generates a clock pulse of, for example, 17.28 KHz, and inputs the clock pulse to a frequency divider 5, which divides the 17°28 KHz clock pulse by 4 to 4.32 MHz. A clock pulse of 4.32 MHz is generated and inputted to the shift register 6, and the clock pulse of 4.32 MH
The shift register 6 is operated by the clock pulse z.

Further, the frequency divider 5 divides the 4.32 MHz clock pulse by 128 to generate a 33.15 KHz clock pulse, which is input to the shift register 6. For example, the shift register 6 may have 128 stages. 33.75K input in the same shift register 6
The Hz clock pulse is delayed and outputted, and is inputted to the phase comparator 2 as a comparison signal.

FIG. 3 is a waveform diagram for explaining the operation of a phase variable phase synchronization circuit showing an embodiment of the present invention. When the input horizontal synchronization signal and comparison signal are in phase synchronization, FIG. As shown, the falling edges of the input synchronizing signal waveform A and the comparison signal waveform B match.

In Figure 2, a 128-stage shift register 6 is used and a 4.32 MHz clock pulse is used, so the period of the clock pulse per shift register is #231 (nS) 4.32X10' Total delay Time t is 231 (nS)×128! The 33.75KH2 clock pulse output from the q29.5 (#S) frequency divider 5 is supplied to the output terminal 7 as an output from the phase synchronization circuit, and therefore the output waveform C shown in Fig. 3 is input. The phase can be advanced by a maximum of 29°5 (μS) from the synchronizing signal waveform A.

The horizontal synchronization signal of the high-vigilance signal uses 33.75 KHz, and one horizontal period is approximately 29.63 μs.
Therefore, by operating the controller 11, an operation signal is input to the microcomputer 10, and the microcomputer 10 outputs a 7-bit control signal to control the operation of the 128-stage shift register, thereby changing the output waveform C to 1. 231 within horizontal period
It becomes possible to perform phase adjustment in units of (nS).

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to generate a synchronization signal whose phase difference with respect to a human synchronization signal can be adjusted, and to use the synchronization signal as a horizontal synchronization signal to synchronize video signals. For example, it is possible to adjust the horizontal display position of the image by controlling the width of the blanking period that appears on the left and right sides of the image display, which greatly contributes to improving the performance of high-visibility town signal reproduction monitors.

[Brief explanation of drawings]

FIG. 1 is an electric circuit block diagram for explaining the principle of a phase-variable phase-locked circuit according to the present invention, FIG. 2 is an electric circuit block diagram of a phase-variable phase-locked circuit showing an embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram for explaining the operation of the same circuit as above, FIG. 4 is a video signal waveform diagram, and FIG. 5 is an explanatory diagram of the west side of the display using the video signal of FIG. 1- Input terminal, 2- Phase comparator, 3- Filter circuit, 4- Voltage controlled oscillator, 5- Frequency divider, 6- Shift register, 7- Output terminal, 10- Microcomputer, 1
1- Controller. Patent applicant: Fujitsu General Ltd. Figure 1 Figure 4 Figure 5

Claims (1)

[Claims] (1) A phase comparator that detects the phase difference between the input synchronization signal and the clock pulse output from the shift register and outputs a detection signal, and a phase comparator that removes unnecessary components of the detection signal output from the same phase comparator. A filter circuit that outputs, a voltage controlled oscillator that changes the oscillation frequency according to the output from the filter circuit and outputs a clock pulse, and divides the clock pulse output from the voltage controlled oscillator to generate a clock of a first frequency. a frequency divider that outputs a pulse and a clock pulse of a second frequency; and a circuit is operated with the clock pulse of the first frequency added from the frequency divider to change the phase of the clock pulse of the second frequency. A phase-variable phase synchronization circuit comprising the shift register that outputs a delayed signal, and outputting a clock pulse whose phase is changed with respect to the input synchronization signal from the frequency divider.