MXPA04008502A - Metodos para buscar previamente, datos/instrucciones relacionados con eventos activados externamente. - Google Patents

Metodos para buscar previamente, datos/instrucciones relacionados con eventos activados externamente.

Info

Publication number
MXPA04008502A
MXPA04008502A MXPA04008502A MXPA04008502A MXPA04008502A MX PA04008502 A MXPA04008502 A MX PA04008502A MX PA04008502 A MXPA04008502 A MX PA04008502A MX PA04008502 A MXPA04008502 A MX PA04008502A MX PA04008502 A MXPA04008502 A MX PA04008502A
Authority
MX
Mexico
Prior art keywords
data
instructions
processor
cache
memory
Prior art date
Application number
MXPA04008502A
Other languages
English (en)
Inventor
Doering Andreas
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MXPA04008502A publication Critical patent/MXPA04008502A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

Se da a conocer un metodo para la busqueda previa de datos / instrucciones relacionadas con eventos activados externamente en un sistema que incluye una infraestructura (18), que tiene una interfaz (20) de entrada, para recibir datos / instrucciones que se van a manejar por dicha infraestructura, y un interfaz (22) de salida para transmitir datos, despues que ellos se han manejado, una memoria (14) para almacenar datos / instrucciones cuando ellos son recibidos por la interfaz de entrada, un procesador (10) para procesar al menos algunos datos / instrucciones, este procesador tiene una memoria cache, en que dichos datos / instrucciones son almacenados, antes de ser procesados, y una fuente externa (26) para asignar tareas en secuencia al procesador. El metodo comprende las siguientes etapas, las cuales son realizadas mientras el procesador realiza una tarea previa: determinar la ubicacion en la memoria de datos / instrucciones que se van a procesar por el procesador, que indican a la memoria cache las direcciones de estas ubicaciones de la memoria, buscar los contenidos de las ubicaciones de la memoria y escribir los mismos en la memoria cache, y asignar la tarea del proceso de los datos / instrucciones en el procesador.
MXPA04008502A 2002-03-05 2003-02-27 Metodos para buscar previamente, datos/instrucciones relacionados con eventos activados externamente. MXPA04008502A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02368022 2002-03-05
PCT/EP2003/002923 WO2003075154A2 (en) 2002-03-05 2003-02-27 Method of prefetching data/instructions

Publications (1)

Publication Number Publication Date
MXPA04008502A true MXPA04008502A (es) 2004-12-06

Family

ID=27771964

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA04008502A MXPA04008502A (es) 2002-03-05 2003-02-27 Metodos para buscar previamente, datos/instrucciones relacionados con eventos activados externamente.

Country Status (8)

Country Link
JP (1) JP2005519389A (es)
KR (1) KR20040101231A (es)
CN (1) CN100345103C (es)
AU (1) AU2003221510A1 (es)
BR (1) BR0308268A (es)
CA (1) CA2478007A1 (es)
MX (1) MXPA04008502A (es)
WO (1) WO2003075154A2 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4837247B2 (ja) * 2003-09-24 2011-12-14 パナソニック株式会社 プロセッサ
US8224937B2 (en) * 2004-03-04 2012-07-17 International Business Machines Corporation Event ownership assigner with failover for multiple event server system
WO2006061767A1 (en) 2004-12-10 2006-06-15 Koninklijke Philips Electronics N.V. Data processing system and method for cache replacement
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619663A (en) * 1994-09-16 1997-04-08 Philips Electronics North America Corp. Computer instruction prefetch system
US5854911A (en) * 1996-07-01 1998-12-29 Sun Microsystems, Inc. Data buffer prefetch apparatus and method
US5761506A (en) * 1996-09-20 1998-06-02 Bay Networks, Inc. Method and apparatus for handling cache misses in a computer system
US6092149A (en) * 1997-05-28 2000-07-18 Western Digital Corporation Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor

Also Published As

Publication number Publication date
AU2003221510A8 (en) 2003-09-16
WO2003075154A3 (en) 2004-09-02
CN1698031A (zh) 2005-11-16
BR0308268A (pt) 2005-01-04
AU2003221510A1 (en) 2003-09-16
CN100345103C (zh) 2007-10-24
CA2478007A1 (en) 2003-09-12
JP2005519389A (ja) 2005-06-30
WO2003075154A2 (en) 2003-09-12
KR20040101231A (ko) 2004-12-02

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