AU2003221510A1 - Method of prefetching data/instructions - Google Patents

Method of prefetching data/instructions

Info

Publication number
AU2003221510A1
AU2003221510A1 AU2003221510A AU2003221510A AU2003221510A1 AU 2003221510 A1 AU2003221510 A1 AU 2003221510A1 AU 2003221510 A AU2003221510 A AU 2003221510A AU 2003221510 A AU2003221510 A AU 2003221510A AU 2003221510 A1 AU2003221510 A1 AU 2003221510A1
Authority
AU
Australia
Prior art keywords
instructions
prefetching data
prefetching
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003221510A
Other versions
AU2003221510A8 (en
Inventor
Andreas Doering
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of AU2003221510A8 publication Critical patent/AU2003221510A8/en
Publication of AU2003221510A1 publication Critical patent/AU2003221510A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
AU2003221510A 2002-03-05 2003-02-27 Method of prefetching data/instructions Abandoned AU2003221510A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02368022 2002-03-05
EP02368022.6 2002-03-05
PCT/EP2003/002923 WO2003075154A2 (en) 2002-03-05 2003-02-27 Method of prefetching data/instructions

Publications (2)

Publication Number Publication Date
AU2003221510A8 AU2003221510A8 (en) 2003-09-16
AU2003221510A1 true AU2003221510A1 (en) 2003-09-16

Family

ID=27771964

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003221510A Abandoned AU2003221510A1 (en) 2002-03-05 2003-02-27 Method of prefetching data/instructions

Country Status (8)

Country Link
JP (1) JP2005519389A (en)
KR (1) KR20040101231A (en)
CN (1) CN100345103C (en)
AU (1) AU2003221510A1 (en)
BR (1) BR0308268A (en)
CA (1) CA2478007A1 (en)
MX (1) MXPA04008502A (en)
WO (1) WO2003075154A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4837247B2 (en) 2003-09-24 2011-12-14 パナソニック株式会社 Processor
US8224937B2 (en) * 2004-03-04 2012-07-17 International Business Machines Corporation Event ownership assigner with failover for multiple event server system
CN101073051A (en) 2004-12-10 2007-11-14 皇家飞利浦电子股份有限公司 Data processing system and method for cache replacement
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619663A (en) * 1994-09-16 1997-04-08 Philips Electronics North America Corp. Computer instruction prefetch system
US5854911A (en) * 1996-07-01 1998-12-29 Sun Microsystems, Inc. Data buffer prefetch apparatus and method
US5761506A (en) * 1996-09-20 1998-06-02 Bay Networks, Inc. Method and apparatus for handling cache misses in a computer system
US6092149A (en) * 1997-05-28 2000-07-18 Western Digital Corporation Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor

Also Published As

Publication number Publication date
MXPA04008502A (en) 2004-12-06
CA2478007A1 (en) 2003-09-12
AU2003221510A8 (en) 2003-09-16
BR0308268A (en) 2005-01-04
WO2003075154A2 (en) 2003-09-12
CN100345103C (en) 2007-10-24
WO2003075154A3 (en) 2004-09-02
CN1698031A (en) 2005-11-16
KR20040101231A (en) 2004-12-02
JP2005519389A (en) 2005-06-30

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase