MXPA01004320A - Horizontal synchronization for digital television receiver - Google Patents

Abstract

A horizontal synchronizing system, comprising:a source of a horizontal synchronizing signal (1fH INPUT);a source (20, 28) of first and second higher frequency horizontal drive signals;a phase detector (14) for generating a first control voltage (17) responsive to the horizontal synchronizing signal and the first horizontal drive signal;a source (22, 24) of a second control signal (25);and, a switch (18) for selectively supplying the first control signal to the source of the drive signals for a phase- locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.

Description

HORIZONTAL SYNCHRONIZATION FOR A DIGITAL TELEVISION RECEIVER FIELD OF THE INVENTION The invention relates to the field of horizontal synchronization in digital television receivers.

BACKGROUND OF THE INVENTION Analog video signals have a horizontal synchronization and a tracking frequency of approximately 15,735KHz in the NTSC system. This synchronization and scanning frequency are different in PAL and SECAM systems, but they are generally comparable. Regardless of the system, this is generally referred to as a horizontal synchronization and standard scanning frequency, often denoted by fH or 1f H. Television receivers provide a better progressive scan than an interlaced scan, operating at twice the the standard synchronization frequency, approximately 31.47 KHz in NTSC, frequently denoted as 2fH. Such television receivers perform an upward conversion of the analog video input, by using digital circuits that duplicate the number of horizontal lines per field, either by repetition of each line or by interpolation. A phase detector is used to synchronize deflection circuit 2fH with an input video signal 1 f H.

Digital television receivers, for example those used to process video signals in the MPEG2 format, can have horizontal synchronization circuits operating at 2.14 fH, approximately 33.75 KHz. Circuits for processing an MPEG2 signal include a time-based correction function, which omits the need for a phase detector. Instead, a binary speed multiplier that responds to a microprocessor controls an oscillator, which, in turn, excites a number of counters that divide the output of the oscillator downward toward the desired horizontal excitation frequency. The up converted video data is written and read into a memory, so that the time base correction is provided. In the prior art of digital televisions, it was thought that they operated at 2.14fH, a standard 1fH video could simply be converted up to 2.14 fH; and certainly the upward conversion presented no special difficulties. However, a number of unforeseen problems arose when displaying the converted video up to 2.14fH. One of the problems encountered was based on the coupling of the voltages and deflection currents within the NTSC 1 fH signal paths within the television receiver, for example from the antenna, from a video cassette recorder and from a DVD player. This is similar to the signal capture and the coupling that can occur inside the television receiver, for example, by circuits to ground on the circuit boards. A third ground wire from the television receiver or externally connected components can also contribute to this signal pick-up. Under this condition, the currents and / or deflection voltages 2.14fH are asynchronous with respect to the input signal NTSC to be displayed and the coupled signal appears in the scanner as an interference similar to the horizontal bars.

It was found that this effect can be reduced by operating a deflection circuit at 2fH instead of 2.14fh. Under these conditions, the coupled interference is reduced in visibility, but is still present and can be observed in the tracker as vertical bars that move horizontally, similar to horizontal shading, except that the moving bars are not fixed in the scan . The unwanted coupled signal moves because the upconversion process does not maintain the horizontal phase relationship of the output of the display section with the incoming NSTC signal. While the upconverted NTSV is closed in frequency at the 2fh scanned, these signals are not on the identical frequency and are not synchronized in phase. Accordingly, a solution was needed that would allow a digital television receiver to display digital video signals, for example in the MPEG2 format, at 2.14fH and to display standard video signals, for example NTSC, in a progressively scanned format. , turned up.

The visibility of the interference due to the scan converted upward even to 2fH, instead of 2.14fH, can also be reduced by closing the phase / frequency deflection 2fH for the incoming 1fH signal. This reduces any coupled signal generated by deflection to a stationary interference in the tracking display. In accordance with this solution, the synchronization / excitation signal obtained from the video input signal 1fH is compared to the deflection exciter pulse in a phase detector. The output of the phase detector is then used to control the frequency of a voltage controlled oscillator. The pixel display clock for the MPEG2 video signal is derived from the VCO, and in accordance with this, controlling its frequency allows closing the closed-phase circuit to bring the 2fH deflection to a phase / frequency closure with the phase component. horizontal synchronization of NTSC input of 1 f H. However, this solution presents another problem, the need to operate the television receiver in two different horizontal scanning frequencies for different kinds of video input signal, for example digital video signal in the MPEG2 format at 2.14 fH and analog video signal in the NTSC, PAL or SECAM formats at 2fH.

BRIEF DESCRIPTION OF THE INVENTION A system of horizontal synchronization in accordance with the inventive configurations, which solves the problems encountered by the prior art, which comprises: a horizontal synchronization signal source, a source of a first and a second higher frequency horizontal excitation signals, a source of a first control voltage, a control signal source; and the source of the excitation signals has a phase locked operation mode at the first higher frequency, which responds to the first control signal and a phase disengage operation mode at a second higher frequency, which responds to the second control signal. The system may also comprise means for the phase lock of the first excitation signal with the source of the horizontal synchronization signal. The source of the excitation signals may comprise a controllable oscillator. The oscillator can operate at the same frequency, which responds to both the first and the second control signals, which is advantageous. The source of the excitation signals may also comprise counters timed by the oscillator and provide different numbers of samples during blocking in the first and second higher frequencies, respectively. Another horizontal synchronization system in accordance with the inventive arrangements, which solves the problems faced by the prior art, comprises: a horizontal synchronization signal source; a source of a first and second signals of horizontal excitation with higher frequency, a phase detector for generating a first control voltage that responds to the horizontal synchronization signal and the first horizontal excitation signal; a source of a second control signal; and a switch for selectively supplying the first control signal to the source of excitation signals for the engaged phase operation mode, of a higher first frequency and supplying the second control signal to the source of the excitation signals. for unlinked phase operation mode, at a second higher frequency. The source of the excitation signals may comprise; a voltage-controlled oscillator and counters for supplying different sample numbers during blocking at the higher first and second frequencies, respectively. The source of the second control signal may comprise; a binary speed multiplier and a binary speed multiplier filter. The system may also advantageously comprise a circuit that responds to the excitation signals to generate a pulse width amplified timing signal as an input to the phase detector, in order to control the response speed of the circuit phase engaged. A horizontal synchronization system in accordance with a currently preferred embodiment comprises: a source of a horizontal synchronization signal fH; a source of signals horizontal excitation nfH and mfH; where n > _ 2, m _ 2 and n is an integer; a phase detector for generating a first control signal responsive to the horizontal synchronization signal fH and the horizontal excitation signal nfH; a source of a second control signal; and a switch for selectively supplying the first control signal to the source of the excitation signals for the phase operation mode engaged to nfH and supplying the second control signal to the source of excitation signals for the operation mode. from phase disengaged to mfH. The factor n can be equal to 2 and the factor m can be equal to 2.14. The source of the excitation signals may comprise: a voltage controlled oscillator; and counters to change the number of samples during blocking at the nfH and mfH frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a multiple frequency horizontal synchronization system in accordance with the inventive arrangements; Figure 2 is a schematic diagram of a first embodiment for implementing the synchronization system shown in Figure 1; Figure 3 is a schematic diagram of a second embodiment for implementing the synchronization system shown in Figure 1; Figure 4 illustrates the waveforms useful to explain the operation of the phase detector of Figure 3.

DETAILED DESCRIPTION OF THE INVENTION Figure 1 shows a block diagram of a multiple frequency horizontal synchronization system 10, in accordance with the inventive arrangements. The system has selectable modes of operation, including an open circuit and closed circuit control path for an oscillator 20. The oscillator can, for example, be a voltage controlled oscillator (VCO) or an oscillator. of glass controlled by voltage (VCXO). The open-loop control is used to display the digital video signals, for example in the MPEG2 format. Oscillator 20 operates at 13.5 MHz, which is then doubled at 27 MHz and used as the reference for an 81 MHz pixel display clock and the MPEG2 system clock. The open circuit control path starts with a microprocessor (μP) 26 which supplies a digital frequency control value to a binary speed multiplier (BRM) on a data bus 40. The digital frequency control value is converted into a control voltage of the MPEG2 system clock by a BRM filter. The output of the BRM filter 24 on line 25 is a first input to a filter source switch 18. The control voltage of the MPEG2 system clock is supplied to the oscillator 20 from the filter source switch 18, which responds to a selection signal 2fH / 2.14fH generated by the microprocessor 27. The input of the filter BRM represents the control signal used for the deflection 2.14 fH. The selection signal is illustrated as a direct cable connection, but the selection control can also be installed by the data bus or by serial data and the type control bus having SDA and SCL signals, not shown . A clock generation and a meter circuit 28 respond to the output of the oscillator 20. A tracking generator responds to the clock generation and the meter circuit 30, and in turn excites the display circuit 36. The deployment circuit generates an excitation signal 2.14 fH. In the currently preferred embodiment, circuits 28, 30 and 36 are incorporated in an integrated Sti7000 circuit available from ST Microelectronics. The closed circuit path includes a phase detector 14.

An analog video signal 1 f H standard, for example NTSC, PAL or SECAM, is an input for a synchronization and digitizer signal separator 12. A synchronization signal 1 f H is a first input for the phase detector 14. The excitation signal generated by the display circuit 36 is fed back as a second input to the phase detector 14. The feedback path includes a branch point that illustrates the three different modalities. In one embodiment, the path 44 leads directly to the phase detector without any modification of the excitation signal. In this case, the phase detector compares the phase of each 1fH synchronization pulse with each other impulse of the excitation signal. In the case of an input video signal of 1fH, the excitation signal will have a frequency of 2fH. In a second embodiment represented by the pulse width expansion circuit 46, the excitation pulses are expanded, for example from a width of about 1 μsec to 9 μsec. In a third embodiment represented by the divider circuit 48, the excitation signal is divided into two. The modalities represented by the circuits 46 and 48 allow the resulting latched phase circuit to operate with a shorter response time than when a direct path 44 is used. The output of the phase detector is integrated by the phase detector filter 16. The integrated output is a latched phase control voltage supplied as a second input to the filter source switch 18 on the line 17. The phase detector filter input represents the control signal used for the deflection 2fH. Analog video that has been processed by digitizer 12 is supplied to lines 15 to an upconversion circuit of 1fH to 2fH. Upconversion can be achieved by doubling the number of horizontal lines, as the digitized video is read from memory 34. Alternatively, upconversion can be achieved by interpolation. The upconverted video signal is read from the memory 34 within the display circuit 36, and is then supplied as a Video output signal (VIDEO OUTPUT). The upconversion circuit 32 can also be part of the Sti7000 integrated circuit. During operation at 2.14fH there will be an input of 2.14fH in the phase detector 14 and there will also be a synchronization signal applied to the phase detector, even if the 1fH signal is not selected for deployment. However, at that time the filter source switch will be supplying the clock control voltage of the MPEG2 system to the oscillator and the output of the phase detector 16, if any, will be effectively ignored. When the system supplies the excitation signal 2fH instead of the excitation signal 2.14 fH, the oscillator operates at the same clock frequency. Instead of changing the frequency of the oscillator, the operation of the clock generation and the counter circuit 28 are modified to change the number of samples during blocking. The important difference is that the excitation signal 2fH and the input signal 1fH are locked in phase, thereby eliminating or at least essentially eliminating the noise problem resulting from the unhooked operation. Figure 2 illustrates a first set of modalities for installing the different parts of the system 10 shown in Figure 1. The pulse width expansion circuit 46 can be incorporated as an integrated circuit U2 CD4098, a double shot CMOS. The single shot uses an external timing circuit formed by capacitor C3 and resistors R2 and R3 for expand the 2fH excitation pulse from a μsec duration to 9 μsec duration. The phase detector 14 can be installed by an integrated U3 circuit MC1391, a horizontal television processor that includes a phase detector. The output of a shot U2 is filtered by resistors R4 and R5 and capacitor C4 and then applied to pin 4 of U3. The horizontal synchronization signal 1 fH is filtered by the resistor R1 and the capacitor C1 and is applied to the pin 3 of U3. The output of the phase detector is applied to the phase detector filter 16, which is incorporated as an integrator formed by the capacitors C5 and C5 and the resistor R6. The voltage at the output of the integrator is then supplied to an operating amplifier U4 TL082, wherein the voltage is scaled to match the VCO / VCXO 20 range. The filter source switch 18 can be incorporated as a multiplexer integrated U5 circuit analog CD4053B. An input contact of a switch A is coupled to the output of an op-amp U4 on pin 13. The other input contact of switch A is coupled with the filter 24 BRM, through resistor R22, on pin 13 of U5. A switch incorporated by transistor Q1 controls the voltage at pin 11 of U5, in response to the control signal 2fH / 2.14fH, thereby controlling the operation of switch A. Switch A selects either the BRM filter or the filter of phase detector as the control source for oscillator 20, for operation at 2.14 fH and 2fH, respectively.

Figure 3 illustrates a second set of modalities for installing various parts of the system 10 shown in Figure 1. The embodiment of Figure 3 is particularly useful for a VCXO oscillator, which uses varactors to control the frequency. With certain advantages, this mode combines the phase detector and the scaler of Figure 2, which reduces the number of components, by having the output of the phase detector directly, generates the range of 0 to 15 volts required for VCXO varactors . In this sense, the phase detector 14 is incorporated into an analogue multiplexer U6 CD4053B, in which the switch A is switched between + 15 volts on the plug 13 and the ground on the plug 12 at a speed of 2fH based on the Deflection The pulse width expansion circuit 46 in Figure 3 is incorporated by a one-shot component circuit formed by the transistors Q2 and Q3. The values of the resistors R10, R11, R12, R13 and R14 are selected to provide an output pulse of approximately 9 μsec, which responds to an input pulse of approximately 1 μsec, as in Figure 2. It should be appreciated that The embodiments of the pulse width expansion circuit 46 shown in Figures 2 and 3 are interchangeable. The speed control 2fH for the switch A is the excitation pulse 2fH of expanded width applied to the pin 11. The switch B is controlled by the transistor Q4 which responds to the synchronization component 1 f H. The output of the switch B is coupled from the pin 1 with the detector filter 16 phase, incorporated by capacitors C16 and C17 and resistor 18. The integrated voltage is coupled to an input of switch C on pin 3. The output of filter BRM is coupled to another input of switch C on pin 5. Switch C switches the voltage applied to the VCXO varactors between the output of the phase detector for an upconversion operation of the video signal 1fH and the output BRM used in the normal MPEG2 decoding. In this sense, the magnitudes of the charge of the phase detector filter and the discharge currents are determined mainly by the value of the resistor R17, currently 20K. In the hooked condition, the average value of the load and discharge currents are equal. Figure 4 illustrates the voltage at pin 15, the voltage at pin 10 and the current through resistor R17, which is also the current at pin 1. It can be seen that signal 1fH at pin 10 samples each pulse of the 2fh signal at pin 15, which causes negative and positive currents at resistor R17 / pin 1. More particularly, when the pulses of signal 1fH are presented, the integrator is charged or discharged. When impulses 1 f H are not present, the integrator input floats. The integrated current in pin 3 does not need to be scaled to excite the VCXO varactors.

Claims (16)

1. A horizontal synchronization system, which comprises: - a source of a horizontal synchronization signal characterized by: - a source of a first and second (output of BRM 22) higher frequency horizontal excitation signal; a phase detector for generating a first control voltage, which responds to the horizontal synchronization signal and the first horizontal excitation signal; - a source of a second control signal; and - a switch for selectively supplying the first control signal with the source of the excitation signal for a phase operation mode engaged to the first higher frequency and supplying the second control signal to the source of the signaling signals. excitation for a phase operation mode disengaged at the second highest frequency.

2. The system according to claim 1, wherein the source of the excitation signals comprises: a voltage controlled oscillator; and counters for supplying different numbers of samples during blocking at the first and second highest frequencies, respectively.

3. The system according to claim 1, wherein the source of the second control signal comprises: a binary speed multiplier; and a binary velocity multiplier filter.

4. The system according to claim 2, wherein the oscillator comprises a crystal oscillator.

5. The system according to claim 1, further comprising a circuit responsive to the excitation signals and for generating a pulse width expanded timing signal as an input to the phase detector.

6. The system according to claim 5, wherein the circuit responding to the excitation signals comprises a trip.

7. The system according to claim 1, wherein the phase detector comprises a multiplexer.

8. The system according to claim 7, wherein the multiplexer comprises: - a first switch having inputs coupled through of potential impulses and generators at the highest frequency as an output that responds to the first excitation signal; a second switch having an input coupled to sample the first higher frequency output pulses that respond to the horizontal synchronization signal; an integrator to develop the first control signal, which responds to the sampled impulses; and a third switch having a first and second control signals coupled with the respective input contacts and having an output coupled with the source of the excitation signals.

9. A horizontal synchronization system, which comprises: a horizontal synchronization signal source fH; characterized by: - a source of horizontal excitation signals nfH and mfH, where n > 2, m > 2 and n is an integer; - a phase detector, a first phase control signal that responds to the horizontal synchronization signal and the horizontal excitation signal nfH; - a source of a second control signal; and a switch for selectively supplying a first control signal to the source of the excitation for a phase operation mode engaged to nfH and supplying the second control signal to the excitation signal source for a phase operation mode unlinked to mfH.

10. The system according to claim 9, wherein the source of excitation signals comprises: a voltage controlled oscillator; and counters to change the number of samples during blocking at the nfH and mfH frequencies.

11. The system according to claim 9, wherein n = 2 and m = 2.14.

12. A horizontal synchronization system, which comprises: a horizontal synchronization signal source; characterized by: a source of first and second highest frequency horizontal excitation signals; a source of a first control voltage; a source of a second control signal; and the source of the excitation signals has a phase operation mode engaged at the first highest frequency, which responds to the first control signal and a unlinked phase operation mode at the second highest frequency, which responds to the second control signal.

13. The system according to claim 12, further comprising means for phasing the first excitation signal with the source of the horizontal synchronization signal.

14. The system according to claim 12, wherein the source of excitation signals comprises a controllable oscillator.

15. The system according to claim 14, wherein the oscillator operates at the same frequency that responds to both the first and the second control signals.

16. The system according to claim 14, wherein the source of excitation signals also comprises counters timed by the oscillator and supplying different numbers of samples during blocking at the first and second highest frequencies, respectively.