MXPA01001035A - Clocked integrated semiconductor circuit and method for operating the same - Google Patents

Abstract

An integrated semiconductor circuit with a plurality of circuit units (S1, S2, S3, HS) that are controlled by a clock signal (Clint) and can be operated in parallel or serially. A connection providing said clock signal (Clint) is connected to the clock input of the respective circuit units (S1, S2, S3, HS) via respective controllable switching means (MP1, MP2, MP3, MP4). The control inputs of the switching means (MP1, MP2, MP3, MP4) are connected to the output of a random signal generator (ZSG), whereby a circuit unit (S1, S2, S3, HS) is operated parallel to or serially with at least one other circuit unit (S1, S2, S3, HS) according to the random signal.

Description

l SOLID STATE CIRCUIT OPERATED BY PULSES AND PROCEDURE FOR THE OPERATION OF THE SAME The invention relates to an integrated solid state circuit, with a number of switching units operating in both parallel and series controlled by a pulse signal, thus as a method for operating such integrated solid-state circuits. 10 Integrated solid-state circuits are mainly used for the development of signals or data and are based on the digital switching technique. Such digital circuits generally need a pulse signal to be able to work synchronously and according to a course determined by the corresponding use. Frequently, certain processes are elaborated according to defined protocols. These protocols need a certain number of pulse signal periods. In many applications such as eir integrated solid state circuits for chip card, the necessary pulse signal is supplied from outside by means of a connection "pin". In critical security applications, this is in applications in which the signals to be processed correspond to values of money or considerations of funds, there is a high interest in improving the action and information on the corresponding course to be able to take influence on the result. This information can be gained from the duration of the individual processes or from the periods of pulse signal that form the necessary number. Especially if a partial knowledge about the type of processes is already presented. Integrated solid state circuits for chip cards, mostly include a number of units Switching or circuit, such as for example a processor, a coprocessor, a memory not aligned with a corresponding programming logic, an input / output switching, such as a UART and others. In the interest of the highest processing speed As many as possible, as many switching units as possible must work simultaneously, so that in many cases one attempts during the inscription of the data in the non-aligned memory to give the processor a task and also allow it to simultaneously work on the coprocessor while the UART receives data from abroad or provides it abroad. The current processes take from the supply voltage mainly during the switching flanks of the pulse signal, energy so that by observing or monitoring the flowing current In the solid state circuit integrated by a part, the moment of the switching edges of the pulse signal can be obtained, while this is input from the outside, but on the other hand the duration of the individual processes can be obtained. determined by a longer surveillance when such processes end. Under certain circumstances, even from the knowledge of the joint process, the individual processes can be decided, and with this the elaboration structure of the integrated solid-state circuit. SUMMARY OF THE INVENTION It is therefore the task of the present invention to prevent the type of the running process from being decided by the account of the current tips of this type. The task is solved in an integrated solid-state circuit of that species where there is a connection that provides the pulse signal through a controllable switching means and which is linked to the pulse input of the corresponding switching units and the control inputs of the switching means are unit with an output of an accident signal generator, so that the operation of a switching unit is carried out in parallel or in series with one or more of the other switching units according to the measurement of the accidental signal. This is solved by a method according to claims t and 9.Other advantageous embodiments of the invention are presented in the subclaims. In the solid-state circuit according to the invention, different switching units depending on the accidental signal are operated once, simultaneously, sometime successively when a pulse signal is supplied to them or not. In this way, a process can be interrupted in a first switching unit and another process can start in another switching unit or continue, to then continue successively or simultaneously the first process. With this it is achieved that a certain process in a repetition never have the same duration and with this it is not possible to determine if it is the same process. In another advantageous embodiment is the connection that prepares the pulse signal from the output of a controllable pulse signal generator whose control input is connected with the output of an accidental signal generator so that the moment of a switching edge of the pulse signal varied according to the measurement of the accidental signal. It is especially advantageous here that the deviations or oscillations of the accidental signal are relatively slow in relation to the average period duration of the pulse signal, however the amplitude of the accidental signal differs from process to process, so that the same processes occur with Different pulse frequency and with this always have different durations. With this, a detection of the switching flanks of the pulse signal is markedly more difficult. With this conformation of the integrated solid state circuit, the dependence between an externally applied pulse signal and the internal switching pulse is removed or removed. The internal pulse signal generator generates, due to the control by the accidental signal generator, an irregular pulse so that the coordination between determined processes at specified time intervals is barely possible. In another embodiment of the invention, at least two pulse signal generators with a different frequency exist in the integrated solid state circuit, where a first number of switching units are operated with a first pulse signal and a second number of pulse units. switching are operated with a second pulse signal. If necessary, other switching units can be operated with other pulse signals. Especially in a process connection in switching units that have pulses of different frequency, another accidental presentation of the durations of the process is achieved. In another particularly advantageous embodiment of this principle, there are the individual connection means implemented as multiplexers through which each pulse signal of each switching unit can be conducted. The multiplexers are controlled by an accidental signal or by different accidental signals, so that a switching unit with different pulse signals can be operated, which can also oscillate accidentally in its frequency. In another embodiment of the invention, a pulse signal generator is constructed with a controlled oscillator especially controlled by voltage. Another embodiment of a touch signal generator can be performed with a phase regulation gauze having a controllable or adjustable frequency divider through which the frequency variations in the pulse signal are coupled. The accidental signal generator can be an accidental number generator, which presents the desired number of digital outputs and thus directly controls the frequency divider of a phase regulation gauze. However, the accidental number generator can also be connected to a D / A transformer through which, for example, the control input of an oscillator can be controlled. Usuimente presents an accidental number generator only one output so that only a switch of the oscillator between two frequencies is made. But it is also possible, connect to a stable oscillator a frequency divider which is controlled from an accidental number generator. Here it is basic to generate a pulse signal modulated in the frequency in which the degree of modulation is below statistical tipping. Here it is favorable if the average period duration of the modulation signal generated by the accidental signal generator has approximately the average duration of the course that is performed in the integrated solid-state circuit. In another advantageous special embodiment of the invention, one of the switching units is constructed as an auxiliary switching unit, with precisely about equal current expenditure as the other switching units, however without the essential function for the solid state circuit integrated. A switching controlled by the accidental signal in this auxiliary switching unit that is presented before and / or during and / or after in the switching units of the integrated solid-state circuit, and each time a defined number of the signal periods of The pulse necessary for the processes leads to an accidental variation of the duration of these processes, without this being recognized in the current expenditure. It is particularly favorable if, during a process in a switching unit, both an accidental switching in the auxiliary switching unit takes place and also one or more other switching units are accidentally operated or not. DESCRIPTION OF THE DRAWINGS The invention will be explained in detail below by means of exemplary embodiments with the help of the figures. Where it shows: Figure 1, a connection or block switching image in principle of an integrated solid-state circuit according to the invention; Figure 2, another block switching image in principle of an integrated solid-state circuit, according to the invention; Figure 3, a variant of a generator of a pulse signal, with an accidental, digital number generator; Figure 4, a variant of a pulse signal generator with a phase regulation gauze; Figure 5, the course in time of the processes with an external pulse signal and according to the invention. DESCRIPTION OF THE INVENTION. Figure 1 shows a switching image in principle of an integrated solid-state circuit, according to the invention, with three switching units SI, S2 and S3. In addition, an auxiliary switching unit HS is shown. There are three pulse signal generators TSGl, TSG2, TSG3 whose output signals can each time be fed by multiplexers MP1, MP2, MP3, MP4 to the switching units SI to S3 or HS. The multiplexers MP1 to MP4 are controlled by output signals from an accidental signal generator ZSG. Another signal output from the accidental signal generator ZSG also controls the pulse signal generators TSGl to TSG3. With the integrated solid-state circuit, according to the invention, different switching units SI to S3 or HS with pulse signals of different frequency in an accidental control are allowed to operate as indicated by the representation in principle in FIG. 1. in series or parallel. In particular, it can be introduced by the switching in the auxiliary switching units HS during the course of a process in a switching unit linked to the operation of "Dummy" pulses so that the process for an external observer is apparently longer than the process. really is. It is also possible to fit shorter processes by parallel pulses from two switching units in a longer process. Figure 2 shows, with a dashed line, an integrated solid state circuit 1, which includes other switches 2, 3 as switches or memory or logic circuits. These circuits 2, 3 receive the pulses of a pulse signal Cl? Nt this internal pulse signal is generated by a pulse signal generator TSG. The pulse signal generator TSG has a control input which is connected to the output of an accidental signal generator ZSG. The integrated solid-state circuit receives from the outside an external pulse signal Cle t, which in the example shown is supplied with a switching 4 also contained in the integrated solid-state circuit I as a pulse signal. Due to the additional use of the external pulse signal Cle? - processes can occur in different switching or circuits with different pulse frequencies. This makes it more difficult to coordinate the processes at specific time periods. In addition, there are switching units such as I / O switches that must receive the pulses of an external pulse signal, set II that contain data from an external terminal and with this they must work synchronously. The TSG pulse signal generator can be constructed as a voltage or voltage controlled oscillator and controlled from an accidental ZSG signal generator with analog output. As shown in figure 3, the accidental signal generator can also be constructed as an accidental number generator ZZG with the desired number of digital outputs. These are in the case shown in FIG. 3 of a pulse signal generator TSG connected with an analog input with an analog digital transformer D / A. Whose analog output signal controls the control input of the TSG pulse signal generator. It is subsequently connected, g in principle also possible, to a conventional pulse signal generator a controllable frequency divider, which is controlled by the accidental number generator ZZG. Also in this way an internal pulse signal Ci? Nt having a period duration or oscillating frequency in time is allowed to be generated. Such an embodiment is shown in FIG. 4 within a solid line. The pulse signal Ci 'to be used in this case is indicated by a continuous arrow as well.

Figure 4 further shows an expansion of the pulse signal generator constructed with a controllable divider T for a phase regulation gauze. Here the output signal of the divider T as well as the external pulse signal Cle - is fed to a phase detector whose output signal is conducted by means of a deep pass filter TPF to the control input of the controllable oscillator VCO. In this case, the output signal of the controllable oscillator VCO produces the internal pulse signal Cl? nt which is tilted according to the measure of the accidental number generator ZZG. Figure 5 shows the different time durations of two processes, I and II in an external pulse signal until now usual Cl '- as well as in an internal pulse signal Cl.rr according to the present invention. The external pulse signal C1-. t shown in the upper part of figure 4, has a constant frequency. A first process I should last eight periods a second process II four periods, as is clearly recognized by the upper part of figure b, would last a first process I always the same time, like a second process II. An aggressor that, for example, from the power supply obtained when the processes can develop in the solid state circuit, with repeatable periods of time of determined duration, conclude that it is a process already done. In contrast to this, an internal pulse signal Ci? Nt with a statically oscillating frequency is shown in the lower part of FIG. 5. Thus, the duration of the period varies in the points or moments of time ti, t2, t3 and t4. In addition, dashed periods of the pulse signal Cl? N-switches are shown in an auxiliary switching unit, as well as the introduction of Dummy pulses. The individual pulse periods of process 1 are characterized by the numbers 1 to you. As shown, process I has firstly a duration TI where during this duration Ti at time points ti and t2 the frequency of the pulse signal Cllnt was switched and three Dummy periods were introduced. With this the duration TI has no relation to the true duration of the process i. Next to the first process I starts a second process I whose pulse periods are also characterized by the figures I to ti. Here after the second pulse period, a Dummy pulse is introduced and then it is switched to another switching unit in which process II runs or passes. Their pulse periods are characterized with the numbers 1 'to 41. After two pulse periods of process II have elapsed, a Dummy pulse is also introduced. Subsequently, the frequency is switched at point or moment T3 on the one hand and on the other hand back to process I. On the next two pulse periods, processes I and II are then run in parallel. The process II then ends after a duration T2, while the second process I continues and ends until after a duration TI1. Processes I and II need both after and before, eight or four period durations of the pulse signal. This produces joint durations for the first two processes I of TI and Ti 'and for the second processes II of T2. As it is recognized in the lower part of figure 5, durations TI and TI1 have different durations, while process II is not presented as an individual process, so that an aggressor can not recognize which processes are involved. By means of an integrated solid-state circuit, according to the invention, it can be done in a very simple way but in a completely efficient way, preventing that by obtaining the duration for certain processes, conclusions can be drawn on its content .

Claims (10)

1. NOVELTY OF THE INVENTION Having described the invention as above, the content of the following is claimed as KJÍ ± v J. IND I.? CX UINJI1 D 1. Integrated solid-state circuit with a number of operable switching units, both in parallel as in series by means of a pulse signal, characterized in that a connection which arranges the pulse signal is connected each time by means of a switching means with the pulse input of the corresponding switching units and the control inputs. of the switching means are connected with an output of an accidental signal generator, so that the operation of a switching unit in parallel or in series, in one or more of the switching units is carried out according to or in accordance with the accidental signal. Integrated solid state circuit according to claim 1, characterized in that the connection determining the pulse signal is the output of a controllable pulse signal generator, whose control input is connected to the output of a signal generator accidental, so that the point in time or moment of a switching edge of the pulse signal varies according to the accidental signal. 3. Embodied solid state circuit according to one of claims 1 or 2, characterized in that at least two connections are provided each time determining the pulse signal, so that a first number of switching units are operated with a first signal of pulse and a second number of switching units are operated with a second pulse signal and if necessary, other numbers of switching units are operated with other pulse signals. Integrated solid-state circuit according to claim 3, characterized in that the switching means or the switching means are constructed so that each time all the pulse signals are conducted and in accordance with the accidental signal one of The pulse signals are switchable to a single switching unit. Integrated solid state circuit according to one of the preceding claims, characterized in that at least one of the pulse signal generators is constructed with a voltage or voltage controlled oscillator. Embodied solid-state circuit according to one of the preceding claims, characterized in that at least one of the pulse signal generators is constructed with a phase-regulating gauze with a frequency divider controllable by the accidental signal generator. Integrated solid state circuit according to one of the preceding claims, characterized in that at least one of the switching units is an auxiliary switching unit. 8. Procedure for operating an integrated solid-state circuit, characterized in that before and / or during and / or after the switching processes of the integrated solid-state circuit have elapsed, the processes that each time need a defined number of During the pulse signal periods, another number is introduced by the accidental signal of pulse signal periods of an auxiliary switching unit with approximately equal current consumption as the previous switching units. 9. Procedure for the operation of a pulsed-driven integrated solid-state circuit, characterized in that during a process that requires a defined number of pulse signal periods and that elapses in a first switching unit of the integrated solid-state circuit, it operates for the duration of the periods of time determined by the accidental signal, at least one other switching unit by the power supply thereof or by means of another pulse signal. Method according to claim 9, characterized in that at least one of the periods of time determined by the accidental signal of the process occurring in the first switching unit is interrupted.