MXPA00011682A - Method and system for operating a multi-stage counter in one counting direction - Google Patents

Abstract

The invention relates to a method for operating a multi-stage counter (11) in one counting direction only, comprising the following steps:altering the count value of a single-stage counter (1) which can only be altered in one direction when the multi-stage counter (11) reaches certain predetermined count value states;detecting the particular count value states of the multi-stage counter (11) and the single-stage auxiliary counter (1);comparing the values of the count value states of the single-stage counter (1) and the multi-stage counter (11) which were detected;and producing an indicator signal based on the results of this comparison.

Description

PROCEDURE AND SYSTEM FOR. THE FUNCTIONING OF A COUNTER OF SEVERAL STAGES IN ONE DIRECTION COUNTING FIELD OF THE INVENTION The invention relates to a system method for operating a multi-stage counter in a counting direction. BACKGROUND OF THE INVENTION At present, many possible fields of application are known, in which a count of what happened must take place. This event can be the frequency of the use of an apparatus, the passage of people or vehicles or objects, the taking of a telephone counter, but also the capture of a travel charge, for example a km counter. in a vehicle of people or a counter of hours of operation of a determined device and not in the last degree the time of work or the time of presence weathered of a worker in his place of work. All these cases are characterized because, they must be captured as accurately as possible, this is as a rule a high field of values must be covered. Furthermore, in the aforementioned cases, the desire is generally presented that the result of the counter is not manipulable, that is, it is not retrocedible. Such a requirement can be safely carried out with a single-stage counter, which can only count backwards or forwards on the status of the counter up to that point. For example, this can be done simply by means of an EEPROM, where for each count value an EEPROM cell is provided, and the EEPROM is only writable or erasable as a forward or backward count is provided. For the first mentioned requirement that a large value area of the counter is captured, it then leads to the result that an EEPROM memory with correspondingly many memory cells has to be provided for its realization. Expressed this in numbers, it means that for example, to reach a maximum counter state of 255, exactly 255 counter cells are needed. Currently also, it is usual to build such systems as small as possible. The use of ur multistage counter with 8 bits, that is, 8 counter cells also leads to a maximum counter state of 255. Such a multistage counter (8-B? T-binary counter), presents without However, the disadvantage is that in a variation of the next counter position, it is retraced to the previous counter position. This leads to the fact that the realization of a multistage counter that only counts in one direction and simultaneously is not manipulable, is only achievable in a very difficult manner.

From EP 0321 727, a switching arrangement is described in which several EEPROM cells are arranged in series. Here several rows are again switched together. The minor cells of each one of the series represent a single value level, where the memory content of a series is only erasable by means of logical monitoring, if a transfer is made in the next higher row. The system published in that document presents exactly the disadvantages previously explained of the manipulation, since the influence on the logical switching is not guaranteed in the unidirectional container with security. A system similar to only something more complicated is presented in EP 0618591, where for each next row an auxiliary memory cell is provided, which is programmable and also erasable again, where this arrangement is also easily manipulated, since Auxiliary memory cells are both erasable and writable. By JP-02 090726A, an arrangement for measuring an A signal is known, with two counters 4 and 6. The periodic signal A, is led to the two counters each time by means of a gate 1 and 2, from here it can be split that in those counters is not treated, since it only counts in one direction, but at least they are retrocedible. Since it is a measurement arrangement here, here the corresponding opening time of both is u 1 / N. The result of the counting of the counter 4, is shown flashing while, the ratio between the two results of the counter is also 1 / N. Then, the result of the counter 4 is displayed, in a fixed manner. Next, the result of the counting of the two counters does not depend on each other, but on the frequency of the signal A, and on the proportion of the opening times of the two composite ones and 2. SUMMARY OF THE INVENTION The invention is proposed with this the task, of providing a procedure or a switching arrangement, for the operation of a multistage counter in which the security against tampering is increased. This task is solved according to the invention, with the measures presented in claims 1 and 4. For the simultaneous operation of a one-stage counter that only counts forward or backward, next to the multistage counter that properly counts the events , it is guaranteed by a comparison that the counted value of the multistage counter will coincide at least in the large magnitude with the count value of the counter of a stage. With this simple means is made the possibility of manipulation, if the coincidence with a predated proportion between both counters is not present, then the indication signal according to claim 2 shows the admissible fault, where it is tested or verified if the count value of the counter of a stage coincides with the count value of the multistage counter, in a certain proportion. According to claim 3, the admissibility is presented by the coincidence of the counting values. BRIEF DESCRIPTION OF THE FIQURE In the following, the invention will be described with reference to the figure, where an embodiment example in the form of a block switching image is presented. DESCRIPTION OF THE INVENTION The embodiment shown in the figure presents an m-stage counter, with m = 8. This is to be understood as the representation of an 8-bit binary counter. The counter 11 can count from 0 to 255, that is, 256 counting positions. The counter 11 is connected to a control unit 3, which supplies the counter 11 with a counting signal S 11. With each delivery of the counting signal S 11, the counter 11 changes in 1, where the change is made in the same direction as the previous variation. This means that the counter symbolically represented in the figure is shaped in such a way that it only counts forward or backward. The corresponding counter state of the multi-stage counter 11 is passed as a count value signal Z 11 to a test logic device 4. Furthermore, a one-stage counter is provided, which in this embodiment shows -cells, with n = 16. This counter symbolically represented in the figure must be constructed in such a way that it also only counts in a counting direction proper from 0 to 16. That is, 16 counting positions. The counter of a stage 1 receives from the control unit 3 a counting signal S 1, with which it moves in a counting value. The counting status of the counter of a step 1 is led to the control unit 3, as a signal of control count value Z 1, and with this to the test logic device 4. The logic test device 4, compares the counting value signal Z 11, with the signal of control value Z 1, and gives in dependence of the comparator a determined signal to a counter control 5. The counter control 5, again gives in dependence on the signal test P, obtained by the test logic device 4, a fault signal E. The two counters 11 and 1, for example, can be constructed as EEPROM cells. Here it is provided that correspondingly to the known operation of a binary counter, the individual memory cells can be written or erased exactly also the control counter of a stage is composed of EEPROM cells, where the individual cells 1 through n, are followed one after the other, and can only be written or only deleted.

Now, the typical operation of the system arrangement represented in the figure will be described. Basically it is provided that with each input signal E, from the control unit 3, a counting signal S 11 is to be produced. Here before the test logic 4, the counting status of the two counters 1 and 11 is tested. , by means of the count value signal Z 11, and of the control count value signal Z 1. Both are for example 0, then the test logic system 4 determines, that the match exists and passes the signal of test P, which by means of the counter control 5 provides the count signal SF. Now it is further provided that both counters count from 0 to 255. This means that the control counter of a stage 1, in each sixteenth count signal S 11, going to the counter 11, also of the counter control 5, obtains in the control unit 3, a control counting signal S 1. For the operation without manipulation, the test logic system is arranged in such a way as to ensure that the counting value of the counter 11 is adjusted to the correct response value reached of the control counter 1, this means in the illustrated embodiment that the counter value of the counter 11 can not be less than (ix 16) -1.

Correspondingly it is valid for a counting arrangement downwards, which also here the counter 11, must be 'corresponding to the counting logic in a zone that conforms to the counting value of the control meter 1. As soon as the logic system of test 4, determines that there is no coincidence a fault signal F is produced. However, the invention is not limited to the embodiment shown in the figure, but it is also representative that especially with a zone of very large counting value which is about to be written of the counter 11, to store the counter cells of the counter of a stage, this will not work in a linear manner, but for example decadic, that is, the counter of a stage would obtain for example, in 10, 100, 1000, etc., a counting signal S 11, from the counting control 5, obtaining a control counting signal S 1. To monitor the operation without manipulation, the test logic system 4 must, to be correspondingly constructed, that is, in such case the counting value of the counter 11, must correspond to the coordinated quantity of each counting value of the control meter 1. It is perfectly possible to represent, that the dependence between the meter counter 11, and the value of contests of the control meter 1, corresponds to an exponential arithmetic function or whatever is wanted, provided it is adequate, this is then applicable both for an arrangement of the counters counting upwards, as well as downwards . Then it should be noted that the counted]: 11, and the control counter 1, not necessarily have to count in the same direction, much more can also be provided that one counter count up and the other counter count down, the The only condition for operation without manipulation is that the control counter only counts one direction and the test logic system is constructed in such a way that the counting value of the counter 11, present with the count value of the control meter 1 , a logical dependence.

Claims (4)

1. NOVELTY OF THE INVENTION Having described the invention as above, the content of the following is claimed as property: CLAIMS 1.- Procedure for the operation of a multi-stage counter in only one counting direction with the steps of: - variation of the value counting a one-stage counter-variable only in one counting direction with predetermined counting value states of the multistage counter; - acquisition of the corresponding count value states of the multistage counter and the one-stage counter-aid; - comparison of the values of the counting value states captured from the one-stage counter and the multi-stage counter; and - generation of an indicator signal based on the results of the comparison.
2. 2.- Procedure according to the claim 1, characterized in that, the indicator signal indicates the acceptance of the counting value of the multistage counter, if this is in a predetermined proportion to the counting value status of the one-stage counter.
3. 3. Method according to claim 2, characterized in that the indicating signal indicates the acceptance of the counting value of the multistage counter when the counting value of the multi-stage counter coincides with the counting value of the counter of one stage.
4. 4. - Switching arrangement to carry out the procedure according to one of claims 1 to 3, characterized in that, a multistage counter that; it only counts upwards or downwards, in which the count value of a stage by varying a counting value of the next stage is returned to an initial value, a one-stage auxiliary counter, which can only work counting towards up or down, and in which the predetermined counting values of the multistage counter vary, and a comparison device which is connected in such a way with the multi-stage counter and with the auxiliary counter, that the count values of the two counters each time compare them and produce a signal corresponding to the comparison.