MX9504950A - Sistema implementado para expulsion selectiva para prioridades de espacio en un conmutador de modo de transferencia asincrona de memoria compartida. - Google Patents

Sistema implementado para expulsion selectiva para prioridades de espacio en un conmutador de modo de transferencia asincrona de memoria compartida.

Info

Publication number
MX9504950A
MX9504950A MX9504950A MX9504950A MX9504950A MX 9504950 A MX9504950 A MX 9504950A MX 9504950 A MX9504950 A MX 9504950A MX 9504950 A MX9504950 A MX 9504950A MX 9504950 A MX9504950 A MX 9504950A
Authority
MX
Mexico
Prior art keywords
packet
packets
space
shared memory
stored
Prior art date
Application number
MX9504950A
Other languages
English (en)
Inventor
Abhijit Kumar Choudhury
Ellen Louise Hahne
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Publication of MX9504950A publication Critical patent/MX9504950A/es

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Packet switching elements characterised by the switching fabric construction
    • H04L49/104Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105ATM switching elements
    • H04L49/108ATM switching elements using shared central buffer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5638Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651Priority, marking, classes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5678Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681Buffer or queue management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Se describe un sistema y método para la formacion en fila o lista y expulsion selectiva, para un modulo de telecomunicaciones en paquete, tal como un conmutador de modo de transferencia asíncrono (ATM) de memoria compartida. La memoria compartida almacena paquetes en filas, cada paquete tiene un campo y a lo más dos indicadores. Dentro de cada fila, los paquetes que tienen respectivas prioridades de espacio son almacenados en subfilas, que tienen cada una las respectivas prioridades de espacio. Los paquetes son almacenados en estas subfilas de prioridad con el uso de un primer indicador, que apunta al siguiente paquete de la misma prioridad de espacio en la fila. El segundo indicador, asociado con un paquete almacenado, apunta el paquete previo de mayor o igual prioridad de espacio en el orden FIFO en la fila. El campo de un paquete es utilizado para almacenar el valor de prioridad correspondiente al siguiente paquete en orden FIFO en la fila, y este campo es utilizado por un procesador para decidir a qué subfilas de prioridad se debe dar servicio enseguida. Los paquetes son almacenados en las filas en un orden FIFO con el uso de los dos indicadores y los campos de los paquetes. El procesador controla la expulsion selectiva, para expulsar un paquete y utiliza los dos indicadores y los campos de los paquetes para restaurar el orden FIFO.
MX9504950A 1994-12-02 1995-11-28 Sistema implementado para expulsion selectiva para prioridades de espacio en un conmutador de modo de transferencia asincrona de memoria compartida. MX9504950A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/348,530 US5521916A (en) 1994-12-02 1994-12-02 Implementation of selective pushout for space priorities in a shared memory asynchronous transfer mode switch

Publications (1)

Publication Number Publication Date
MX9504950A true MX9504950A (es) 1997-01-31

Family

ID=23368434

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9504950A MX9504950A (es) 1994-12-02 1995-11-28 Sistema implementado para expulsion selectiva para prioridades de espacio en un conmutador de modo de transferencia asincrona de memoria compartida.

Country Status (6)

Country Link
US (1) US5521916A (es)
EP (1) EP0715436A3 (es)
JP (1) JPH08298522A (es)
KR (1) KR960027837A (es)
CA (1) CA2159528A1 (es)
MX (1) MX9504950A (es)

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Also Published As

Publication number Publication date
JPH08298522A (ja) 1996-11-12
KR960027837A (ko) 1996-07-22
CA2159528A1 (en) 1996-06-03
US5521916A (en) 1996-05-28
EP0715436A3 (en) 1997-10-22
EP0715436A2 (en) 1996-06-05

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