MX2021011705A - Aparato y metodo para transmision de datos y medio de almacenamiento legible. - Google Patents

Aparato y metodo para transmision de datos y medio de almacenamiento legible.

Info

Publication number
MX2021011705A
MX2021011705A MX2021011705A MX2021011705A MX2021011705A MX 2021011705 A MX2021011705 A MX 2021011705A MX 2021011705 A MX2021011705 A MX 2021011705A MX 2021011705 A MX2021011705 A MX 2021011705A MX 2021011705 A MX2021011705 A MX 2021011705A
Authority
MX
Mexico
Prior art keywords
transmission
controller
data
end processor
buffers
Prior art date
Application number
MX2021011705A
Other languages
English (en)
Inventor
Jinhua Shao
Jin Sun
Houli Duan
Qiong He
Shibo Sun
Original Assignee
Wuxi Hisky Medical Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Hisky Medical Tech Co Ltd filed Critical Wuxi Hisky Medical Tech Co Ltd
Publication of MX2021011705A publication Critical patent/MX2021011705A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

La presente solicitud provee un aparato, un método para transmisión de datos y un medio de almacenamiento legible, el aparato incluye un procesador de etapa inicial (101), un controlador de transmisión (102 y un procesador de etapa final (103); en el procesador de etapa inicial (101), un controlador DMA (1011) está conectado respectivamente con el controlador de transmisión (102), un controlador de memoria (1013), memorias intermedias de transmisión respectivas (1014, 1015) y un planificador de transmisión(1012), y el controlador de transmisión (102) y el planificador de transmisión (1012) están conectados respectivamente con las memorias intermedias de transmisión respectivas (1014, 1015); el controlador DMA (1011) está configurado para: recibir una solicitud para transmisión de datos enviada por el procesador de etapa final (103), recibir datos leídos desde el controlador de memoria (1013) y enviarlos hacia las memorias intermedias de transmisión (1014, 1015); el controlador de memoria (1013) está configurado para: controlar, de conformidad con la instrucción de lectura de datos, la memoria para leer datos y enviar los lados leídos hacia el controlador DMA (1011); el planificador de transmisión (1012) está configurado para: controlar múltiples memorias intermedias de transmisión (1014, 1015) para escribir datos enviados por el controlador DMA (1011), y controlar las múltiples memorias intermedias de transmisión (1014, 1015) para leer datos y transmitir, a través del controlador de transmisión (102); los datos hacia el procesador de etapa final (103); ejecutando transmisión rápida de datos masivos, se evita el consumo de grandes cantidades de recursos.
MX2021011705A 2019-03-27 2020-01-09 Aparato y metodo para transmision de datos y medio de almacenamiento legible. MX2021011705A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910237373.3A CN110008156B (zh) 2019-03-27 2019-03-27 数据传输的装置、方法及可读存储介质
PCT/CN2020/071106 WO2020192242A1 (zh) 2019-03-27 2020-01-09 数据传输的装置、方法及可读存储介质

Publications (1)

Publication Number Publication Date
MX2021011705A true MX2021011705A (es) 2021-10-22

Family

ID=67168369

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2021011705A MX2021011705A (es) 2019-03-27 2020-01-09 Aparato y metodo para transmision de datos y medio de almacenamiento legible.

Country Status (9)

Country Link
US (1) US11803490B2 (es)
EP (1) EP3951605B1 (es)
JP (1) JP7236173B2 (es)
CN (1) CN110008156B (es)
AU (1) AU2020249861B2 (es)
BR (1) BR112021019106A2 (es)
CA (1) CA3134888A1 (es)
MX (1) MX2021011705A (es)
WO (1) WO2020192242A1 (es)

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Also Published As

Publication number Publication date
AU2020249861A1 (en) 2021-10-28
CN110008156B (zh) 2020-12-15
CN110008156A (zh) 2019-07-12
BR112021019106A2 (pt) 2021-11-30
WO2020192242A1 (zh) 2020-10-01
CA3134888A1 (en) 2020-10-01
AU2020249861B2 (en) 2023-09-21
US20220012194A1 (en) 2022-01-13
JP7236173B2 (ja) 2023-03-09
EP3951605B1 (en) 2024-06-05
EP3951605A4 (en) 2022-11-30
JP2022527907A (ja) 2022-06-07
EP3951605A1 (en) 2022-02-09
US11803490B2 (en) 2023-10-31
KR20210134965A (ko) 2021-11-11

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