BR112021019106A2 - Aparelho para transmissão de dados, método para transmissão de dados e meio de armazenamento legível por computador - Google Patents

Aparelho para transmissão de dados, método para transmissão de dados e meio de armazenamento legível por computador

Info

Publication number
BR112021019106A2
BR112021019106A2 BR112021019106A BR112021019106A BR112021019106A2 BR 112021019106 A2 BR112021019106 A2 BR 112021019106A2 BR 112021019106 A BR112021019106 A BR 112021019106A BR 112021019106 A BR112021019106 A BR 112021019106A BR 112021019106 A2 BR112021019106 A2 BR 112021019106A2
Authority
BR
Brazil
Prior art keywords
transmission
data
controller
data transmission
storage medium
Prior art date
Application number
BR112021019106A
Other languages
English (en)
Inventor
Houli Duan
Jin Sun
Jinhua Shao
Qiong He
Shibo Sun
Original Assignee
Wuxi Hisky Medical Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Hisky Medical Tech Co Ltd filed Critical Wuxi Hisky Medical Tech Co Ltd
Publication of BR112021019106A2 publication Critical patent/BR112021019106A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

aparelho para transmissão de dados, método para transmissão de dados e meio de armazenamento legível por computador. o presente pedido fornece um aparelho, um método para transmissão de dados e um meio de armazenamento legível, o aparelho inclui um processador de parte dianteira (101), um controlador de transmissão (102) e um processador de parte traseira (103). no processador de parte dianteira (101), um controlador de dma (1011) é respectivamente conectado com o controlador de transmissão (102), um controlador de memória (1013), respectivos buffers de transmissão e um programador de transmissão (1012), e o controlador de transmissão (102) e o programador de transmissão (1012) estão respectivamente conectados aos respectivos buffers de transmissão . o controlador de dma (1011) é configurado para: receber uma solicitação de transmissão de dados enviada pelo processador de parte traseira (103), receber dados lidos do controlador de memória e enviá-los para os buffers de transmissão . o controlador de memória é configurado para: controlar, de acordo com uma instrução de leitura de dados, a memória para ler dados e enviar os dados lidos para o controlador de dma (1011). o programador de transmissão (1012) é configurado para: controlar múltiplos buffers de transmissão para gravar dados enviados pelo controlador de dma (1011) e controlar os múltiplos buffers de transmissão para ler dados e transmitir, por meio do controlador de transmissão (102), os dados para o processador de parte traseira (103). ao realizar a transmissão rápida de grande volume de dados, evita-se o consumo de grandes quantidades de recursos.
BR112021019106A 2019-03-27 2020-01-09 Aparelho para transmissão de dados, método para transmissão de dados e meio de armazenamento legível por computador BR112021019106A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910237373.3A CN110008156B (zh) 2019-03-27 2019-03-27 数据传输的装置、方法及可读存储介质
PCT/CN2020/071106 WO2020192242A1 (zh) 2019-03-27 2020-01-09 数据传输的装置、方法及可读存储介质

Publications (1)

Publication Number Publication Date
BR112021019106A2 true BR112021019106A2 (pt) 2021-11-30

Family

ID=67168369

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112021019106A BR112021019106A2 (pt) 2019-03-27 2020-01-09 Aparelho para transmissão de dados, método para transmissão de dados e meio de armazenamento legível por computador

Country Status (10)

Country Link
US (1) US11803490B2 (pt)
EP (1) EP3951605B1 (pt)
JP (1) JP7236173B2 (pt)
KR (1) KR20210134965A (pt)
CN (1) CN110008156B (pt)
AU (1) AU2020249861B2 (pt)
BR (1) BR112021019106A2 (pt)
CA (1) CA3134888A1 (pt)
MX (1) MX2021011705A (pt)
WO (1) WO2020192242A1 (pt)

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CN117112465A (zh) * 2023-10-16 2023-11-24 北京象帝先计算技术有限公司 Dma调度器及方法、片上系统、电子组件及设备

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Also Published As

Publication number Publication date
EP3951605A1 (en) 2022-02-09
CN110008156B (zh) 2020-12-15
EP3951605B1 (en) 2024-06-05
US11803490B2 (en) 2023-10-31
CN110008156A (zh) 2019-07-12
AU2020249861B2 (en) 2023-09-21
EP3951605A4 (en) 2022-11-30
CA3134888A1 (en) 2020-10-01
AU2020249861A1 (en) 2021-10-28
JP2022527907A (ja) 2022-06-07
MX2021011705A (es) 2021-10-22
WO2020192242A1 (zh) 2020-10-01
US20220012194A1 (en) 2022-01-13
KR20210134965A (ko) 2021-11-11
JP7236173B2 (ja) 2023-03-09

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