MX2017010996A - Aparato de relleno con ceros para codificar la informacion de señalizacion de longitud variable y metodo de relleno con ceros que lo utiliza. - Google Patents
Aparato de relleno con ceros para codificar la informacion de señalizacion de longitud variable y metodo de relleno con ceros que lo utiliza.Info
- Publication number
- MX2017010996A MX2017010996A MX2017010996A MX2017010996A MX2017010996A MX 2017010996 A MX2017010996 A MX 2017010996A MX 2017010996 A MX2017010996 A MX 2017010996A MX 2017010996 A MX2017010996 A MX 2017010996A MX 2017010996 A MX2017010996 A MX 2017010996A
- Authority
- MX
- Mexico
- Prior art keywords
- zero padding
- bit string
- signaling information
- groups
- length
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 230000011664 signaling Effects 0.000 title abstract 2
- 238000004904 shortening Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Multimedia (AREA)
- Computer Networks & Wireless Communication (AREA)
- Error Detection And Correction (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Se describe un aparato y método de relleno con ceros para información de señalización de longitud variable; un aparato de relleno con ceros de acuerdo con una modalidad de la presente invención incluye un procesador configurado para generar una cadena de bits de información LDPC al escoger un número de grupos cuyos bits se van a llenar con 0 usando una diferencia entre una longitud de la cadena de bits de información LDPC y una longitud de una cadena de bits codificada por BCH, seleccionar los grupos que utilizan un orden de patrón de acortamiento para rellenar todos los bits de los grupos con 0 y rellenar al menos una parte de los grupos restantes que no están llenos con 0 con la cadena de bits codificada por BCH; y una memoria configurada para proporcionar la cadena de bits de información LDPC a un codificador LDPC.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20150028063 | 2015-02-27 | ||
| KR1020160020867A KR102453475B1 (ko) | 2015-02-27 | 2016-02-22 | 가변 길이 시그널링 정보 부호화를 위한 제로 패딩 장치 및 이를 이용한 제로 패딩 방법 |
| PCT/KR2016/001758 WO2016137205A1 (ko) | 2015-02-27 | 2016-02-23 | 가변 길이 시그널링 정보 부호화를 위한 제로 패딩 장치 및 이를 이용한 제로 패딩 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| MX2017010996A true MX2017010996A (es) | 2017-10-18 |
| MX370802B MX370802B (es) | 2020-01-07 |
Family
ID=56946141
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2017010996A MX370802B (es) | 2015-02-27 | 2016-02-23 | Aparato de relleno con ceros para codificar la información de señalización de longitud variable y método de relleno con ceros que lo utiliza. |
| MX2019015682A MX2019015682A (es) | 2015-02-27 | 2017-08-25 | Aparato de relleno con ceros para codificar la informacion de se?alizacion de longitud variable y metodo de relleno con ceros que lo utiliza. |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2019015682A MX2019015682A (es) | 2015-02-27 | 2017-08-25 | Aparato de relleno con ceros para codificar la informacion de se?alizacion de longitud variable y metodo de relleno con ceros que lo utiliza. |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US10298260B2 (es) |
| KR (2) | KR102453475B1 (es) |
| CA (1) | CA2977623C (es) |
| MX (2) | MX370802B (es) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA3065452C (en) | 2015-02-27 | 2022-05-17 | Electronics And Telecommunications Research Institute | Zero padding apparatus for encoding fixed-length signaling information and zero padding method using same |
| KR102453472B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법 |
| KR102453476B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
| WO2016137204A1 (ko) | 2015-02-27 | 2016-09-01 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 패리티 인터리빙 장치 및 이를 이용한 패리티 인터리빙 방법 |
| KR102453471B1 (ko) * | 2015-02-27 | 2022-10-14 | 한국전자통신연구원 | 고정 길이 시그널링 정보 부호화를 위한 제로 패딩 장치 및 이를 이용한 제로 패딩 방법 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8266508B2 (en) | 2007-06-08 | 2012-09-11 | Telefonaktiebolaget L M Ericsson (Publ) | Computational efficient convolutional coding with rate matching |
| KR101503058B1 (ko) | 2008-02-26 | 2015-03-18 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치 |
| EP2477335B1 (en) * | 2011-01-18 | 2019-05-29 | Samsung Electronics Co., Ltd. | Apparatus and method for transmitting and reveiving data in communication/broadcasting system |
| KR101791477B1 (ko) | 2011-10-10 | 2017-10-30 | 삼성전자주식회사 | 통신/방송 시스템에서 데이터 송수신 장치 및 방법 |
| KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| KR20150005426A (ko) | 2013-07-05 | 2015-01-14 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| US10305632B2 (en) | 2013-09-17 | 2019-05-28 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
| CA3065452C (en) | 2015-02-27 | 2022-05-17 | Electronics And Telecommunications Research Institute | Zero padding apparatus for encoding fixed-length signaling information and zero padding method using same |
-
2016
- 2016-02-22 KR KR1020160020867A patent/KR102453475B1/ko active IP Right Grant
- 2016-02-23 CA CA2977623A patent/CA2977623C/en active Active
- 2016-02-23 US US15/553,908 patent/US10298260B2/en active Active
- 2016-02-23 MX MX2017010996A patent/MX370802B/es active IP Right Grant
-
2017
- 2017-08-25 MX MX2019015682A patent/MX2019015682A/es unknown
-
2019
- 2019-03-21 US US16/360,409 patent/US10812105B2/en active Active
-
2024
- 2024-02-07 KR KR1020240018999A patent/KR20240024869A/ko active Search and Examination
Also Published As
| Publication number | Publication date |
|---|---|
| KR20240024869A (ko) | 2024-02-26 |
| CA2977623C (en) | 2020-02-25 |
| MX370802B (es) | 2020-01-07 |
| US20180041226A1 (en) | 2018-02-08 |
| US10298260B2 (en) | 2019-05-21 |
| MX2019015682A (es) | 2020-02-26 |
| US20190229750A1 (en) | 2019-07-25 |
| CA2977623A1 (en) | 2016-09-01 |
| US10812105B2 (en) | 2020-10-20 |
| KR102453475B1 (ko) | 2022-10-14 |
| KR20160105312A (ko) | 2016-09-06 |
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