MX2009010345A - Concordancia de velocidad basada en memoria intermedia circular. - Google Patents

Concordancia de velocidad basada en memoria intermedia circular.

Info

Publication number
MX2009010345A
MX2009010345A MX2009010345A MX2009010345A MX2009010345A MX 2009010345 A MX2009010345 A MX 2009010345A MX 2009010345 A MX2009010345 A MX 2009010345A MX 2009010345 A MX2009010345 A MX 2009010345A MX 2009010345 A MX2009010345 A MX 2009010345A
Authority
MX
Mexico
Prior art keywords
bits
parity
circular buffer
systematic
rate matching
Prior art date
Application number
MX2009010345A
Other languages
English (en)
Inventor
Juan Montojo
Yongbin Wei
Durga Prasad Malladi
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2009010345A publication Critical patent/MX2009010345A/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Se describen sistemas y metodologías que facilitan el empleo de una concordancia de velocidad basada en memoria intermedia circular; los bloques codificados que incluyen bits sistemáticos, de paridad 1 y paridad 2 pueden ser generados utilizando un código turbo; el tipo de bit puede ser identificado para separar bits en distintos grupos; los bits sistemáticos pueden ser intercalados juntos para generar una secuencia aleatorizada de bits sistemáticos, los bits de paridad 1 pueden ser intercalados juntos para producir una secuencia aleatorizada de bits de paridad 1, y los bits de paridad 2 pueden ser intercalados juntos para emitir una secuencia aleatorizada de bits de paridad 2; las secuencias aleatorizadas de bits de paridad 1 y paridad 2 pueden ser entrelazadas juntas en una manera de alternación; la secuencia aleatorizada de los bits sistemáticos puede ser insertada en una memoria intermedia circular, y al momento de insertar toda la secuencia, los bits de paridad entrelazados pueden ser insertados en la memoria intermedia circular (por ejemplo, hasta alcanzar la capacidad); los bits insertados en la memoria intermedia son transmitidos.
MX2009010345A 2007-03-27 2008-03-27 Concordancia de velocidad basada en memoria intermedia circular. MX2009010345A (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US90840207P 2007-03-27 2007-03-27
US12/055,195 US8726121B2 (en) 2007-03-27 2008-03-25 Circular buffer based rate matching
PCT/US2008/058500 WO2008119048A2 (en) 2007-03-27 2008-03-27 Circular buffer based rate matching

Publications (1)

Publication Number Publication Date
MX2009010345A true MX2009010345A (es) 2009-10-19

Family

ID=39789279

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009010345A MX2009010345A (es) 2007-03-27 2008-03-27 Concordancia de velocidad basada en memoria intermedia circular.

Country Status (14)

Country Link
US (1) US8726121B2 (es)
EP (1) EP2145414A2 (es)
JP (1) JP5479317B2 (es)
KR (1) KR101201461B1 (es)
CN (1) CN105610551A (es)
AU (1) AU2008230783B2 (es)
BR (1) BRPI0809365A2 (es)
CA (1) CA2679826A1 (es)
IL (1) IL200597A0 (es)
MX (1) MX2009010345A (es)
NZ (1) NZ579312A (es)
RU (1) RU2442285C2 (es)
TW (1) TWI382706B (es)
WO (1) WO2008119048A2 (es)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7293217B2 (en) * 2002-12-16 2007-11-06 Interdigital Technology Corporation Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes
US9686044B2 (en) 2007-03-27 2017-06-20 Qualcomm Incorporated Rate matching with multiple code block sizes
WO2008151061A1 (en) * 2007-05-31 2008-12-11 Interdigital Technology Corporation Channel coding and rate matching for lte control channels
US8189559B2 (en) * 2007-07-23 2012-05-29 Samsung Electronics Co., Ltd. Rate matching for hybrid ARQ operations
US7986741B2 (en) * 2007-09-28 2011-07-26 Samsung Electronics Co., Ltd. Method and apparatus of improved circular buffer rate matching for turbo-coded MIMO-OFDM wireless systems
KR20090036534A (ko) * 2007-10-09 2009-04-14 엘지전자 주식회사 성상 재배열을 이용한 데이터 전송 방법
CN101741527B (zh) * 2008-11-27 2013-03-27 中兴通讯股份有限公司 速率匹配方法和装置
US8737503B2 (en) * 2009-03-17 2014-05-27 Futurewei Technologies, Inc. System and method for multiple input, multiple output layer mapping
CN101510819B (zh) * 2009-04-08 2011-09-14 华为技术有限公司 速率匹配方法及装置
EP2485420A4 (en) * 2009-09-30 2014-10-08 Fujitsu Ltd DATA TRANSMISSION APPARATUS, DATA GENERATION PROGRAM, AND DATA TRANSMITTING / RECEIVING METHOD
CN102075285B (zh) * 2009-11-25 2013-06-05 中兴通讯股份有限公司 一种速率匹配方法及装置
US8291136B2 (en) 2009-12-02 2012-10-16 International Business Machines Corporation Ring buffer
EP2461511A4 (en) * 2010-01-04 2014-01-22 Zte Corp SERIAL PROCESSING METHOD, BIT RATE MATCHING PARALLEL PROCESSING METHOD, AND DEVICE THEREOF
US8537755B2 (en) * 2010-05-11 2013-09-17 Qualcomm Incorporated Rate matching device
TW201141078A (en) * 2010-05-14 2011-11-16 Nat Univ Chung Cheng Method of handling packet loss using error-correcting codes and block rearrangement
EA201401072A1 (ru) * 2012-04-27 2015-03-31 Общество С Ограниченной Ответственностью "Научно-Инновационный Центр "Мэйзер" Способ защиты цифровой информации
US9424126B2 (en) * 2013-09-03 2016-08-23 Kabushiki Kaisha Toshiba Memory controller
BR112016021434A2 (pt) * 2014-03-19 2017-08-15 Huawei Tech Co Ltd Método de equiparação de taxa de código polar e aparelho de equiparação de taxa
WO2016017052A1 (ja) * 2014-07-29 2016-02-04 日本電気株式会社 キャリアアグリゲーションでのダウンリンクｈａｒｑプロセスを処理するための方法及び装置
JP6468526B2 (ja) * 2014-11-27 2019-02-13 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Ｐｏｌａｒ符号レートマッチング方法および装置、ならびに無線通信デバイス
EP3523905A1 (en) * 2016-10-07 2019-08-14 IDAC Holdings, Inc. Rate matching and harq with irregular modulation
CN108288966B (zh) 2017-01-09 2022-11-18 中兴通讯股份有限公司 极性Polar码的速率匹配处理方法及装置
WO2018146629A1 (en) * 2017-02-10 2018-08-16 Telefonaktiebolaget Lm Ericsson (Publ) Circular buffer rate matching for polar codes
US10348329B2 (en) * 2017-02-13 2019-07-09 Qualcomm Incorporated Low density parity check (LDPC) circular buffer rate matching
WO2018176003A1 (en) * 2017-03-23 2018-09-27 Intel Corporation Flexible information block size support for polar code
US10873347B2 (en) 2017-08-07 2020-12-22 Mediatek Inc. Channel bit interleaver design for polar coding chain
US10579293B2 (en) * 2017-09-27 2020-03-03 Aci Worldwide Corp. System and computer-implemented method for improving data storage and analysis
KR102541319B1 (ko) * 2018-03-29 2023-06-08 삼성전자주식회사 무선 통신 시스템에서 극 부호를 이용한 부호화 및 복호화를 위한 장치 및 방법
WO2020199225A1 (en) * 2019-04-05 2020-10-08 Qualcomm Incorporated Rate matching for different transmission modes

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9814960D0 (en) 1998-07-10 1998-09-09 Koninkl Philips Electronics Nv Coding device and communication system using the same
US6298463B1 (en) * 1998-07-31 2001-10-02 Nortel Networks Limited Parallel concatenated convolutional coding
US6748481B1 (en) 1999-04-06 2004-06-08 Microsoft Corporation Streaming information appliance with circular buffer for receiving and selectively reading blocks of streaming information
CA2268853C (en) 1999-04-13 2011-08-02 Wen Tong Rate matching and channel interleaving for a communications system
US6985537B1 (en) 1999-09-15 2006-01-10 Lucent Technologies Inc. Symbol self synchronous interleaving method and apparatus for OFDM-based communication system
US6977897B1 (en) * 2000-05-08 2005-12-20 Crossroads Systems, Inc. System and method for jitter compensation in data transfers
CA2405119C (en) 2001-02-13 2007-09-11 Samsung Electronics Co., Ltd. Apparatus and method for generating codes in communication system
KR100918765B1 (ko) 2001-10-20 2009-09-24 삼성전자주식회사 부호분할다중접속 이동통신시스템에서 부호화 및 레이트매칭장치 및 방법
US7000173B2 (en) 2002-02-11 2006-02-14 Motorola, Inc. Turbo code based incremental redundancy
US7293217B2 (en) 2002-12-16 2007-11-06 Interdigital Technology Corporation Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes
KR100770902B1 (ko) 2004-01-20 2007-10-26 삼성전자주식회사 고속 무선 데이터 시스템을 위한 가변 부호율의 오류 정정부호 생성 및 복호 장치 및 방법
JP4488810B2 (ja) * 2004-06-30 2010-06-23 富士通株式会社 通信システム及び受信方法
KR100594043B1 (ko) * 2004-11-08 2006-06-30 삼성전자주식회사 고속 터보 디코더에서 병행방식의 디 래이트 매칭을수행하는 입력 버퍼 장치
KR100860504B1 (ko) * 2005-06-09 2008-09-26 삼성전자주식회사 이동통신 시스템에서 송수신 장치 및 방법
RU2008107716A (ru) * 2005-08-30 2009-09-10 Самсунг Электроникс Ко., Лтд. (KR) Устройство и способ передачи и приема данных в системе множественного доступа с частотным разделением и система для этого
US20080016425A1 (en) * 2006-04-04 2008-01-17 Qualcomm Incorporated Turbo decoder with symmetric and non-symmetric decoding rates
EP2100385A4 (en) 2007-01-05 2012-07-25 Lg Electronics Inc METHODS OF LAYER MAPPING AND DATA TRANSMISSION FOR MIMO SYSTEM
EP2259527A3 (en) 2007-02-02 2011-02-16 Research In Motion Limited Multi carrier apparatus and method for communicating a data block with a PAPR reduction identification sequence superimposed thereon

Also Published As

Publication number Publication date
WO2008119048A3 (en) 2009-01-15
TWI382706B (zh) 2013-01-11
KR101201461B1 (ko) 2012-11-14
KR20090123019A (ko) 2009-12-01
WO2008119048A2 (en) 2008-10-02
EP2145414A2 (en) 2010-01-20
BRPI0809365A2 (pt) 2014-09-16
TW200913557A (en) 2009-03-16
RU2009139652A (ru) 2011-05-20
RU2442285C2 (ru) 2012-02-10
IL200597A0 (en) 2010-05-17
CA2679826A1 (en) 2008-10-02
NZ579312A (en) 2012-01-12
JP5479317B2 (ja) 2014-04-23
CN105610551A (zh) 2016-05-25
US20090049359A1 (en) 2009-02-19
JP2010523064A (ja) 2010-07-08
US8726121B2 (en) 2014-05-13
AU2008230783B2 (en) 2011-10-13
AU2008230783A1 (en) 2008-10-02

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