LU503319B1 - Stabilizer circuit with frequency compensation circuit adapting to load changes - Google Patents

Stabilizer circuit with frequency compensation circuit adapting to load changes Download PDF

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Publication number
LU503319B1
LU503319B1 LU503319A LU503319A LU503319B1 LU 503319 B1 LU503319 B1 LU 503319B1 LU 503319 A LU503319 A LU 503319A LU 503319 A LU503319 A LU 503319A LU 503319 B1 LU503319 B1 LU 503319B1
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LU
Luxembourg
Prior art keywords
mos tube
circuit
stage
drain
adapting
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Application number
LU503319A
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German (de)
Inventor
Ye Lin
Yijie Zhang
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Jingsu Huachuang Microsystem Company Ltd
Nanjing Research Institute Of Electronics Tech
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Priority to LU503319A priority Critical patent/LU503319B1/en
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Publication of LU503319B1 publication Critical patent/LU503319B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/153—Feedback used to stabilise the amplifier

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The present invention discloses a stabilizer circuit with a frequency compensation circuit adapting to load changes, comprising: a first-stage amplification circuit, a second-stage amplification circuit, an output-stage circuit, and a frequency compensation circuit adapting to load changes, a frequency compensation circuit adapting to load changes, comprises a compensation capacitor C1, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, and a ninth MOS tube M9, wherein an output terminal of the first-stage amplification circuit is connected to an input terminal of a second-stage circuit, an output terminal of the second-stage circuit is connected to the output-stage circuit, and the frequency compensation circuit adapting to load changes is connected between a second-stage input terminal and a second-stage output terminal. Advantages: Compared with a circuit in which a fixed resistance is used as pole-zero point compensation, the circuit in the present invention uses a MOS tube as an adjustable resistance, and a proper adjustment relationship is created between the circuit and the load current, so that the circuit can automatically adjust the pole-zero point frequency when the load current changes. Therefore, the system can operate stably in different load current conditions, and the premise for a larger current is provided.

Description

BL-5567
LU503319
STABILIZER CIRCUIT WITH FREQUENCY COMPENSATION
CIRCUIT ADAPTING TO LOAD CHANGES
TECHNICAL FIELD
The present invention relates to the field of chip design technologies, and specifically, to a stabilizer circuit with a frequency compensation circuit adapting to load changes that is applied to a floating point multiplier-adder.
BACKGROUND
Negative feedbacks are widely used in analog signal processing because the nature of feedbacks enables the system to work precisely by suppressing changes in open-loop performance. A negative feedback system is shown in FIG 1.
A feedback system produces oscillation at a frequency ® when: (1) at the ® frequency, a phase shift around a loop can be large enough to turn a negative feedback into a positive feedback, and (2) a loop gain is sufficient to generate a signal (to be specific, the loop gain is greater than or equal to 1). Therefore, to avoid instability, the total phase shift needs to be reduced to the minimum, so that when the loop gain amplitude is equal to 1, /ßH is still greater than —80°. FIG 2 and FIG 3 are respectively Bode diagrams of a stable system and an unstable system.
A system is unstable if there is a pole on a right half plane of an open-loop transfer function of a system in the s-domain. If a pole and a zero point only exist on a left half plane, the stability of the system further needs to be analyzed in the Bode diagram.
In the Bode diagram, the gain curve drops at —20dB/10 octave slope at a pole, and rises at 20dB/10 octave slope at a zero point. The phase curve starts to drop at the 0.1&p frequency and completes a —90° phase change at the 10wp frequency. At a zero point, if the zero point is on the left half plane, the phase curve starts to rise at the 0.1®z frequency and completes a 90° phase change at the 10wz frequency. At a zero point on the right half plane, the phase curve drops at —45° slope, and finally completes a —90° phase change.
For the feedback system in the linear stabilizer circuit structure shown in FIG 4, the conventional frequency compensation manner is to provide a resistor structure (C1, R1) between a first-stage operational amplifier output terminal and the ground as the pole-zero 1
BL-5567 compensation pair to compensate for stability of the feedback system. HUS033T9
Without pole-zero compensation, simple analysis shows that due to the large load capacitance, pole P1 of the output stage is set to a main pole, that is, the pole with the lowest frequency. A first-stage amplification circuit has a large gain, that is, a large transconductance.
Therefore, pole P2 of the first-stage amplification circuit is set to a secondary pole, that is, a pole with the second lowest frequency. The remaining poles have very high frequencies and do not affect the system stability, and therefore, are omitted herein. The main pole and the secondary pole cause a total of a —180° phase shift. In addition, frequencies of the two poles are low and close, which results in a —180° phase shift in a very narrow frequency. Consequently. the system is unstable. In this case, the gain curve is shown in FIG 5.
When pole-zero point compensation is performed by using C1 and R, a new pole P and a new zero point Z on the left half plane are introduced between P1 and P2 from C1 and R1. In this case, the gain curve is shown in FIG 6. It can be learned through analysis that the gain can decrease to 0 dB more quickly. Although the bandwidth is reduced, the system is more stable.
Although the pole-zero point can be compensated for by using the foregoing technology, the system becomes unstable when the load changes. For example, when the load current increases, it can be learned based on the pole frequency of P1 that the load current increases when the transconductance of the power tube increases, and P1 moves toward the direction with higher frequency. However, when the load current changes, the compensation pole-zero point does not move. Consequently, the pole-zero compensation pair cannot perform compensation effectively, the gain can decrease to 0 dB only at a higher frequency, and the circuit becomes unstable when the load current changes.
SUMMARY
The present invention mainly resolves a problem that a pole moves due to changes of load currents, but a compensation pole-zero point cannot move with the pole based on the changes of the load currents, and further resolves the problems that the stability of a system decreases due to invalid compensation of a pole-zero point pair and a load capacity of the system is limited.
The present invention provides a stabilizer circuit with a frequency compensation circuit adapting to load changes. The technical solutions are as follows: 2
BL-5567
A frequency compensation circuit adapting to load changes includes: a first-stage amplification circuit, a second-stage amplification circuit, an output-stage circuit, and a frequency compensation circuit adapting to load changes that comprises a compensation capacitor C1, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, and a ninth MOS tube M9, wherein an output terminal of the first-stage amplification circuit is connected to an input terminal of a second-stage circuit, an output terminal of the second-stage circuit is connected to the output-stage circuit, and the frequency compensation circuit adapting to load changes is connected between a second-stage input terminal and a second-stage output terminal; the sixth MOS tube M6 and the seventh MOS tube M7 are P-type MOS tubes, and the eighth MOS tube M8 and the ninth MOS tube M9 are N-type MOS tubes; and the input terminal of the second-stage amplification circuit is connected to one terminal of the compensation capacitor C1 in the frequency compensation circuit adapting to load changes, the second-stage output terminal is connected to a drain and a gate of the sixth MOS tube M6 and a gate of the seventh MOS tube M7, and sources of both the seventh MOS tube M7 and the sixth MOS tube M6 are connected to a power supply VDD; a drain of the seventh MOS tube
M7 is connected to a drain and a gate of the eighth MOS tube M8 and a gate of the ninth MOS tube MO, a drain of the ninth MOS tube M9 is connected to the output terminal of the first-stage amplification circuit after being connected to the compensation capacitor Cl in series; and sources of both the eighth MOS tube M8 and the ninth MOS tube M9 are grounded.
In the stabilizer circuit in the present invention, resistances of a compensation capacitor C1 and a ninth MOS tube M9 are used as a pole-zero compensation pair of a circuit, changes of load currents are reflected on voltages of point C (which is a node connected to an output terminal of a second-stage amplification circuit), and then are reflected on voltages of point F (which is a node connected to a drain of a seventh MOS tube M7) by a current mirror to control the resistance of the ninth MOS tube M9, so that the pole-zero point compensation frequency changes with the load, where the voltages of point F are gate voltages of the ninth MOS tube
M9. 3
BL-5567
A further defined technical solution of the stabilizer circuit with a frequency compensition 9 circuit adapting to load changes of the present invention is as follows:
The first-stage amplification circuit comprises a first MOS tube M1, a second MOS tube
M2, a third MOS tube M3, a fourth MOS tube M4, and a tail current source; the power supply
VDD is connected to sources of both the first MOS tube M1 and the second MOS tube M2 through the tail current source, the source of the first MOS tube M1 is connected to the source of the second MOS tube M2, and the first MOS tube M1 and the second MOS tube M2 are
P-type MOS tubes; a gate of the third MOS tube M3 is connected to a gate of the fourth MOS tube M4, the third MOS tube M3 and the fourth MOS tube M4 are N-type MOS tubes, and sources of both the third MOS tube M3 and the fourth MOS tube M4 are grounded; a drain of the first MOS tube M1 is connected to a drain of the third MOS tube M3, a first node A is provided on a connection line between the drain of the first MOS tube M1 and the drain of the third MOS tube M3, and a circuit led out from the node A is connected to the gates of the third
MOS tube M3 and the fourth MOS tube M4; and a drain of the second MOS tube M2 is connected to a drain of the fourth MOS tube M4, a second node B is provided on a connection line between the drains of the second MOS tube M2 and the fourth MOS tube M4, and the second node B is connected to the output terminal of the first-stage amplification circuit.
A gate of the first MOS tube M1 receives the reference voltage, and a gate of the second
MOS tube M2 receives a feedback voltage FBOUT, wherein the feedback voltage FBOUT is generated by the output-stage circuit.
The second-stage amplification circuit comprises a fifth MOS tube M5, a resistor R2, and a resistor R3, the fifth MOS tube M5 is an N-type MOS tube, a gate of the fifth MOS tube MS is connected to the output terminal of the first-stage amplification circuit, a source of the fifth
MOS tube M5 is grounded after being connected to the resistor R3 in series, and a drain of the fifth MOS tube M5 is connected to the power supply VDD after being connected to the resistor
R2, and the drain of the fifth MOS tube M5 is connected to the output-stage circuit.
Compared with a conventional technology, the present invention has the following beneficial effects: 4
BL-5567
Compared with a circuit in which a fixed resistance is used as pole-zero por 9 compensation, the circuit in the present invention uses a MOS tube as an adjustable resistance, and a proper adjustment relationship is created between the circuit and the load current, so that the circuit can automatically adjust the pole-zero point frequency when the load current changes.
Therefore, the system can operate stably in different load current conditions, and the premise for a larger current is provided.
BRIEF DESCRIPTION OF DRAWINGS
FIG 1 is a circuit diagram of a basic negative feedback system.
FIG 2 is a Bode diagram of a stable system.
FIG 3 is a Bode diagram of an unstable system.
FIG 4 is a circuit diagram of a conventional frequency compensation manner of a feedback system in a linear stabilizer circuit structure.
FIG 5 is an amplitude frequency diagram showing that pole-zero point compensation is not performed.
FIG 6 is an amplitude frequency diagram showing that normal pole-zero point compensation is performed.
FIG 7 is a circuit diagram of a stabilizer circuit with a frequency compensation circuit adapting to load changes according to the present invention.
FIG 8 is an amplitude frequency diagram showing of follow compensation when load currents of the stabilizer circuit change according to the present invention.
DESCRIPTION OF EMBODIMENTS
To make the present invention more comprehensible, specific embodiments are described below with reference to FIG 1 to FIG 8 and specific implementations.
As shown in FIG 7, a stabilizing circuit with a frequency compensation circuit that adapts to load changes in this embodiment, includes: a first-stage amplification circuit, a second-stage amplification circuit, an output-stage circuit, and a frequency compensation circuit adapting to load changes that comprises a compensation capacitor C1, a sixth MOS tube M6, a seventh
MOS tube M7, an eighth MOS tube M8, and a ninth MOS tube M9, wherein an output terminal of the first-stage amplification circuit is connected to an input terminal of a second-stage circuit, 5
BL-5567 an output terminal of the second-stage circuit is connected to the output-stage circuit, and ds frequency compensation circuit adapting to load changes is connected between a second-stage input terminal and a second-stage output terminal.
As shown in FIG8, the sixth MOS tube M6 and the seventh MOS tube M7 are P-type
MOS tubes, and the eighth MOS tube M8 and the ninth MOS tube M9 are N-type MOS tubes; the input terminal of the second-stage amplification circuit is connected to one terminal of the compensation capacitor C1 in the frequency compensation circuit adapting to load changes, the second-stage output terminal is connected to a drain and a gate of the sixth MOS tube M6 and a gate of the seventh MOS tube M7, and sources of both the seventh MOS tube M7 and the sixth
MOS tube M6 are connected to a power supply VDD; a drain of the seventh MOS tube M7 is connected to a drain and a gate of the eighth MOS tube M8 and a gate of the ninth MOS tube
M9, a drain of the ninth MOS tube M9 is connected to the output terminal of the first-stage amplification circuit after being connected to the compensation capacitor Cl in series; and sources of both the eighth MOS tube M8 and the ninth MOS tube M9 are grounded.
In this embodiment, a fixed resistor R1 used in a conventional method is replaced with a
MOS tube resistor controlled by a gate voltage related to the load current, as shown in FIG 7.
Resistances of a compensation capacitor C1 and a ninth MOS tube M9 are used as a pole-zero compensation pair of a circuit. Changes of load currents are reflected on voltages of point C, and then are reflected on voltages of point F by a current mirror to control the resistance of the ninth MOS tube MO.
In this embodiment, a first-stage amplification circuit, a second-stage amplification circuit, and an output-stage circuit are known circuits in this technical field.
As shown in FIG7, in this embodiment, the first-stage amplification circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, and atail current source; the power supply VDD is connected to sources of both the first MOS tube
M1 and the second MOS tube M2 through the tail current source, the source of the first MOS tube M1 is connected to the source of the second MOS tube M2, and the first MOS tube M1 and the second MOS tube M2 are P-type MOS tubes; a gate of the third MOS tube M3 is connected 6
BL-5567 to a gate of the fourth MOS tube M4, the third MOS tube M3 and the fourth MOS tube MA a 9
N-type MOS tubes, and sources of both the third MOS tube M3 and the fourth MOS tube M4 are grounded; a drain of the first MOS tube M1 is connected to a drain of the third MOS tube
M3, a first node A is provided on a connection line between the drain of the first MOS tube M1 and the drain of the third MOS tube M3, and a circuit led out from the node A is connected to the gates of the third MOS tube M3 and the fourth MOS tube M4; a drain of the second MOS tube M2 is connected to a drain of the fourth MOS tube M4, a second node B is provided on a connection line between the drains of the second MOS tube M2 and the fourth MOS tube M4, and the second node B is connected to the output terminal of the first-stage amplification circuit. a gate of the first MOS tube M1 receives the reference voltage, and a gate of the second MOS tube M2 receives a feedback voltage FBOUT, wherein the feedback voltage FBOUT is generated by the output-stage circuit.
In this embodiment, the second-stage amplification circuit comprises a fifth MOS tube M5, a resistor R2, and a resistor R3, the fifth MOS tube M5 is an N-type MOS tube, a gate of the fifth MOS tube M5 is connected to the output terminal of the first-stage amplification circuit, a source of the fifth MOS tube M5 is grounded after being connected to the resistor R3 in series, and a drain of the fifth MOS tube MS is connected to the power supply VDD after being connected to the resistor R2, and the drain of the fifth MOS tube M5 is connected to the output-stage circuit.
An output terminal of a frequency compensation circuit adapting to load changes used in the stabilizer circuit has a constant voltage. When the load current increases, it can be learned by analyzing the output terminal that the voltage of point C decreases. In this case, the current flowing through a sixth MOS tube M6 and a seventh MOS tube M7 increases, and the voltage of point F also increases, that is, the gate voltage of the ninth MOS tube M9 increases, so that the resistance of the ninth MOS tube M9 decreases. As can be learned based on the pole frequency of P1, when the load current increases, the transconductance of the power tube also increases, and P1 moves toward the direction with a higher frequency. As can be learned based on the compensation frequency of the compensation pole-zero point, if the resistance of the ninth MOS tube M9 decreases, the compensation pole-zero point frequency also moves toward 7
BL-5567 . . . . . LU503319 the direction with a higher frequency, as shown in FIG. 8. Therefore, when the load changes, the compensation pole-zero point frequency also changes, to stabilize the circuit.
Compared with a circuit in which a fixed resistance is used as pole-zero point compensation, circuit for adaptive load change in this embodiment uses a MOS tube as an adjustable resistance, and a proper adjustment relationship is created between the circuit and the load current, so that the circuit can automatically adjust the pole-zero point frequency when the load current changes. Therefore, the system can operate stably in different load current conditions, and the premise for a larger current is provided.
The foregoing embodiments are merely intended for describing the technical concept of the present invention, but cannot be used to limit the protection scope of the present invention.
Any changes made to the technical solutions according to the technical concept of the present invention shall fall within the protection scope of the present invention. 8

Claims (4)

BL-5567 LU503319 CLAIMS
1. A stabilizer circuit with a frequency compensation circuit adapting to load changes, comprising: a first-stage amplification circuit, a second-stage amplification circuit, an output-stage circuit, and a frequency compensation circuit adapting to load changes that comprises a compensation capacitor C1, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, and a ninth MOS tube M9, wherein an output terminal of the first-stage amplification circuit is connected to an input terminal of a second-stage circuit, an output terminal of the second-stage circuit is connected to the output-stage circuit, and the frequency compensation circuit adapting to load changes is connected between a second-stage input terminal and a second-stage output terminal; the sixth MOS tube M6 and the seventh MOS tube M7 are P-type MOS tubes, and the eighth MOS tube M8 and the ninth MOS tube M9 are N-type MOS tubes; and the input terminal of the second-stage amplification circuit is connected to one terminal of the compensation capacitor C1 in the frequency compensation circuit adapting to load changes, the second-stage output terminal is connected to a drain and a gate of the sixth MOS tube M6 and a gate of the seventh MOS tube M7, and sources of both the seventh MOS tube M7 and the sixth MOS tube M6 are connected to a power supply VDD; a drain of the seventh MOS tube M7 is connected to a drain and a gate of the eighth MOS tube M8 and a gate of the ninth MOS tube MO, a drain of the ninth MOS tube M9 is connected to the output terminal of the first-stage amplification circuit after being connected to the compensation capacitor C1 in series; and sources of both the eighth MOS tube M8 and the ninth MOS tube M9 are grounded.
2. The stabilizer circuit with a frequency compensation circuit adapting to load changes according to claim 1, wherein the first-stage amplification circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, and a tail current source; the power supply VDD is connected to sources of both the first MOS tube M1 and the second MOS tube M2 through the tail current source, the source of the first MOS tube M1 is connected to the source of the second MOS tube M2, and the first MOS tube M1 and the second 9
BL-5567 LU503319 MOS tube M2 are P-type MOS tubes; a gate of the third MOS tube M3 is connected to a gate of the fourth MOS tube M4, the third MOS tube M3 and the fourth MOS tube M4 are N-type MOS tubes, and sources of both the third MOS tube M3 and the fourth MOS tube M4 are grounded, a drain of the first MOS tube M1 is connected to a drain of the third MOS tube M3, a first node A is provided on a connection line between the drain of the first MOS tube M1 and the drain of the third MOS tube M3, and a circuit led out from the node A is connected to the gates of the third MOS tube M3 and the fourth MOS tube M4; and a drain of the second MOS tube M2 is connected to a drain of the fourth MOS tube M4, a second node B is provided on a connection line between the drains of the second MOS tube M2 and the fourth MOS tube M4, and the second node B is connected to the output terminal of the first-stage amplification circuit.
3. The stabilizer circuit with a frequency compensation circuit adapting to load changes according to claim 2, wherein a gate of the first MOS tube M1 receives the reference voltage, and a gate of the second MOS tube M2 receives a feedback voltage FBOUT, wherein the feedback voltage FBOUT is generated by the output-stage circuit.
4. The stabilizer circuit with a frequency compensation circuit adapting to load changes according to claim 2, wherein the second-stage amplification circuit comprises a fifth MOS tube M5, a resistor R2, and a resistor R3, the fifth MOS tube M5 is an N-type MOS tube, a gate of the fifth MOS tube MS is connected to the output terminal of the first-stage amplification circuit, a source of the fifth MOS tube M5 is grounded after being connected to the resistor R3 in series, and a drain of the fifth MOS tube MS is connected to the power supply VDD after being connected to the resistor R2, and the drain of the fifth MOS tube M5 is connected to the output-stage circuit. 10
LU503319A 2023-01-09 2023-01-09 Stabilizer circuit with frequency compensation circuit adapting to load changes LU503319B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
LU503319A LU503319B1 (en) 2023-01-09 2023-01-09 Stabilizer circuit with frequency compensation circuit adapting to load changes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
LU503319A LU503319B1 (en) 2023-01-09 2023-01-09 Stabilizer circuit with frequency compensation circuit adapting to load changes

Publications (1)

Publication Number Publication Date
LU503319B1 true LU503319B1 (en) 2023-07-10

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LU503319A LU503319B1 (en) 2023-01-09 2023-01-09 Stabilizer circuit with frequency compensation circuit adapting to load changes

Country Status (1)

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