KR980012887A - Clock high-level midpoint detection circuit - Google Patents

Abstract

The present invention relates to a clock pulse detection circuit having an integrator for receiving an input clock signal and integrating and outputting the input clock signal. More particularly, the present invention relates to a clock pulse detection circuit that changes the output of an integrator to a dual state of a steady state and an inverted state, And a spherical waveform generating means for generating and outputting a spherical waveform having a positive minus peak value and a positive waveform having a minus peak value as a substitute for a peak value, and a derivative means for obtaining a derivative value of a middle interval between a peak value and a peak value in a square wave generated by the square- And a detection means for detecting and outputting only a signal which is input to a portion corresponding to a high state other than the clock signal among the signals output from the differential means for each section by receiving the signal output from the differential means for each section A high-level midpoint detection circuit including a clock, There is no circuit for detecting the midpoint of the level and there is no circuit for detecting the midpoint where the hold time of the device is at the high level so that even if the hold time of the device is shorter than the middle point of the high level, There is an effect of solving a problem that has not been achieved.

Description

Clock high-level midpoint detection circuit

FIG. 1 is a block diagram of a conventional circuit for detecting the stability of a pulse

FIG. 2 is a block diagram of a high-level midpoint detection circuit for a clock according to the present invention;

FIG. 3 is an exemplary waveform for the main part of FIG. 2; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

10: integrator 20: buffer 30: retarder

40: adder 50: zero point detector AND: AND gate

The present invention relates to a pulse detection circuit and, more particularly, to a method of detecting a pulse edge, not a method of detecting a previous pulse edge. Level midpoint detection circuit for detecting a high-level midpoint.

In general, any device will typically receive a clock pulse for its own operation, which is a key factor in increasing the reliability and lifetime of the device.

For this reason, many detection circuits for recognizing the stability of the generated state of the clock pulse have been proposed. Among them, a circuit for detecting the pulse edge is used. Referring to FIG. 1, the structure of the detection circuit is as follows.

The conventional pulse edge detection circuit comprises an integrator 1 for integrating an input pulse signal, a delay 2 for delaying the output of the integrator 1 for a predetermined time, And a logic gate (XOR) for exclusive-ORing the output signals of the integrator (1) and the delay circuit (2) and outputting the calculated value.

In the above configuration, the delay unit 2 inverts the current output signal only when the clock signal rate of the integrator 1 exceeds the predetermined threshold range set by the input of the clock signal rate of the integrator 1, thereby repeating the above- And an inverter 2B for inverting and outputting a signal output from the shimmer trigger 2A.

The conventional pulse edge detection circuit configured as described above is characterized in that a phase of an original input pulse signal is compared with a phase of a delayed signal in a logic gate (XOR) to find an edge of a pulse. It is difficult to verify the stability of the pulse to be used in the case of a device with a level sensor which is a time-critical parameter.

In addition, if the hold time of the device is shorter than the midpoint of the high level, it is possible to speed up the system so that clock doubling is not a problem in terms of operation of the device, but conventionally, There is a problem in that it is not possible to provide an automatic judgment criterion.

An object of the present invention to solve the above problem is to provide a high level intermediate detection circuit for detecting a midpoint of a high level of a pulse so that the stability of an input pulse can be detected even in a level sensitive device have.

According to an aspect of the present invention, there is provided a clock pulse detection circuit including an integrator that receives an input clock signal and integrates and outputs an input clock signal, wherein the output of the integrator is divided into a normal state and a reversed state And a generating unit for generating and outputting a square wave having the same period as the input clock and having a value corresponding to a maximum value as a plus and minus peak value, A differential signal generating means for generating a differential signal by multiplying the output signal of the differential signal generating means by the differential signal output from the differential signal generating means, And detecting means for detecting and outputting only the clock signal and the signal corresponding to the portion corresponding to the high state.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram of a high-level midpoint detection circuit according to the present invention. The integrator 10 integrates an input clock signal. A buffer 20, which inverts or non-inverts the output of the integrator 10, A delay unit 30 for receiving and delaying the output of the inverted signal from the buffer 20 and a delay unit 30 for receiving a signal output from the delay unit 30 and a non- And an adder 40 for adding and synthesizing the signals. A zero point detector (50) for detecting a position where a magnitude of a signal becomes zero in a signal output from the adder (40) and generating a force force signal in a high state. And a slew gate (AND) for performing an AND operation on the clock signal input to the integrator (10) and the output signal of the zero point detector (50) and outputting the calculated value.

The buffer 20 receives the output signal of the buffer 20 at the inverted data input terminal thereof, receives the output of the integrator 10 at the non-inverted data input terminal, inverts the signal output from the integrator 10 A first buffer OP1 for receiving the output signal of its own from the non-inverted data input unit feedback, inverting the signal output from the integrator 10 by receiving the output of the integrator 10 at the inverted data input, And a second buffer OP2.

A preferred operation example of the high-level midpoint detection circuit according to the present invention will be described with reference to FIG.

FIG. 3 is an illustration of an input / output waveform for a main part of each configuration shown in FIG. 2; FIG.

When a clock pulse as shown in FIG. 3 (a) is input to the integrator 10. The integrator 10 integrates and outputs it. The signal output from the integrator 10 is not inverted in the first buffer OPI but comes in a waveform as shown in FIG. 3 (B), whereas in the second buffer OP2, And outputs a signal inverted to the output signal of the first buffer OP1 as shown in FIG. 3 (c).

The signal output from the twenty-first buffer OP2 is delayed in phase through the delay unit 30 to output a delayed signal as shown in FIG. 3 (d). The phase difference of the delayed signal shows a difference of 90 degrees with respect to the original signal.

The signal output from the first buffer 0P1 (see FIG. 3B) and the signal output from the delay unit 30 (see FIG. 3D) are synthesized by the adder 40, And outputs a delayed signal as shown in FIG. 3 (e).

The signal output from the adder 40 is converted into a predetermined number of impulse signals (see also FIG. 3 (b)) through the zero point detector 50 and output.

At this time, the signal output from the zero point detector 50 is provided as one input to the end gate (AND), and the other input terminal of the AND gate (AND) receives the original clock pulse 3) (see also Fig.

Therefore, the output signal of the end gate (AND) is shown in FIG. 3 (b), in which only the impulse signal of the portion of the impulse signal output from the zero point detector 50 is logically multiplied with the high state of the clock pulse And is output in the form as it is.

According to the present invention, there is no circuit for detecting a midpoint of a high level of a clock pulse, so that the hold time of the device is a high level and a time shorter than the increment point There is a problem of solving the problem that the clock doubling is not reliable.

Claims (7)

And a clock pulse detection circuit for converting the output of the integrator into a normalized state and an inverted state and outputting an output signal having a period equal to that of the input clock, A square wave generating means for generating and outputting a square wave having a value between a plus and a minus peak, and outputting a square wave having a value between plus and minus peaks; and a section-by-section differentiating means for obtaining a derivative value of an intermediate section between the perc value and the peak value, And detecting means for detecting and outputting only a signal corresponding to a portion corresponding to a high state of the clock signal among the signals output from the section-by-interval differentiating means, Wherein the clock signal is a clock signal. The method of claim 1, Wherein the square wave generating means comprises: buffering means for inverting and noninverting the output of the integrator; delay means for receiving and delaying the inverted signal among the signals output through the buffering means; And an adder for adding and combining a signal output from said delay means and a signal output from said delay means. 3. The apparatus according to claim 1 or 2, wherein the section differentiating means comprises zero point detecting means for detecting a position at which a magnitude of a signal is zero in a signal output from the adder and generating a specific signal Clock high-level midpoint detection circuit. The high-level midpoint detection circuit according to claim 3, wherein the signal output from the zero point detection means is a force pulse signal in a high state. 2. The method as claimed in claim 1, wherein the position of the differential value obtained by the section-by-section differentiating means is substituted for a place where the middle of each of the high and low sections of the input clock of the constant- Detection circuit. The method of claim 1, Wherein the buffering means comprises: a first buffer for receiving a feedback signal of its own output signal at an inverted data input terminal, receiving the output of the integrator at an obesity data input terminal and outputting the inverted signal without inverting; And a second buffer for receiving a feedback input at an inverted data input terminal, receiving the output of the integrator at an inverted data input terminal, inverting a signal output from the integrator, and outputting the inverted signal. The apparatus as claimed in claim 1 or 5, wherein the detecting means comprises an AND gate for receiving a differential value obtained from the section-by-section differentiating means and a clock signal input to the integrator, performing an AND operation and outputting the calculated value Characterized in that the high-level midpoint detection circuit of the clock. ※ Note: It is disclosed by the contents of the first application.