KR980012254A - Device isolation method of semiconductor device - Google Patents

Abstract

The present invention forms a trench using a material film having an etching rate similar to that of a semiconductor substrate having a thickness of about 80% to 100% of the depth of a trench to be formed in a device isolation method of a semiconductor substrate. Therefore, by using the material layer as an etch mask in the process of etching the substrate for trench formation, the material layer is also etched at a similar etching rate to terminate the etching of the interface of the other material layer under the material layer. Thus, the depth of the trench can be uniformly formed in every trench forming process. Based on these results, the following planarization process can be performed stably and an advantage that the step between the active region and the field region can be removed can be obtained.

Description

Device isolation method of semiconductor device

The present invention relates to a device isolation method of a semiconductor device, and more particularly to a method of forming a trench in a trench type device isolation method.

As semiconductor devices become more and more highly integrated, the spacing between elements becomes narrower and the possibility of electrical contact between elements becomes even higher. Therefore, electrical isolation between semiconductor elements, for example between memory cells, becomes more important.

Accordingly, a variety of device isolation structures and methods for separating devices have been proposed. For example, there are a LOCOS type and a trench type device isolation method, which are typical in the conventional device isolation method. The LOCOS type is a very useful device isolation method when the integration degree is not considered to a great extent. However, as in the present high integration state, the active region which is the device formation region is largely invaded by the bird's beak. As a result, the active region is narrowed, resulting in a high integration degree. The trench type can form a trench having a predetermined depth in a semiconductor substrate and then form an oxide film for element isolation in a trench. The oxide trench can be formed in a narrow space at a narrow interval. Buzz beaks are not formed as in the LOCOS type, There are advantages to be able to. What should be considered in the process of forming the trench type is to form the trench having a constant depth uniformly in the semiconductor substrate. Currently, the etch method used to form such a trench is time etching, which is time-based etching. This method is very effective because it requires accurate measurement of the etching time. However, this method requires that the etching equipment used be exactly the same from the preparation of the etching to the end of the etching. In actual processes, the state of the equipment changes slightly. Therefore, the etching rate per unit time, that is, the etch rate, is changed in each etching process. Therefore, the depth of the trench may slightly vary depending on the wafer. If the depth of the trench is changed, a good flat surface can not be obtained in the planarization process performed after forming the device isolation film filling the trenches. In this connection, reference is made to Figs. 1 to 3 showing the relationship between the depth of the trench formed in the semiconductor substrate and the flatness of the insulating film.

In FIGS. 1 to 3, (a) and (b) show a case where a trench is formed at a normal depth in the semiconductor substrate 10 and a case where a trench is formed at a normal depth. And (c) shows a case where the depth is shallower than the normal depth. 1 is a step of forming trenches 12a, 12b, and 12c in a semiconductor substrate 10. In FIG. Reference numeral 14 in FIG. 1 is a reference line introduced for convenience of comparison of trench depths in FIGS. (A) to (c) and is based on the trench depth of FIG. 2 is a step of forming an insulating film 16 filling the trenches 12a, 12b, and 12c. The trenches 12a, 12b, and 12c are formed sufficiently to fill and remain. 3, the entire surface of the insulating film 16 is planarized using an etch-back method or a chemical mechanical polishing (CMP) method. The flatness of the trenches 12a, 12b, and 12c varies in the planarization process. That is, in the case where the depth of the trench is deeper than the normal depth, the flat surface is formed to be lower than the upper end of the trench 12a by the planarization process in (a). When the trench is formed at a normal depth, the flat surface is formed to be the same as the top of the trench 12b. When the trench is formed shallower than the normal depth, it can be seen that the flat surface is formed to be higher than the upper end of the trench 12c in the view (c). (a) and (c), the stepped coverage of various patterns is not good because the flat surface forms a high step in the subsequent many thin film forming processes.

A method of using a trench in a device isolation method of a semiconductor device according to the prior art will be described in detail with reference to the accompanying drawings. FIGS. 4 to 13 are diagrams showing steps of a trench type element isolation method of a conventional semiconductor device. 4 is a step of forming first and second insulating films 22 and 24 used as an etching mask. Specifically, the first and second insulating films 22 and 24 having different physicochemical properties are formed on the semiconductor substrate 20. Specifically, first and second insulating films 22 and 24 having different physicochemical properties are sequentially formed on the semiconductor substrate 20. The first insulating film 22 is used as an etching mask in the process of forming the trenches. The second insulating film 24 is a film for protecting the first insulating film 22 in the trench forming process. The first insulating film 22 is formed of a nitride film (SiN), and the second insulating film 24 is formed of an oxide film.

FIG. 5 is a step of forming a photoresist pattern defining regions to form trenches. Specifically, a photoresist film is formed on the entire surface of the second insulating film 24, and then the photoresist pattern 26 is patterned so that the interface of the second insulating film 24 exposes a predetermined region. Since the trenches are formed in the semiconductor substrate corresponding to the regions defined by the photoresist patterns 26, the photoresist patterns 26 eventually define the regions in which the trenches are to be formed.

6 is a step of forming the first and second insulating film patterns 22a and 24a. Specifically, the entire surface of the second insulating film 24 is anisotropically etched using the photoresist pattern 26 as an etching mask. At this time, the anisotropic etching is performed until the limited portion of the first insulating film 22 is removed and the interface of the substrate is exposed. As a result of the anisotropic etching, the first and second insulating film patterns 22a and 24a, in which portions defined by the photoresist pattern are removed, are formed. The photoresist pattern 26 is then removed. As a result, the first and second insulating film patterns 22a and 24a define the trench region, that is, the field region. Accordingly, the active region is naturally limited. The active region is a portion where the first and second insulating film patterns 22a and 24a are formed.

7 is a step of forming the trench 28 in the semiconductor substrate 20. [ Specifically, a limited portion of the semiconductor substrate 20 is anisotropically etched using the first and second insulating film patterns 22a and 24a as an etching mask to form a trench 28 having a predetermined depth in the semiconductor substrate 20. [ The anisotropic etching is performed by setting the depth of the trench in advance by time etching, estimating the etching time in consideration of the etching of the substrate material, and then performing the etching according to the time. However, such a time etch can vary the depth of the trench formed for the reasons described above. Therefore, the subsequent planarization process can be made unstable.

Subsequently, the resultant is heat-treated to form a thermal oxide film 30 on the inner wall of the trench 28 (FIG. 8). Next, a third insulating film 32 filling the trench 28 is formed on the entire surface of the semiconductor substrate 20a on which the trench 28 is formed (FIG. 9). The third insulating film 32 is used as an insulating film for element isolation. A first photoresist pattern 34 is formed on the entire surface of the third insulating layer 32 to define a trench region (FIG. 10). The third insulating film 32 is anisotropically etched using the first photoresist pattern 34 as an etching mask to form a third insulating film pattern 32a having a step between the active region and the trench region (FIG. 11).

12 is a plan view for planarizing the entire surface of the resultant product. Specifically, the entire surface of the third insulating film pattern 32a is planarized by etch back or CMP. In the planarization process, the third insulating film pattern 32a and the second insulating film pattern 24a are completely removed, and the first insulating film pattern 22a remains only a thin thickness.

13 is a step for completing the trench isolation. Specifically, in FIG. 12, the first insulating film pattern 22a is stripped by wet etching. As a result, in the active region, the insulating film is completely removed and an insulating film remains only in the trench 28, so that a complete trench type device isolation film is formed. The device isolation layer is formed differently depending on the depth of the trench as shown in FIGS. 1 to 3. The device isolation film shown in Fig. 13 is normally formed.

As described above, in the conventional device isolation method for a semiconductor device, time etching is performed to form a trench on a semi-solid substrate. Therefore, the etch rate may be varied depending on the state of the etching equipment, and trenches having different depths may be formed in each wafer. If the depth of the trench is changed, the planarization process proceeds unstably after filling the trench with the insulating material.

It is therefore an object of the present invention to provide a device isolation method of a semiconductor device which can uniformly form a trench having a constant depth and can easily confirm the depth of the trench in order to solve the above problems.

FIGS. 1 to 3 are views showing the relationship between the depth of the trench formed in the semiconductor substrate and the flatness of the insulating film.

FIGS. 4 to 13 are diagrams showing steps of a trench type element isolation method of a conventional semiconductor device.

FIG. 14 through FIG. 23 are diagrams showing steps of a trench type element isolation method of a semiconductor device according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

20a: semiconductor substrate 28: element isolation insulating film

40: Third insulating film

In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention comprises:

A method for isolating elements in a semiconductor device, the method comprising: forming an etch endpoint detection layer (hereinafter referred to as an EPD layer) formed on a semiconductor substrate and a trench formed on the EPD layer A material film having an etch rate similar to that of the semiconductor substrate is formed as an etch mask.

The EPD layer is formed of a single layer or a plurality of insulating films. For example, the plurality of insulating films may be formed of two insulating films, which are referred to as first and second insulating films. The material film is formed of an insulating film (hereinafter referred to as a third insulating film). The third insulating film is formed of an undoped polysilicon film. The thickness of the material film is formed differently depending on the depth of the trench. The thickness of the material layer is preferably about 80% to about 100% of the trench depth. The material film is etched together during the formation of the trench. However, if the material film remains after forming the trench, it may be removed by over-etching,

Forming a thermal oxide film on the inner wall of the trench; Forming an insulating film (hereinafter referred to as a fourth insulating film) filling the trenches on the front surface of the semiconductor substrate on which the trenches are formed; And planarizing the entire surface of the fourth insulating film.

In the planarization step, etch back or CMP is used as the planarization means. The present invention forms a trench in a semiconductor substrate by an end point detection (EDP) method instead of a time etch. An etch mask is used to prevent the active region from being etched by the trench in the trench formation process. The etch mask is added to the multi-layer insulating film composed of the oxide film and the nitride film as in the conventional etch mask, Lt; RTI ID = 0.0 > a < / RTI > etch rate. Therefore, even if the etching rate is changed by the change of the state of the etching equipment, the depth of the trench can be uniformly formed in each etching process, so that the subsequent planarization process of the insulating film can be performed stably. As a result, the height of the device isolation film filling the trench can be made equal to the height of the trench, and the flatness of the resultant surface can be maintained until the subsequent thick film process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a device isolation method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings described below, the same reference numerals as those used in describing the prior art represent the same members.

FIGS. 14 to 23 are views showing steps of a trench type element isolation method of a semiconductor device according to an embodiment of the present invention. 14 is a step of forming the material film 40. Fig. Specifically, a multi-layer insulating film composed of a first insulating film 22 formed of a nitride film and a second insulating film 24 formed of a high temperature oxide film (HTO) is formed on the entire surface of the semiconductor substrate 20, A material film 40 having an etching rate similar to the etching rate of the semiconductor substrate 20 is formed on the entire surface of the second insulating film 24. The material film 40 is formed of an insulating film (hereinafter referred to as a third insulating film). The second insulating film 24 of the multilayer insulating films 22 and 24 is used as an EPD layer. The third insulating film 40 plays a very important role in forming a trench in a trench forming process. That is, the depth of the trench is determined by the thickness of the third insulating film 40. Therefore, the depth of the trench to be formed must be determined before forming the third insulating film 40. In order to determine the depth of the trench using the thickness of the third insulating film 40, the etching process should be stopped after the third insulating film 40 is etched. That is, there must be means to detect the etch end point. For this purpose, the second insulating film 24 is used. Therefore, when the third insulating layer 40 is etched to expose the interface of the second insulating layer 24, the etching process is stopped, and the semiconductor substrate 20a is exposed with a trench having a depth corresponding to the thickness of the third insulating layer 40, .

In order to use the third insulating layer 40 as a means for determining the depth of the trench, the etching rate of the third insulating layer 40 should be similar to that of the semiconductor substrate 20, as described above. In order to heighten such a condition, the third insulating film 40 should be formed using a material for forming the semiconductor substrate 20. [ For example, if the material forming the semiconductor substrate 20 is silicon, the third insulating film 40 is also formed using a material formed of a silicon component. However, the silicon used for forming the third insulating film 40 should not be doped with conductive impurities. This is because the etching rate of the third insulating film 40 is changed according to the amount of the doping concentration. The third insulating film 40 should be removed by both the transient etching and the trench inner wall oxidation process to be performed later. Thus, the thickness of the formation can be as thin as 80% of the depth of the trench to be formed and up to 100% of the depth of the trench to be formed.

15 is a step of defining an active area and a field area. Specifically, the photoresist pattern 42 is formed on the entire surface of the third insulating film 40 and spaced apart from the photoresist pattern 42 by a predetermined distance. The portion covered by the photoresist pattern 42 is an active region to be protected in the etching process and the portion exposed by the photoresist pattern 42 is a field region to be etched.

16 is a step of exposing the interface of the semiconductor substrate 40 corresponding to the field region. Specifically, portions of the third insulating film 40 and the second and first insulating films 24 and 22 defined by the field region are sequentially etched using the photoresist pattern 42 as an etching mask. As a result, the interface of the portion of the semiconductor substrate 40 which is not defined by the photoresist pattern 42 is exposed, and the active region is exposed through the third insulating film pattern 40a and the first and second insulating film patterns 22a , 24a.

17 is a step of forming a trench 28 in the semiconductor substrate 20. [ Specifically, the entire surface of the final product of FIG. 16 is dry-etched. The third insulating film pattern 40a on the upper layer among the insulating film patterns defining the active region in the etching process is gradually etched and the field region of the semiconductor substrate 20a is also gradually etched. The etching is terminated when the interface of the second insulating film pattern 24a used as the EPD means is detected. When the etching is completed, a trench 28 having a depth corresponding to the thickness of the third insulating film pattern 40a is formed in the field region of the semiconductor substrate 20a. Since the third insulating film pattern 40a is formed of a material similar to the material forming the semiconductor substrate 20a, the third insulating film pattern 40a and the semiconductor substrate 20a are similar to each other even if the etching rate of the etching equipment is changed. It is possible to form the trench 28 with a similar depth because it is etched to the fullest extent. Although not shown, the third insulating film pattern 40a may be partially left on the second insulating film pattern 24a without being completely removed after the trench 28 is formed. The third insulating layer pattern 40a may be completely removed in a subsequent transient etching for a short time.

Figs. 18 to 21 show the same steps as those of Figs. 8 to 11 showing the steps of the device isolation method according to the prior art. That is, a thermal oxide film 30 is formed on the inner wall of the trench 28 (FIG. 18). If the third insulating film pattern (40a in FIG. 16) remains on the second insulating film pattern 24a in the process of forming the thermal oxide film 30, it is formed as an oxide film (not shown). Such an oxide film can be completely removed in the subsequent planarization process. Subsequently, a thick insulating film 32 (hereinafter referred to as a "fourth insulating film") is formed on the entire surface of the final product of FIG. 18 (FIG. 19). Next, a first photoresist pattern 34 is formed on the fourth insulating film 32 to define a field region (FIG. 20). The entire surface of the fourth insulating film 32 is anisotropically etched using the first photoresist pattern 34 as an etching mask, and then the first photoresist pattern 34 is removed. The thickness of the fourth insulating film 32 at the portion corresponding to the active region of the fourth insulating film 32 becomes extremely thin by the anisotropic etching (FIG. 21).

22 is a planarization step. Specifically, the entire surface of the final product of FIG. 21 is planarized by an etch-back or CMP method. The planarization completely removes the fourth insulating film 32 and the second insulating film pattern 24a on the active region and also removes the first insulating film pattern 22a to a certain thickness. At this time, an oxide film (not shown) formed by the third insulating film pattern 40a (FIG. 16) formed on the second insulating film pattern 24a is also removed. On the field region, a fourth insulating film pattern 32a having the same height as the first insulating film pattern 22a formed on the active region by the planarization process is formed. The fourth insulating film pattern 32a is an element isolation insulating film which substantially fills the trench 28. [

23 is a step of removing the first insulating film pattern 22a formed on the active region. Specifically, the first insulating film pattern 22a defining the active region is removed by wet etching in the final product of FIG. After the drying process, the semiconductor substrate 20a is completely separated into the active region and the field region. The field region is filled with an element isolation insulating film, which is the fourth insulating film pattern 32a. As can be seen from FIG. 23, a step difference is hardly formed between the active region and the field region. Therefore, the following thin film process will not cause problems due to at least the step difference. This is because the depth of the trench formed in the semiconductor substrate can be excluded from the influence of the etching equipment by using a separate insulating film.

As described above, the element isolation method of a semiconductor device according to the present invention forms a trench in a semiconductor substrate by the EDP method instead of the time etching. As an etching mask used to perform the EDP, an etching mask is used to prevent the active region from being etched by etching in the trench formation process. The etch mask is formed by a trench in a multilayer insulating film composed of an oxide film and a nitride film, A material layer having an etching rate similar to that of the semiconductor substrate to be formed is further used.

Therefore, even if the etching rate is changed by the change of the state of the etching equipment, the depth of the trench can be uniformly formed in each etching process, so that the subsequent planarization process of the insulating film can be stably performed. As a result, the height of the element isolation insulating film filling the trench can be made equal to the height of the trench, and the flatness of the resultant surface can be maintained until the subsequent thick film process.

It is obvious that the present invention is not limited to the above embodiments and that many modifications can be made by those skilled in the art within the technical scope of the present invention.

Claims (10)

A method for isolating elements in a semiconductor device, the method comprising: forming an etch endpoint detection layer (hereinafter referred to as an EPD layer) formed on a semiconductor substrate and a trench formed on the EPD layer Wherein a material film having an etch rate similar to that of the semiconductor substrate is formed as an etch mask. The device isolation method according to claim 1, wherein the EPD layer is sequentially formed of a first insulating film and a second insulating film as a multilayer. The method according to claim 2, wherein the first and second insulating films are formed of a nitride film (SiN) and a high-temperature thermal oxide film (HTO), respectively. The device isolation method according to claim 1, wherein the thickness of the material film is formed to be similar to the depth of the trench. The method of claim 1, wherein the thickness of the material layer is about 80% to about 100% of the depth of the trench. The method of claim 1, wherein the material film is etched together with the trenches during the formation of the trenches. The device isolation method according to claim 1, wherein when the material film remains after forming the trench, excessive etching is performed to remove the material film. 8. The method of claim 7, further comprising: forming a thermal oxide film on the inner wall of the trench when the material film remains after forming the trench; Forming a fourth insulating film on the front surface of the semiconductor substrate on which the trench is formed, the fourth insulating film filling the trench; And planarizing the entire surface of the fourth insulating film. The method according to any one of claims 1 to 8, wherein the material film is formed of a third insulating film. 10. The method according to claim 9, wherein the third insulating film is formed of an undoped silicon film. ※ Note: It is disclosed by the contents of the first application.